1. Perform logic synthesis using chiptop design
2. Use following timing constraints
set PERIOD 3.0
set INPUT_DELAY 1.0
set OUTPUT_DELAY 1.0
set CLOCK_LATENCY 1.0
set SOURCE_LATENCY 1.0
set UNCERTAINTY 0.15
set MAX_TRANSITION 0.5
set MIN_CLOCK_LATENCY 0.5
set MIN_SOURCE_LATENCY 0.5
set MIN_IO_DELAY 0.5
every output drive 10 Inverters in next stage
every input driven by least drive strength Inverter, except clk and reset.
3. Reports for Timing, Area, Power and QoR.
Design: chiptop
Technology:
14nm
EDK
Frequency
150 Mhz
Corners
ff0p88v25c
tt0p8v125c
Jitter
150 ps
Wire Load
35000
Skew
350 ps
ns
ns
Number of violating
paths
Total negative slack
Worst negative slack
Cell
Name
Power
-
Dynamic Power
Leakage Power
Design: chiptop
Technology:
14nm
EDK
Frequency
150 Mhz
Corners
ff0p88v25c
tt0p8v125c
Jitter
150 ps
Wire Load
35000
Skew
350 ps
Total negative slack
Number of violating
paths
Max
Worst negative slack
Cell
Power
0
0
0
Dynamic Power
0
Leakage Power
0
0
0