L6 In Class Assignment – TimerA
Names _______________________________________________________________________________
1. Write an instruction that sets a Boolean variable called IsSwitchPressed true if pin P1.4 (configured
as an input) is being driven low.
isSwitchPressed = ((P1IN & 0x10) == 0);
2. The system clock in the MSP432 can range in frequency from 1MHz to 48MHz. The SMCLK is a
quarter of the configured system clock. Find the minimum and maximum periods that TimerA can be
configured for when using SMCLK as the clock input. Show all work.
TimerA has a maximum count of 65536 and a minimum count of 1.
Configured for 1MHz we can find the longest delay, since 1MHz is the slowest time.
Formula:
Time = counts * N/(frequency)
Time = 65536 * (largest clock division)/(smallest frequency/4)
//SMCLK is ¼ master clock
Time = 65536 * (64)/250kHz
Timer = 16.777 Seconds
Configured for 48MHz we can find the shortest delay, since 48MHz is the faster frequency
Time = counts * N/(frequency)
Time = 1 * (smallest clock division)/(largest frequency/4)
Time = 1 * 1/(12MHz)
Time = 83.333 ns
3. Calculate the smallest clock divider that can be used to create a delay of 30ms. Assume an SMCLK of
12MHz.
Time = counts * N/(frequency)
30 ms = 65536 * (N)/(12MHz)
N = (30ms*12MHz)/65536
N = 5.493. No divider is available for 5.493 so need to round up to 6.
ID = 2, TAIDEX = 3
4. Configure TimerA3 to create an output PWM signal that has a period of 500us and a 40% duty cycle.
Assume a SYSTEM CLOCK of 48MHz and use UP mode. Use smallest divider possible.
Complete the following register write instructions, you may write each register directly, no bit
masking required for this problem. If you do not use a register fill it in with N/A. Show all of your
work.
TA3CTL
= _______0x0210____________//configures SMCLK with divider of 1 in UP MODE
TA3R
= _______0x0000____________ //start count at zero
TA3CCTL1 = _______0x00E0____________ //output configured for reset/set mode
TA3CCR0 = _______5999____________ //6k – 1 to include 0
TA3CCR1 = _______2399____________ // (40% of 6k) -1
TA3EX0
= _______0x0000____________ // no additional clock division needed
Time = counts * N/(frequency)
500us = counts * 1/12MHz
Counts = 6000
Since 6000 < 65536 there is no need to change the clock scaler
5. Configure TimerA1 to create a delay of 20ms. Assume a SYSTEM CLOCK of 48MHz and use
continuous mode. Use smallest divider possible.
Complete the following register write instructions, you may write each register directly, no bit
masking required for this problem. If you do not use a register fill it in with N/A. Show all of your
work.
20 ms = 65536 * (N)/(12MHz) -> N = 4
TA1CTL
= ______0x02A0_____________//configures SMCLK with divider of 4 in continuous mode
TA1R
= ______0x0000_____________ //start count at zero
TA1CCTL1 = ______N/A_____________
//no output generated
TA1CCR0
= ______59999_____________ //60k – 1 to include 0
TA1CCR1
= ______N/A_____________
TA1EX0
= ______0x0000_____________// no additional clock division needed
//No need for 2 CCRs
Time = counts * N/(frequency)
20ms = counts * 4/12MHz
Counts = 60,000
Since 60000 < 65536 there is no need to change the clock scaler