FPGA Based Design
EE-410
Lab: 11
Date of Submission:
May-10-2023
Title:
Implementation of transmitter in UART
Students’ Names:
Abdullah Basit
M. Sheraz
M. Huzaifa
Teacher:
Batch:
BSEE 2020-24
Semester:
6th
Dr. Shahid Nazeer
Lab Invigilator :
 Mr Zubaid
 Miss Arham
Department of Electrical Engineering
Contents
1.
Abstract : ...................................................................................................................................................................... 3
2.
Objective : .................................................................................................................................................................... 3
3.
Equipment : .................................................................................................................................................................. 3
4.
Background : ................................................................................................................................................................ 3
5.
Introduction : ............................................................................................................................................................... 3
6.
UART Transmitter : .................................................................................................................................................. 4
7.
Block diagram of Transmitter :..................................................................................................................................... 4
8.
State Diagram :............................................................................................................................................................. 4
9.
Code : ........................................................................................................................................................................... 5
10.
Simulation Result : ................................................................................................................................................... 6
11.
Hardware Implementation : .................................................................................................................................... 7
12.
Discussion : .............................................................................................................................................................. 9
13.
Conclusion : ............................................................................................................................................................. 9
14.
Reference : ............................................................................................................................................................... 9
2
1.
Abstract :
The UART transmitter core is an essential component of communication systems in embedded devices. It allows the
device to transmit data to other devices using a standard serial communication interface. The core includes a FIFO
buffer to store the data that needs to be transmitted, which ensures that the data is transmitted in a timely and
efficient manner. The baud rate generator is used to set the transmission speed, and the start and stop bits are
added to each byte of data to ensure proper synchronization between the transmitting and receiving devices. The
UART transmitter core is designed using hardware description languages like Verilog or VHDL, which enables the
design to be synthesized using tools like Xilinx ISE. The simplicity, low overhead, and flexibility of the UART protocol
make it a popular choice in the industry for communicating with other devices over serial interfaces.
2.
Objective :
The objective is as follows.

State diagram of UART

Test bench of UART

Implementation on FPGA
3.


4.
Equipment :
laptop
Xilinx
Background :
The Universal Asynchronous Receiver Transmitter (UART) protocol is widely used in embedded systems to transmit
and receive data over serial communication channels due to its simplicity, reliability, and wide support. Designing
and implementing a UART transmitter core using tools like Xilinx ISE is a crucial task in digital circuit design for
embedded systems. The core includes a FIFO buffer to store data, a baud rate generator to set the transmission
speed, and logic to add start and stop bits for synchronization between devices. The ability to simulate and
synthesize digital circuits using tools like Xilinx ISE provides a powerful means of testing and verifying the
functionality of the UART transmitter core. This lab report aims to present the design and implementation of a UART
transmitter core using Xilinx ISE, covering various aspects such as design flow, simulation, synthesis, testing, and
verification, and exploring the limitations and trade-offs involved in designing a UART transmitter core.
5.
Introduction :
This lab report focuses on the design and implementation of a UART transmitter core using Xilinx ISE, a commonly
used tool in the digital design industry. The UART protocol is widely used in embedded systems to transmit and
receive data over serial communication channels due to its simplicity, reliability, and wide support. The core is
designed using Verilog, which is a popular hardware description language, and simulated using Xilinx's ModelSim.
The design is then synthesized to generate the bitstream file for programming onto an FPGA board. The primary
objective of this lab is to provide practical experience in designing and implementing a UART transmitter core,
covering various aspects such as design flow, simulation, synthesis, testing, and verification of the functionality using
an FPGA board. Additionally, the lab also aims to explore the limitations and trade-offs involved in designing a UART
transmitter core, including the impact of clock speed and data rate on the system's performance.
3
6.
UART Transmitter :
The UART transmitter core is an essential component of the UART communication system, responsible for
converting parallel data into serial data that can be transmitted over a communication channel using the UART
protocol. It is composed of various sub-modules, including a data serialize, a baud rate generator, and a start/stop
bit generator. The data serialize is responsible for converting parallel data into a serial bit stream, which is then
transmitted one bit at a time over the communication channel. The baud rate generator generates a clock signal
that determines the transmission speed of the data. The start/stop bit generator adds a start bit and one or two
stop bits to each byte of data, which are used to synchronize the receiver and indicate the start and end of each
byte. The transmitter core is typically implemented using hardware description languages such as Verilog or VHDL,
which enable efficient design and simulation of digital circuits. It can be synthesized and programmed onto an FPGA
or ASIC for use in embedded systems. The transmitter core is an integral part of the UART communication system
and is widely used in various applications such as serial communication between microcontrollers and sensors, and
communication between PCs and peripheral devices.
7.
Block diagram of Transmitter :
8.
State Diagram :
4
9.
Code :
Code
Test Bench 1 (Task)
module uat_top(clk_x, rst_p, din_rdy, din_byte,
ser_out);
input clk_x;
input rst_p; //1-bit Asyncronous Active Low Reset
input
input din_rdy; //1-bit ready input signal that indicates
the data is
ready at input for Tx
input [7:0] din_byte; //8-bit data input in UART for Tx
output reg ser_out; //1-bit Tx data output from UART
reg din_rdy_reg; // 1-bit serial data from channel
reg [2:0] shift_count;
reg [7:0] data_buf;
wire start_bit_sig, data_bits_sig, stop_bit_sig; // Bit
Insertion Control Signal
Generated from State Machine
// Registered Data Ready Signal
always @(posedge clk_x or posedge rst_p)
begin
if(rst_p)
din_rdy_reg <= 1'b0;
else
din_rdy_reg <= din_rdy ;
end
//Output Logic
always @(posedge clk_x or posedge rst_p)
begin
if(rst_p)
ser_out <= 1'b1;
else
begin
case({start_bit_sig, data_bits_sig, stop_bit_sig})
3'b100:
ser_out <= 1'b0;
3'b010:
ser_out <= data_buf[0];
3'b001:
ser_out <= 1'b1;
default:
ser_out <= 1'b1;
endcase
end
end
//Start Bit Pipelining
always @(posedge clk_x or posedge rst_p)
begin
module uat_t ();
5
reg clk_x;
reg rst_p;
reg din_rdy;
reg [7:0] din_byte;
wire ser_out;
uat_top m1 (clk_x, rst_p, din_rdy, din_byte, ser_out);
initial
begin
clk_x = 0;
din_byte = 8'b11001010;
din_rdy = 0;
rst_p = 1;
#15 din_rdy = 1;
#15 rst_p = 0;
end
always #10 clk_x = ~clk_x;
initial #500 $stop;
endmodule
if(rst_p)
data_buf <= 8'd0;
else if(start_bit_sig)
data_buf <= din_byte; // at just arriving the
start_bit_sig , we load
data into data_buffer
else if(data_bits_sig)
data_buf <= {1'b1,data_buf[7:1]};
else
data_buf <= data_buf;
end
// Counter that Count Shift in Data Buffer Logic
always @(posedge clk_x or posedge rst_p)
begin
if(rst_p)
shift_count <= 3'd0;
else if(data_bits_sig)
shift_count <= shift_count + 1; //Counter will start
when
"data_bits_sig" flag is High
else
shift_count <= 3'd0;
end
// State Machine for Tx
uat_sm uat_sm_inst( .clk_x(clk_x), .rst_p(rst_p),
.din_rdy(din_rdy_reg),
.shift_count(shift_count),
.start_bit_sig(start_bit_sig),
.data_bits_sig(data_bits_sig),
.stop_bit_sig(stop_bit_sig) );
endmodule
10.
Simulation Result :
Figure 1: UART
6
11. Hardware Implementation :
Code
Constraint file
module uart_top(CLK, BTN_SOUTH, BTN_WEST,
# ==== Clock inputs (CLK) ====
RS232_DCE_RXD, dout_rdy, dout_byte,
NET "CLK" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
d_rdy, d_byte, RS232_DCE_TXD, clk_x);
NET "CLK" PERIOD = 20.0ns HIGH 40%;
parameter SIZE = 11;
# ==== Pushbuttons (BTN) ====
parameter MAX = 1302;
NET "BTN_SOUTH" LOC = "K17" | IOSTANDARD = LVTTL
input CLK, dout_rdy;
| PULLDOWN ;
input BTN_SOUTH; // Active Low Reset
NET "BTN_WEST" LOC = "D18" | IOSTANDARD = LVTTL |
input BTN_WEST; // Din Ready
PULLDOWN ;
input RS232_DCE_RXD; // Receiver Pin
# ==== 6-pin header J1 ====
input [7:0] dout_byte;
# These are shared connections with the FX2 connector
output d_rdy; // 1-bit ready input signal that indicates NET "dout_byte<0>" LOC = "B4" | IOSTANDARD = LVTTL
the data is ready at
| SLEW = SLOW | DRIVE = 6 ;
input for Tx
NET "dout_byte<1>" LOC = "A4" | IOSTANDARD = LVTTL
output clk_x;
| SLEW = SLOW | DRIVE = 6 ;
output RS232_DCE_TXD; // Monitoring Signal: 1-bit Tx NET "dout_byte<2>" LOC = "D5" | IOSTANDARD = LVTTL
data output from UART
| SLEW = SLOW | DRIVE = 6 ;
output [7:0] d_byte;
NET "dout_byte<3>" LOC = "C5" | IOSTANDARD = LVTTL
reg clk_16x, d_rdy, drdy;
| SLEW = SLOW | DRIVE = 6 ;
reg [3:0] count_div;
# ==== 6-pin header J2 ====
reg [7:0] d_byte;
# These are shared connections with the FX2 connector
reg [7:0] databyte; //8-bit data input in UART for Tx NET "dout_byte<4>" LOC = "A6" | IOSTANDARD = LVTTL
reg [SIZE-1:0] count_div_19200;
| SLEW = SLOW | DRIVE = 6 ;
wire dout_rdy_wire, clk_x;
NET "dout_byte<5>" LOC = "B6" | IOSTANDARD = LVTTL
wire [7:0] dout_byte_wire;
| SLEW = SLOW | DRIVE = 6 ;
// ---------------- CLOCK DIVIDER BLOCK for Baud Rate -- NET "dout_byte<6>" LOC = "E7" | IOSTANDARD = LVTTL
-------------| SLEW = SLOW | DRIVE = 6 ;
always @(posedge CLK or posedge BTN_SOUTH)
NET "dout_byte<7>" LOC = "F7" | IOSTANDARD = LVTTL
begin
| SLEW = SLOW | DRIVE = 6 ;
if(BTN_SOUTH)
# ==== RS-232 Serial Ports (RS232) ====
begin
NET "RS232_DCE_TXD" LOC = "M14" | IOSTANDARD =
count_div_19200 <= 0;
LVTTL | DRIVE = 8 | SLEW = SLOW ;
clk_16x <= 1'b0;
end
else if(count_div_19200 == MAX-1)
begin
count_div_19200 <= 0;
clk_16x <= ~clk_16x;
end
else
begin
count_div_19200 <= count_div_19200 + 1;
clk_16x <= clk_16x;
end
end
// clk_16x = 19200 Hz
7
always @(posedge clk_16x or posedge BTN_SOUTH)
begin
if(BTN_SOUTH)
count_div <= 4'd0;
else
count_div <= count_div + 1;
end
// clk_x = 1200 Hz
assign clk_x = count_div[3];
always @(posedge CLK or posedge BTN_SOUTH)
begin
if(BTN_SOUTH)
begin
d_rdy <= 1'b0;
d_byte <= 8'd0;
end
else if(BTN_WEST)
begin
d_rdy <= dout_rdy;
d_byte <= dout_byte;
end
else
begin
d_rdy <= dout_rdy_wire;
d_byte <= dout_byte_wire;
end
end
always @(posedge CLK or posedge BTN_SOUTH)
begin
if(BTN_SOUTH)
begin
drdy <= 1'b0;
databyte <= 8'd0;
end
else
begin
drdy <= d_rdy;
databyte <= d_byte;
end
end
// Transmitter
uat_top uat_top_inst( .clk_x(clk_x),
.rst_p(BTN_SOUTH), .din_rdy(drdy),
.din_byte(databyte),
.ser_out(RS232_DCE_TXD) );
endmodule
8
12. Discussion :
Implementing the transmission core of UART on Xilinx involves a number of important considerations, and a solid
understanding of the key components is essential. To start with, it is crucial to have a clear grasp of what UART is
and how it operates, as it is a widely used serial communication protocol in computer systems. The clock signal is
another crucial element in the implementation, as it is required to synchronize the transmission and reception of
data between the sender and the receiver. Xilinx FPGA devices typically have a built-in clock management system
that can generate clock signals with different frequencies and phases, which must be carefully set up to match the
baud rate of the UART communication. Additionally, the baud rate is specified in bits per second and is a critical
factor in determining the rate at which bits are transmitted over the communication line. Data format and control
signals are also important considerations in designing a functional UART transmission core on Xilinx, and careful
attention must be paid to these aspects during the design, simulation, and synthesis processes
13. Conclusion :
To summarize, designing a UART transmission core on Xilinx involves understanding the basic principles of UART
communication, such as the use of a clock signal and baud rate to synchronize data transmission. Implementing a
UART transmission core on Xilinx requires the selection of appropriate hardware design tools and IP cores, as well
as careful consideration of the data format and control signals needed for reliable serial communication. By taking
these factors into account, a customized UART transmission core can be created that meets the specific
requirements of the external device and enables efficient and reliable data transmission between the sender and
receiver.
14. Reference :
The reference are given below

https://www.pantechsolutions.net/uart-interface-with-xilinx-spartan-fpga

https://support.xilinx.com/s/question/0D52E00006hpZx1SAE/uart-programming?language=en_US

9