Comparison of Diodes and Resistors for Measuring
Chip Temperature During Thermal Characterization
of Electronic Packages Using Thermal Test Chips
Alan Claassen
IBM Corporation
Storage Systems Division
5600 Cottle Road
San Jose, CA 95193
U.S.A.
aclaassenavnet.ibm.com
H. Shaukatullah
IBM Corporation
Microelectronics Division
1701 North Street
Endicott, NY 13760
U.S.A.
Abstract
Thermal test chips are specially designed and built
for thermal characterization of electronic packages.
These chips have heaters for powering the chip and
temperature sensors for measuring the chip temperature. One type of temperature sensor in wide use is
a diode. Small resistors (also known as resistance
temperature detectors or RTDs) are also used for
measuring the chip temperature. This paper reviews
and compares the characteristics of the diodes and
RTDs used for chip temperature measurement
during the thermal characterization of electronic
packages. Techniques for reducing the measurement
errors associated with these chip temperature
sensors are also discussed. It is shown that the temperature versus voltage characteristics of RTDs at
constant current are much more linear than those of
diodes.
I
current, A
k
Boltmaim's constant
K
K factor method constant defined in equation
(9,OClV
constant in equation (1)
power dissipation in the chip, W
electron charge
constant in equation (1)
resistance, ohm
resistance at temperature T I ,ohm
thermal resistance, OC/W
chip sensor temperature, "C
absolute temperature, K
TASS
Nomenclature
ambient temperature
condition, "C
at
steady
state
A
coefficient defined in equations (2), (3)
TAO ambient temperature at initial equilibrium
condition at time zero, "C
B
coefficient defined in equations (2), ( 3 )
T,, chip sensor temperature at steady state
C
coefficient defined in equation ( 3 )
0-7803-3793-X/97/$5.0001997 IEEE
condition after application of power, "C
198
Thirteenth IEEE SEMI-THERMTM
Symposium
chip sensor temperature at initial equilibrium
condition, "C
Techniques for reducing measurement errors associated with these chip sensors are also discussed.
reference temperature, "C
voltage, V
Thermal Test Chip Description
extrapolated energy gap at absolute zero
temperature
Two test chips, one with diodes and the other with
resistors for temperature sensing were used in this
study. A schematic of the test chip with diodes as
temperature sensors is shown in Fig. 1. This chip
had 5 heaters (one around the periphery and one in
each quadrant) for powering the chip and 19 diodes
for sensing the chip temperature. The nominal size
of the chip was 7x7.3 mm with 403 small solder
balls (commonly known as controlled collapse chip
connections or C4s) arranged in a circular pattern in
the center of the chip (23x23 array, depopulated in
the corners). A cross section of the flip chip package
using this test chip is shown in Fig. 2. The package
consisted of an alumina substrate with copper alloy
pins staked into holes. The nominal size of the
package was 36 rnm square and the pins were
arranged in a 2.54x2.54mm grid. The test package
had 179 pins in a 14x14 array with 17 depopulated
near the center for the chip. The top surface of the
substrate was metallized with chromium-copperchromium metallurgy to provide interconnection
circuitry between the chip and the pins. The chip
was joined to the substrate using the flip chip C4
solder reflow technique. To protect the chip and the
circuitry on the substrate from damage during handling, an aluminum cap was used on these packages. The cap was mechanically secured to the
substrate and sealed with epoxy. For thermal characterization, this package was plugged into a socket.
temperature coefficient of resistance, "C
J
change in temperature between two
calibration temperatures or between initial
and steady state conditions, "C
change in voltage between two calibration
temperatures or between initial and steady
state conditions, V
Introduction
Temperature is a primary factor affecting the reliability of integrated circuit chips and packages.
Circuit density and power dissipation of integrated
circuit chips are increasing and proper thermal characterization of electronic packages is becoming very
important. The JEDEC JC 15.1 committee is developing standards for thermal characterization of electronic packages. One of the proposed standards [11
is on the design of thermal test chips. See also [2].
Thermal test chips are specially designed for thermal
characterization of electronic packages. They have
heaters, in the form of resistors or diodes, for powering the chip and temperature sensors in the form
of diodes or resistors for measuring the chip temperature. There are a number of references that
describe the thermal test chips with diodes [3, 4, 5,
6, 7, 81, and diodes appear to more commonly used.
Resistors (commonly known as resistance temperature detector or RTD) are also used for measuring
the chip temperature and test chips using these are
described in [6, 9, 10 ,111.
A schematic of the thermal test chip with RTDs is
shown in Fig. 3. This was a wire bond type chip
with 331 pads along the periphery of the chip
arranged in a double row. The nominal size of this
chip was 11.5x11.5 mm. It had 4 heaters (one in
each quadrant) for powering the chip and 4 small
resistors for temperature sensing. The temperature
sensors were made into a small spiral as shown in
Fig. 4 and had a nominal resistance of about 10
ohms at 22 "C. The size of the spkd was nomindy
0.05 mm. In addition, this chip had a number of
other structures for assessing the reliability of the
package. These included pairs of inner and outer
perimeter lines around the wire bond pads for determining chip cracking, a comb structure for corrosion and electromigration studies, and several sets of
For thermal characterization of electronic packages
with thermal test chips, the temperature sensors
(diodes or resistors) in the test chip are calibrated
prior to use. During tests, the calibration data is
used to determine the chip temperature. This paper
reviews and compares the characteristics of the
diodes and resistors used in thermal test chips for
thermal characterization of electronic packages.
199
Thirteenth IEEE SEMI-THERMm" Symposium
rDlODE
HEATERS71
B
7-4
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
O O O O C J b O O O O O ~ O O O O O ~ O O O IO
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7.3
Fig. I .
Schematic of the flip chip showing the heaters and diodes. Nomind dimensions in II~II~.
L
sUBsT RATE
EPOXY SEAL
Fig. 2.
Cross section of the metallized ceramic package with flip chip.
200
Thirteenth IEEE SEMI-THERM” Symposium
f
\. I I
Fig. 3.
OUTER PERIMETER L I N E S
,-INNER PERIMETER
I
/
sE'qs0R/7
Schematic of the wire bond chip showing heaters, resistance temperature sensors (RTDs) a d
other reliability test structures. Dimensions in mm.
201
Thirteenth IEEE SEMI-THERMTMSymposium
Fig. 4.
Details of the temperature sensing resistor spiral (RTD) in the wire bond test chip.
OPPER LEADFRAME
ALUMINUM BASE
ONDUCTIVE A D H E S I V E
ALUMINUM
Fig. 5.
LID
Cross section of the metal quad flat pack with wire bond chip.
N
-Q I
I
I
I
I
I
I
I
I
131.2 '
C
95.9 OC
.I
..-*.-- 60.9 C'
-.-m-'-
22.6 C
'
U
c
0.4
0.6
Fig. 6.
1 .o
0.8
FORWARD VOLTAGE,
1.2
V
Current versus voltage characteristics of the diode used in this study oyer a range of temperatures.
202
Thirteenth IEEE SEMI-THERMTMSymposium
pads connected together for assessing the integrity of
wire bond pads. This chip was packaged in a
surface mount metal quad flat pack. The cross-section is shown in Fig. 5. This was a 28 rnm
208-leaded cavity-down type of package and for
thermal characterization, was soldered to a test card.
voltage is measured and temperature is determined
from these equations.
The current versus voltage characteristics of the
diode in the test chip are shown in Fig. 6 for
various temperatures. The simplified form of
Shockley's relation is valid only in the linear portions of the curves, in this case, approximately
between 0.01 and 1 mA. For the tests reported in
this study, the diode was operated at a constant
current of 0.1 mA.
Characteristics of Diodes and Resistors
The temperature characteristics of a diode used for
measuring the chip temperature is the forward
voltage drop at constant current. The voltage, VI
and current, I, are related to absolute temperature,
using a simplified form of Shockley's relation
[121 expressed as
The relation between resistance and temperature of
a resistor is usually expressed in the form [131
(4)
where R1 is the resistance at reference temperature
Tl, R is the resistance at temperature T , and a is the
temperature coefficient of resistance. This linear
relationship is usually valid over limited temperature
ranges. Over extended temperature ranges a more
elaborate relation known as the Callendar-Van
Dusen relation is used [13]. For practical use in
thermal characterization, the above relation can be
simplified to the form of equation (2) by the use of
Ohm's Law relating voltage, current and resistance
(V= I R ) at constant current. For extended ranges,
polynomials of the form in equation (3) can be
used. The resistance temperature sensor in these
tests was operated at a constant current of 10 mA.
where, Gois the extrapolated energy gap at absolute
zero temperature, k is Boltzmann's constant, Kl is a
constant that depends on geometrical factors such
as base width of the junction, r is a constant that
depends on the temperature dependence of mobility
of minority carriers in the base region, and q is the
electron charge.
This relation shows that at constant current, the
forward voltage drop of a diode is almost a linear
function of temperature. For practical use this
relation can be expressed as
T=A+BV
The calibration of thermal test chips is usually done
at only two to four temperatures as described in the
JEDEC JC 15.1 electrical test method standard
[141. For two points, the standard requires a temperature difference of at least 50 "C, then gives
room ambient temperature and 100 "C as sample
temperatures. It also explains that smaller temperature increments can help detect a bad data point
and account for a small non-linearity in the calibration curve. Sample data points mentioned are
room temperature, 50 " C ,75 "C, and 100 "C.
(2)
and forms the basis of the constant-current method
for sensing temperature. The constants A and B are
determined by calibration at constant current over
the temperature range expected during subsequent
tests. For thermal characterization, the temperature
is usually not expressed in absolute units. This
linear relation is generally valid over small temperature ranges. Over extended ranges, higher order
polynomials of the form
T = A + B V + C V ~ +...
When two points are used, the calibration curve is
limited to the linear fit given in equation (2). T h e
JEDEC standard describes an alternate method of
using a two point linear fit referred to as the K
factor method. During calibration, the diode or
resistor is monitored at two temperatures, for
example room temperature and 100 "C,and the K
(3)
are used. In equations (2) and (3), the temperature
is kept as a dependent variable and voltage as the
independent variable for convenience. During tests,
203
Thirteenth IEEE SEMI-THERMTMSymposium
factor is calculated as the change in temperature,
AT, divided by the change in voltage, AV, between
those conditions.
K=
AT
AV
__
The K factor is equivalent to the slope B in
equation (3,but the intercept constant A is not
used. Instead, application of the K factor calibration method for thermal resistance measurements
relies on an initial equilibrium condition where the
diode or resistor temperature, To, is equal to the
ambient temperature 7'40. Then after powering the
chip, the steady state chip temperature, T,,, is a
function of the change in diode or resistor voltage
between the initial equilibrium condition and the
final steady state condition. This is given by
A thermal resistance, &, can be calculated from (see
c 151)
(7)
where TA$,is the ambient temperature at steady
state conditions, and PH is the power dissipation in
the chip. By substituting equation (6) in (7), the
expression for thermal resistance becomes
to the top center of the package with silver-filled
epoxy. A dab of quick drying epoxy was used to
cover the silver epoxy and any bare wires near the
bead. This thermocouple was used for calibrating
the temperature sensors in the chip. All tests were
conducted in an oven because it is easy to set and
control the temperature. During the tests, the thermocouple on the package and the temperature
sensor in the chip (diode or resistor) were monitored to check for steady state before recording any
data. Steady state was assumed when the chip temperature sensor output showed a change of about
0.1 "C or less in four minutes (in terms of voltage,
the criteria was 0.0001 V or less for diodes and
0.00003 V or less for RTDs) and the thermocouple
output showed a change of 0.1 "C or less in two
minutes.
All tests were done using a computer controlled
data acquisition system. The typical test procedure
was as follows: the package was placed in the oven
and allowed to equilibrate to room temperature.
The temperature sensor in the chip and the thermocouple on the package were monitored to check for
steady state. At steady state, the voltage output of
the temperature sensor (at fixed current) and the
temperature indicated by the package thermocouple
were recorded. Next, the oven was turned on and
set to a higher temperature. The chip temperature
sensor and package thermocouple were monitored
for steady state. At steady state, the sensor voltage
and thermocouple output were recorded. This procedure was repeated for several other temperatures.
Data was recorded at room temperature (about 22
as is done in the JEDEC natural convection (still
air) environment standard [IS]. When applied in
this way, the K factor method does not require the
initial ambient temperature, TAO,and the steady
state ambient temperature, TArr,to be equal. What
is required is that, prior to applying heating power,
the chip temperature is equal to a measured initial
"C), about SS "C, and from there onwards at about
5 " C steps to about 135 "C. The oven used in these
tests could not be set to temperatures less than
about 55 "C.In order to do so would have required
the use of a coolant (liquid carbon-dioxide) and this
was not done. One sample of each type of package
was used. For each package, the temperature
sensor in the center of the chip was used.
temperature, in this case the initial ambient temper-
ature. Any error in meeting this requirement will
add to the calibration error.
Test Procedure
A 36 gauge (0.13 mm diameter wire) copper-constantan (ANSI Type T) thermocouple was attached
Results and Discussion
Calibration data for the diode over a temperature
range from about 22 "C to 135 "C is shown in Fig.
7. Also shown is the least squares linear fit to the
data. The deviations between the fitted line and the
data points are shown in Fig. 8. The deviations are
204
Thirteenth IEEE SEMI-THERM" Symposium
T = 483.410 - 596.843
X
V
h
B
K v -
3
*
$ -
I
0.5
I
I
0.6
I
I
0.7
6
I
I
0.8
*
0.9
VOLTAGE. V
TEMPERATURE. '
C
fig. 10. Deviations between data and linear fit
using four points (22, 60, 100 and 135 "C)
for the diode.
Fig. 7. Calibration data for the diode (at 0.1 mA
current) fitted to a linear curve using all
data points.
DONr
s'
- 603.481
T = 488.311
r\
2-
-
$I -
*
I
F
I
40
GI
, ,,*:
**
**
**
x V
*
1
I
****-*
120
160
v
6
TEMPERATURE. '
C
Fig. 8.
Deviations between data and linear fit
using all data for the diode.
T = 483.151
if
P
Eo I
TEMPERATURE. '
C
- 597.140
Fig. 11. Deviations between data and linear fit
using four points (22,55, 75 and 100 "C) '
for the diode.
x V
T = 487.992
r"[
- 603.418
3
I
L
v
g7 -
z-
I
.n
40
9
80
************
,
12$*
**
0.
,.
I
II
160
I
40
I
Bo***-
..**
**
**
X
V
*
,
1
120
160
******
O N _
TEMPERATURE.
Fig. 9.
Deviations between data and linear fit
using two points (22 and 135 "C) for the
diode.
"e
Fig, 12. Deviations between data and hear fit
using two points (22 and 100 "C)for the
diode.
205
Thirteenth IEEE SEMI-THERMTMSymposium
not random and there is a trend in the data points
implying that the linear fit is not a good approximation to the data. The maximum deviation (fitted
value - measured value) is of the order of 1 "C and
for some practical cases, may be considered acceptable. The deviation plot also shows a slight skew
towards the lower temperature. The reason for this
is the missing data points between 22 and 55 "C.
Normally for package thermal characterization using
test chips, the calibration is done at only a few
points covering the expected test temperature range.
Assuming an expected range from room temperature to 135 "C, Fig. 9 shows the deviations for a
linear fit using the two calibration end points
(nominal 22 and 135 "C). Here again, the maximum
deviations are of the order of 1 "C. The deviations
between the data and a linear fit using four equally
spaced points (nominally 22, 60, 100 and 135 "C)
are shown in Fig. 10. Here the maximum deviations are of the order of 0.6 "C. Thus, by using
four equally spaced points, the maximum deviations
are reduced. In this case, using four equally spaced
points is better than using all the data because the
data has fewer points at the low range. As noted
above, the fewer points at low temperature are
biasing the fit towards the higher temperature and
resulting in a larger error at the low end. This effect
is not present in the results discussed below.
For the temperature range from room temperature
to 100 "C, as used in the JEDEC standard [14], the
deviations between the fit and the data points using
four approximately equally spaced points (nominally 22, 55, 75, and 100 "C) are shown in Fig. 11.
Here the maximum deviation between the fit and
the data point is of the order of 0.4 "C within the
range of the fit (22 to 100 "C). But beyond this
range, the deviations increase with temperature to
1.5 "C at 135 "C. The deviations between the fit
and the data points using two points (nominally 22
and 100 "C) as in the K factor method are shown in
Fig. 12. The maximum deviation within the range
of fit is of the order of 0.6 "C. Beyond this range it
increases to 1.2 "C at 135 "C. Thus, in the case of
a diode, increasing the number of equally spaced
points from two to four in the range of interest
decreases the error in that range. However, extrapolating a diode linear fit beyond the calibration range
can result in large errors in chip temperature measurements. It is better to do the calibration over the
range of temperature expected during the tests using
four (preferably more) equally spaced points if a
linear fit is going to be used.
The errors can be reduced by using a higher order
fit to the diode data. Figure 13 shows the deviations between the fit and the data points for the
diode using a 2nd order polynomial. With the 2nd
order fit the maximum deviations are around 0.1 "C
and have been reduced by almost an order of magnitude compared to the linear fit (Fig. 8). Similar
deviations are obtained if a 2nd order fit is used
with four approximately equally spaced points over
the temperature range (22, 60, 100, 135 "C). Therefore, the 2nd order fit is not sensitive to the missing
points near room temperature. Figure 14 shows the
results for a 2nd order fit of four equally spaced
points over the temperature range (22, 55, 75, 100
"C). Though the maximum deviation within the
range of fit is again 0.1 "C, beyond this range it
increases to nearly 0.5 "C at 135 "C. This is less
than the 1.5 "C deviation obtained with the linear
fit (Fig. ll), but still shows the advantage of calibrating over the range of interest to avoid having to
extrapolate the calibration curve.
The calibration data for the RTD is shown in Fig.
15 with a linear fit to all the data points. The deviations between the fitted line and the data points are
shown in Fig. 16. The maximum deviation is of the
order of 0.1 "C. Thus the RTD is much more linear
than a diode (deviations are an order of magnitude
less). Deviations for a linear fit using two points
(22 and 135 "C) and four points (22, 60, 100, 135
"C) are shown in Figs. 17 and 18 respectively.
Because the RTD is almost linear, the improvement
between the two and four points fits is small, but
four or more equally spaced points are better. The
deviations for a linear fit with two points used for
the K factor method (22 and 100 "C) are shown in
Fig. 19. Here also, the deviations within the range
of the fit (22 to 100 "C) are much smaller (0.07 "C
or less), and beyond the calibration range increase
to around 0.13 "C. Again, extrapolating data
beyond the calibration range should be avoided, but
in the case of RTDs the errors are an order of magnitude less compared to diodes.
Figure 20 shows the deviations between the data
and a 2nd order polynomial using all data points for
the RTD. Compared to the linear fit, the 2nd order
fit is better, but the improvement here is not as
much as in the case of the diode. Also, for most
206
Thirteenth IEEE SEMI-THERM" Symposium
*+
'C
TEMPERATURE.
Fig. 13. Deviations between data and 2nd order fit
uskg all data for the diode.
"'i
T = 417.623
- 402.637
X
V
"C
TEMPERATURE.
-
Fig. 16. Deviations between data and linear fit
using all data for the RTD.
u%l
142.015 x V2
T
+
-254.485
*
2200.005 x V
*** *** * ****
2-
+!
$
***
I
PO,
E 1
'**
'TEMPERATURE.
L,.
I
I
40
BO
I
I
120
I
I '
.p
160
I
"C
TEMPERATURE.
fig. 14. Deviations between data and 2nd order fit
using four points (22, 55, 75 and 100 "C)
for the diode.
"C
Fig, 17 Deviations between data a d hear fit
using two points (22 and 135 "C)for the
RTD.
pz[
T = -254.547
+
2200.080 x V
*
:****** ****
TEMPERATURE.
Fig. 15. Catibration data for the RTD (at 10 mA
current) fitted to a linear curve using all
data points.
'
C
Fig, 18, Deviations between data and linear fit
using four points (22, 60, 100 and 135 '12)
for the RTD.
207
Thirteenth IEEE SEMI-THERMTMSymposium
practical purposes, errors of the order of 0.1 " C are
acceptable. So using a 2nd order fit for RTD is not
needed in most cases.
&
I
+
T = -254.169
2197.489 x V
F "'i
40
80
?-
'
L
2 0
160
*A20
***
v
m-
I
I
LL
-
*
I-
2 I
TEMPERATURE.
RTD.
r
T = -250.756
+ 2149.444
x V
+
166.109 x
Vz
*
TEMPERATURE.
For thermal characterization of packages, both the
calibration curve and K factor methods can be used
for RTDs and diodes. If a 2nd order polynomial fit
is required for the diodes and RTDs, then the calibration method must be used. Also, use of the calibration method does not require data for the initial
equilibrium condition where the chip temperature
stabilizes to the environment temperature. Therefore, the calibration curve method can result in a
shorter test time.
"C
Fig. 19. Deviations between data and h e a r fit
using two points (22 and 100 "C) for the
.o 2
Although the diode is almost 4 time more sensitive
than the RTD, this is not much of a concem
because high resolution digital volt meters are commonly used for data acquisition these days, and they
are capable of resolving 1 pV or less in one volt.
"C
Fig. 20. Deviations between data and 2nd order fit
using all data for the RTD.
The above comparison has shown that at constant
current, the temperature versus voltage characteristics of RTDs are much more linear than those of
diodes. Another advantage of the RTD is that it can
be designed to measure either a local spot temperature or the average chip temperature. For a spot
temperature, the RTD can be designed as a spiral as
shown in Fig. 4 or as a zig-zag patch. For the
average chip temperature, the RTD can be designed
so that it is distributed over the chip as shown in
[ 6 ] . The diode has the advantage of higher sensitivity. For the samples used in this study, the diode
had a sensitivity of about 1.7 mV/"C whereas the
RTD had a sensitivity of about 0.45 mV/"C.
Conclusions
This study shows that the temperature versus
voltage characteristics of RTDs at constant current
are much more linear than those of diodes, For
thermal characterization of electronic packages using
test chips and a two point calibration, or a linear fit
of more data points, the errors involved with RTDs
are an order of magnitude smaller compared to
diodes. The diode errors can be reduced by using a
2nd order fit to the calibration data. The calibration points must be equally spaced to " k e
fitting errors. Compared to the diodes, the sensitivity of the RTDs is less, but this is not a major
disadvantage these days because high resolution
digital volt meters are commonly available. The
RTDs have the advantage that they can be designed
to measure either a local temperature or the average
temperature of the chip.
The K factor method can result in unacceptable
errors for diodes if only two points are used. Four
or more equally spaced points are recommended.
Two points provide a good fit for RTDs, but four
points are still recommended so that a bad data
point can be detected.
Acknowledgements
This study was made possible due to the efforts of a
number of IBM employees. In particular we would
like to acknowledge the work of Ralph Kilmoyer in
208
Thirteenth IEEE SEMI-THERM" Symposium
the design of the wire bond chip and Charlie Tai in
the design of the flip chip. The drawing of the wire
bond chip was made by Pat Johnson.
Intemational Conference on Multichip
Modules, SPIE Vol. 2794, pp. 323-328,
Denver, Colorado, April 17-19, 1996.
References
P.E. Roughan, 'Thermal Resistance of IC
Packages," Electronic Packaging and Production, Vol. 14, No. 6 , pp. 116-120, June
1974.
c 11
c21
JEDEC JC 15.1 Committee Proposal,
"Thermal Test Chip Guideline (Wire Bond
Type Chip)," (1996).
H. Shaukatullah, S.J. Diffenderfer, and E.G.
Flynn, "Comparative Thermal Evaluations of
Small Surface Mount Flat Packs," Proceedings of the 1995 Intemational Electronics
Packaging Conference (IEPS), pp. 102-114,
San Diego, California, September 24-27,
SEMI G32-86, "Guideline for Unencapsulated Thermal Test Chip," Book of SEMI
Standards, Vol. 4 (Packaging Division), Semiconductor Equipment and Materials International (SEMI), Mountain View, California,
1990.
1995.
H. Shaukatullah, F.E. Andros, M.A. Gaynes,
and C.P. Loveland, "Thermal Characteriza-
c31
M.H. McLaughlin, and N.D. Fitzroy,
"Thermal Chip Evaluation of IC Packages,"
IEEE Transactions on Parts, Hybrids, and
Packaging, Vol. PHP-8, No. 3, pp. 39-44,
September 1972.
tion of Tape Ball Grid h a y Packages," Proceedings of the 1996 Intemational Electronics
Packaging Conference (IEPS), pp. 377-395,
Austin, Texas, September 29-October 1,
1996.
c41
F.F. Oettinger, 'Thermal Evaluation of VLSI
Packages Using Test Chips - A Critical
H. Shaukatullah, "A Method of Using
Thermal Test Chips With Diodes for
Thermal Characterization of Electronic Packages Without Calibration," Eleventh Annual
IEEE Semiconductor Thermal Measurement
and Management Symposium, pp. 83-86, San
Jose, California, February 7-9, 1995.
Review," Solid State Technology, Vol. 27,
NO. 2, pp. 169-179, February 1984.
c51
J.N. Sweet, "Integrated Test Chips improve
IC Assembly," IEEE Circuits and Devices,
Vol. 6, No. 5, pp. 39-45, September 1990.
C61
V.W. Antonetti, S. Oktay, and R.E. Simons,
"Heat Transfer in Electronic Packages," in
Microelectronics Packaging Handbook, edited
by R.R Tummala and E.J. Rymaszewski,
Chapter 4, pp. 176-223, Van Nostrand Reinhold, New York, 1989.
c71
CSl
R.P. Benedict, Fundamentals of Temperature, Pressure, and Flow Measurements, 3rd
edition, John Wiley &. Sons, New York,
1984.
EIA/JEDEC Standard EIA/JESDSl-l, "Integrated Circuit Thermal Measurement Method
- Electrical Test Method (Single Semiconductor Device)", Electronic Industries Association, Arlington, Virginia, December 1995.
S.C.O. Mathuna , and L. Daguang, "Development and Application of Test Chips and
Test Systems for the Thermal Characterization of IC Packaging Technologies," Eight
Annual IEEE Semiconductor Thermal Measurement and Management Symposium, pp.
47-54, Austin, Texas, February 3-5, 1992.
EIA/JEDEC Standard EIA/JESD51-2, "Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection
(Still Air)",Electronic Industries Association,
Arlington, Virginia, December 1995.
D.J. Bennett, B.T. DeMuth, and B.E. Pines,
"Refming MCM Thermal Simulation Models
with Test Vehicles," Proceedings of 1996
209
Thirteenth IEEE SEMI-THERM" Symposium