Chapter 10 :
Flip-flops and Register
OUTLINE
S-R Flip-flop
Gated S-R Flip-flop
Gated D Flip-flop
D Latch: 7475IC; VHDL Description
D Flip-flop: 7474IC; VHDL Description
Master-Slave J-K Flip-flop
Edge- Trigerred J-K Flip-flop with VHDL Model
Integrated- Circuit J-K Flip-flop (7476, 74LS76)
Using an Octal D Flip-flop in a Microcontroller Application
S-R Flip-Flop
A flip-flop circuit can stay in a binary state continually (as long as power is transferred to the circuit)
before conducted by an input signal to switch states. S-R flip-flop represents SET-RESET flip-flops.
The SET-RESET flip-flop includes two NOR gates and also two NAND gates.
The S and R inputs control the state of the flip-flop when the clock pulse goes from LOW to HIGH.
The flip-flop will not change until the clock pulse is on a rising edge. When both S and R are
simultaneously HIGH, it is uncertain whether the outputs will be HIGH or LOW.
The SR flip-flop has two inputs such as the ‘Set’ input and a ‘Reset’ input. The two outputs of SR flipflop are the main output Q and its complement.
S-R Flip-Flop (Cross NOR S-R Flip-flop)
Gated S-R Flip-Flop (Cross NAND S-R Flip-flop)
1
0
1
0
A
B
x
Y
S-R Flip-flop Application
Gated S-R Flip-flop
The gated SR flip-flop is the basic flipflop that generates the feedback from both the
outputs back to its opposing input.
Gated S-R Flip-Flop is an edge-triggered type of memory circuit.
Asynchronous
output responds
immediately to input
Synchronous
output responds in
stepwith a control
input.
Gated S-R Flip-flop
Gated D Flip-Flop
Gated D Flip-Flop
A gated D flip-flop is a type of digital circuit or another type of flip-flop
that stores a single bit of information and can be controlled by a gating
signal.
Gated D Flip-Flop
The operation is such that Q will be the same as D while G is HIGH, and Q will
remain latched when G goes LOW. (Latched means that Q remains constant
regardless of changes in D.)
D Latch: 7475IC; VHDL Description
is a simple digital circuit that stores a single bit of information. It is commonly used in
digital systems for temporary storage of data and synchronization purposes.
Also known as the data latch or delay latch.
D latch integrated circuit the 7475IC has four separate D latches. Each latch has two
inputs (D for data and C for clock), one output (Q), and two inputs. The IC also features an
active-low enable input (G) that, when set to logic low, makes it possible to deactivate the
outputs.
Using the programming language VHDL (VHSIC Hardware Description Language), digital
circuits and systems are described. Before implementation, it enables designers to model
and synthesize their ideas, lowering mistakes and increasing efficiency.
D Latch: 7475IC; VHDL Description
D Latch: 7475IC; VHDL Description
ADVANTAGE
The main advantages of D latches are their simplicity and ease of use.
They are more suited for low-power and price-sensitive applications since they require
fewer components than other storage elements like flip-flops and registers.
DISADVANTAGE
D latches also have significant disadvantages. They are especially prone to errors and
metastability problems when utilized in crucial timing pathways.
They cannot be utilized for sequential logic designs and have restricted utility in
comparison to other storage components.
D Flip-Flop: 7474IC; VHDL Description
It is frequently used in digital electronics products including counters, shift registers, and
memory units.
A kind of digital circuit that holds a single piece of data.
The 7474IC is a well-known D flip-flop integrated circuit that comes in a single package
with two separate flip-flops. Due to its dependability and affordability, it is frequently
utilized in a variety of electrical tasks.
The SET and RESET stable states are used by the D flip-flop to store a single bit of data
throughout the operation. The input data is sampled and stored in the flip-flop according
to its current state when the clock signal is applied.
D Flip-Flop: 7474IC; VHDL Description
D Flip-Flop: 7474IC; VHDL Description
ADVANTAGE
It is a popular alternative among experts and enthusiasts alike for digital electronics
applications since it is affordable and dependable.
The total complexity of the circuit design is reduced by the 7474IC's simplicity of usage
and low requirement for external components.
Master-Slave J-K Flip-flop
The Master-Slave J-K Flip-Flop is a digital circuit that can store
and manipulate binary information.
I called toggle. Toggle means that Q and Q' will switch to their
opposite states (Q will switch from a 1 to 0 or from a 0 to a 1.)
It has two input (J and K) and output (Q and Q')
When both J and K are low, the output does not change. When
both J and K are high, the output toggles (switches between 0
and 1).
74H71, 7472, 7473, 7476, 7478, 74104, 74105 are master salve
variety
It consist of two latches: a master
S-R latch (S-R flip-flop) that receives data while the input
trigger clock is HIGH, and a slave S-R latch that receives
data from the master and outputs it when the clock goes
LOW
Edge- Triggered J-K Flip-Flop with VHDL Model
The Edge-Triggered J-K Flip-Flop with VHDL Model is a digital circuit
component that synchronizes its behavior with the clock signal and
can be used to implement a variety of logic functions.
Accepts data only on the J and K inputs that are present at the active
clock edge
(either the HIGH-to-LOW edge of Cp or the LOW-to-HIGH edge of Cp).
Have the ability to accept input data on J and K at
a precise instant in time.
The logic symbols for edge-triggered flip-flops use a small triangle at the clock input
to signify that it is an edge-triggered device
(see Figure 10–37).
Transitions of the Q output for the positive edge-triggered flip-flop shown in
Figure 10–37(a) will occur when the Cp input goes from LOW to HIGH (positive
edge). Figure 10–37(b) shows a negative edge-triggered flip-flop. The input clock
signal will connect to the IC pin labeled . The small circle indicates that transitions
in the output will occur at the HIGH-to-LOW edge (negative edge) of the Cp input.
Positive Edge triggered( Low to high)
Negative Edge triggered( High to low)
The function table for a negative edge-triggered J-K flip-flop is shown in
Figure 10–38.
The downward arrow in the column indicates that the flip-flop is triggered by
the HIGH-to-LOW transition (negative edge) of the clock.
Integrated- Circuit J-K Flip-flop (7476, 74LS76)
The 7476 and 74LS76 are popular
J-K flip-flops because they are both dual flip-flops (two flip-flops in each IC
package)
and they have asynchronous inputs
as well as synchronous inputs
The 7476 is a positive pulse-triggered (master–slave) flip-flop, and the
74LS76 is a negative edge-triggered flip-flop,
Using an Octal D Flip-Flop in a Microcontroller
Application
An octal D flip-flop can be used in a microcontroller application for various purposes, such as data storage,
synchronization, and control.
Here are a few use cases for an octal D flip-flop in a microcontroller application:
Data Storage: The octal D flip-flop can be used to store digital data. Each flip-flop within the octal package has a D
(data) input, a clock input, and a Q (output) signal.
Parallel Input/Output (I/O) Control: In microcontroller applications, parallel I/O is often required to interface with
external devices or subsystems. The octal D flip-flop can be used as a latch to hold the state of the data to be input or
output in parallel.
Synchronization: The octal D flip-flop can be used for synchronization purposes, particularly in situations where
timing and sequencing are critical.
Control Signal Generation: In some microcontroller applications, the generation of control signals is necessary to
drive various components or subsystems.
Overall, the octal D flip-flop provides a versatile and flexible component that can be utilized in a microcontroller
application for data storage, synchronization, parallel I/O control, and control signal generation, among other functions.
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