Digital Microelectronic
Circuits
(361-1-3021 )
Presented by: Dr. Alex Fish
Lecture 5:
Parasitic Capacitance
and
Driving a Load
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
1
Motivation



Thus far, we have learned how to model our essential
building block, the MOSFET transistor, and how to use
these building blocks to create the most popular logic
family, Static CMOS.
We analyzed the characteristics of a static CMOS inverter,
including its Static and Dynamic Properties.
We saw that both the delay and the power consumption of
a CMOS gate depend on the load capacitance of the gate.
t pd  0.69ReqCLoad
Digital Microelectronic Circuits
2
Pdynamic  f  C VDD
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
2
What will we learn today?

Today, we will go back to our MOSFET transistor to try and
understand what parasitic capacitances are inherent to its
structure.

Then, we will develop a model for equivalent capacitance
estimation for delay calculation of a CMOS inverter.

Accordingly, we will examine the optimal sizing of a CMOS
gate.

And finally, we will develop a methodology for sizing a
chain of inverters to drive a large load.
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
3
What will we learn today?
5.1 MOSFET Capacitance
5.2 Inverter Delay
Capacitance Model
5.3 Driving a Load
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
4
5.2
5.1 MOSFET Capacitance
5.2 Inverter Delay
Capacitance Model
5.3 Driving a Load
So back to our device, let’s see what
parasitic capacitances we have:
MOSFET
CAPACITANCE
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
5
MOSFET Capacitance


One of the important parameters of a MOS Transistor is its
capacitance.
The MOSFET has two major categories of capacitance:
» Gate/Channel Capacitance – capacitance caused by the insulating
oxide layer under the gate.
» Junction Capacitance – pn-Junction capacitance between the
diffusions and the substrate.
t
ox
CGS
n
+
L
CGC
CSB
CGD
n
+
CDB
p-substrate
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
6
Gate Capacitance

The Gate Capacitance includes:
» Gate to Channel Capacitance, CGC:
The main capacitance that is
dependent on the region of operation.
 ox
In general:
CGC  WL
tox
 CoxWL
» Gate Overlap Capacitance, CGDO, CGSO:
A constant (small) capacitance caused
by gate overlap of the diffusions.
CGSO  CGDO  WCOverlap
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
7
Gate Capacitance

Looking at gate capacitance as a function of biasing shows
how it changes.
» In accumulation, the capacitance is across the oxide.
» As VGS grows, the depletion layer decreases the capacitance
(as if the dielectric gets longer)
» Once the channel is formed, the capacitance jumps.
» At pinch-off, the drain capacitance drops to zero.
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
8
Gate Capacitance
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
9
Gate Capacitance

To model this non-linear behavior, we will use the
following approximations:
All capacitance is
towards substrate
CGB  CoxWL
Capacitance
symmetrically divided
between source and drain
All capacitance to
Source
CoxWL

2
2
CGCS  CGCD
CGCS  CoxWL
3
Question: How do we relate to Velocity Saturation?
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
10
Junction (Diffusion) Capacitance


The Junction Capacitance is the diffusion capacitance of the
MOSFET.
This is measured according to fabrication parameters
Cdiff  Cbottom  Cside walls 
 C j  Area  C jsw  Perimiter 
 C j  Ldiff W  C jsw  2 Ldiff  W 


Digital Microelectronic Circuits
Diffusion cap is non-linear and
voltage dependent.
For simplicity, we will take it as
constant in this course.
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
11
MOSFET Capacitance Summary

Dependence of MOS capacitances on W and L:
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
12
MOSFET Capacitance Summary
G
CGS
CGS  CGCS  CGSO
CGD
D
S
CGD  CGCD  CGDO
CGB  CGCB
CGB
CSB
CDB
CSB  CSdiff
CDB  CDdiff
B
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
13
5.2
5.1 MOSFET Capacitance
5.2 Inverter Delay
Capacitance Model
5.3 Driving a Load
OK, so we saw that the MOSFET has a bunch of non-linear
parasitic capacitances, which makes them tough to use. To
simplify life we’ll now develop an:
INVERTER DELAY CAPACITANCE MODEL
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
14
Capacitance Modeling





As we saw, MOSFET capacitances are non-constant and
non-linear.
Therefore, it is hard to solve a general equation for an
arbitrary transition/operation.
Instead, we will develop a simple model that will
approximate the capacitances during a specific transition
that interests us.
In this case, we are looking for the Load Capacitance to
use when finding the gate delay.
Therefore, we will apply a step function to the input of an
inverter and approximate the capacitances according to the
MOSFET parasitics we just learned.
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
15
Capacitance Modeling

Let’s look at a CMOS inverter with all
C
its parasitic capacitances:
GSP
S
» Considering the Gates of the
G
transistors are the inputs to the
B
inverter, any capacitor touching the
CGBP
CGDP
D
gate should be considered
Vin
CGDN
input capacitance.
D
» Considering the Drains of the
transistors are connected to the
CGBN
G
B
inverter output, any capacitor touching
CGSN
S
the Drains should be considered
output capacitance.
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
CSBP
CDBP
Vout
CDBN
Lecture 5: Capacitances and Loads
CSBN
16
Capacitance Modeling

We have to differentiate between output (intrinsic)
capacitances and load (extrinsic) capacitances.
Driver
Load
Cwire
Cout,1
Cin,2
Cint

Cext
Our total load capacitance is CLoad  Cout ,1  Cwire  Cin,2
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
17
Intrinsic (Output) Capacitance


We’ll now look at what makes up the
intrinsic output capacitance of the driver.
This is primarily made up of diffusion
capacitances:
» Both drain-to-body capacitances have a terminal
with a constant voltage and the other connected
to the output.
CDBP
CDBP
+CDBN
» For a simple computation, we will replace them
with an equivalent capacitance to ground.
CDBN
» These capacitances are very non-linear and we
will not go into their calculation in this course.
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
18
Intrinsic (Output) Capacitance

How about feedthrough capacitance?
» Taking the input step as ideal, the gate-to-source
and gate-to-body capacitances don’t contribute to
the propagation delay.
» The source-to-body capacitance is shorted to
the supply, so it doesn’t switch.

CGSP+CGBP
CGDP+CGDN
What about the gate-to-drain capacitance?
» While the gate voltage rises (Vin), the drain voltage
drops (Vout) and vice versa.
» According to the Miller Effect, we can move this
capacitance relative to ground, doubling its value.
» This can be regarded as overlap capacitance, as CGSN+CGBN
for the majority of the transition the devices are in
cutoff or saturation.
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
2(CGDP
+CGDN)
19
The Miller Effect

A capacitor experiencing identical, but opposite
voltage swings at both its terminals can be
replaced by a capacitor to ground, whose value is
twice the original value.
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
20
Summary of Intrinsic Output Cap
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
21
External Capacitance



Now, to annotate the parasitics during switching, we will
cascade another inverter after the first.
We first add the Wire Capacitance.
CGP2
Then we add the gate capacitances of
the second inverter.
» These are approximately the oxide
capacitance times the area:
P2
P1
CGN 2  CGP 2  COX WN 2 LN 2  WP 2 LP 2 
N1
» Again, we can just add the pMOS gate
capacitance to the general capacitance to
ground.
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
CW
N2
CGN2
Lecture 5: Capacitances and Loads
22
External Capacitance

What happened to overlap capacitance and the
Miller Effect on CGD2?
» Remember that this is an approximate model, but…
» L=Leff+2*Lov, so CG=Cox*W*Ldrawn.
» During the transient, for most of the time the load gate’s
transistors are in cutoff or in linear.
» Miller effect won’t appear, because the second gate
won’t switch until tpd1 is over.

Therefore:
» YES, CGD2 and CGS2 contribute to the load capacitance.
» BUT, a good approximation is just CG2=COX*W*L
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
23
Summary of Next Stage Input Cap
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
24
Parasitic Capacitances - Summary

Altogether, as a very general approximation, we get:
Cload  2(CGDP1  CGDN 1 )   CDBP1  CDBN 1    CGP 2  CGN 2   CW
Miller

Diffusion
An even more general approximation
with N fan-out gates gives us:
Cload  Cout  Cwire  N  Cin
CGP2
Load
P1 CDBP1
P2
CGDP1+CGDN1
N1
CDBN1
+CW
N2
CGN2
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
25
Last Time…

CMOS Inverter Capacitance Model for tpd.
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
26
Last Time…

MOS Capacitance Model Cload  Cout  Cwire  N  Cin
» Driver Cap (Cout or Cint): Diffusion + Miller
» Load Cap (Cin or Cg): Gate cap, no miller
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
27
5.3
5.1 MOSFET Capacitance
5.2 Inverter Delay
Capacitance Model
5.3 Driving a Load
Up till now, we discussed device sizing with an
optimal fanout of 1. What happens if we want to
cascade more gates to the output?
DRIVING A LOAD
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
28
External Capacitance



Up till now, we assumed our inverter was only driving a
copy of itself. This is known as intrinsic or unloaded delay.
But we usually will have a larger fanout, and in some
cases, we will need to drive large loads.
Let’s remember how we defined our load capacitance:
Cload   Cdiff  Coverlap    C fanout  Cwire 
Driver
Load
Cint  Cext
Cwire
We can now write our delay
equation according to these
components.
t pd  0.69ReqCload  0.69Req  Cint  Cext 

Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Cout,1
Cin,2
Cint
Cext
Lecture 5: Capacitances and Loads
29
Sizing Factor (S)


t pd  0.69Req  Cint  Cext 
This means that if we add a larger
load, our delay will increase. This is intuitive, as it means
we have to supply more current from the same source.
If we were to widen our transistors by a factor S, this would
decrease our resistance and increase our intrinsic
*
capacitance.
Cint
 S  Cint Req*  Req S
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
30
Sizing Factor (S)
*
Cint
 S  Cint Req*  Req S
t pd  0.69Req  Cint  Cext 
These two factors trade-off, which is why we get an optimal
inverter size. *
R

*
t pd ,unloaded  0.69 Req* Cint
 0.69  eq   S  Cint   0.69ReqCint
 S

However, upsizing our gate doesn’t affect the external
capacitance and therefore decreases the loaded delay.
t
*
pd


Cext 
Cext 
 0.69
 SCint  Cext   0.69ReqCint 1 
  t p 0 1 

S
SC
SC
int 
int 


Req
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
31
Sizing Factor (S)
C

t p  t p 0 1  ext

SC
int 

t p 0  0.69 Req Cint
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
32
Driving a Large Load

So now we have a very large load to drive.

We could just use a very large inverter.
» But then someone would have to drive this large
inverter.

So considering we start with a limited input
capacitance, how should we best drive this load?
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
34
Inverter Chain
In
Out
CL

If CL is given:
» How many stages are needed to minimize the
delay?
» How to size the inverters?

Anyone want to guess the solution?
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
35
Delay Optimization Problem #1

To solve an optimization problem, we need a set of
constraints:
» Load Capacitance.
» Number of Inverters.
» Size of input capacitance.
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
36
Delay Optimization Problem #1

To explore this problem, we must define
a proportionality factor, γ.

γ is a function of technology*, that describes the
relationship between a gate’s input gate capacitance (Cg)
and its intrinsic output capacitance (Cint):
Cint
 Cg
* γ is close to 1 for most submicron processes!
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
37
Delay Optimization Problem #1

 Cg
Now, we will write the delay as a function of γ, and the
effective fanout, f:
Cext
 Cext 

f
t pd  t p 0 1 
 t 1
  C  p 0   
g 


Cint
f
Cg
We can see that the delay for a certain technology is only a
function of the effective fanout!
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
38
Inverter with Load

So we see that the delay
increases with ratio of load
to inverter size:

f 
t p  t p 0 1  
  
is the intrinsic delay of an unloaded inverter.
 γ is a technology dependent ratio.
 f is the Effective Fanout – ratio of load to inverter size
 tp0
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
39
Sizing a chain of inverters

Now we will express the delay
of a chain of inverters:

Assuming a negligible wire capacitance,
for the j-th stage, we get:
t pd , j


f 
t p  t p 0 1  
  
 Cg , j 1 
fj 

 t p 0 1    t p 0 1 


 Cg , j 
  

And we can write the total delay as:
N
t pd   t pd , j
j 1
Digital Microelectronic Circuits
 Cg , j 1 
 t p 0  1 


 Cg , j 
j 1 
N
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
40
Sizing a chain of inverters

We have N-1 unknowns, so we will derive N-1 partial
derivatives: t pd
Cg , j

0
We receive a set of constraints:
Cg , j 1
Cg , j

 Cg , j 1 
t pd  t p 0  1 



C
j 1 
g, j 
N

Cg , j
Cg , j 1
 Cg , j  Cg , j 1Cg , j 1
This means that:
» Each inverter is sized up by the same factor, f.
» Each inverter has the same effective fanout, fj=f.
» Each inverter has the same delay, tp0(1+f/ γ).
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
41
Sizing a chain of inverters

f
N

Now this is interesting…
what if we multiply the fanout of each stage?:
N
N
Cg , j 1
j 1
j 1
Cg , j
  fj  
Cg ,2 Cg ,3 Cg ,4
Cg , N Cload Cload






Cg ,1 Cg ,2 Cg ,3 Cg , N 1 Cg , N Cg ,1
We found the ratio between input and load capacitance!
f  Cload / Cg ,1  F
N
Digital Microelectronic Circuits
N
The VLSI Systems Center - BGU
F
Cload
Cg ,1
Lecture 5: Capacitances and Loads
42
Sizing a chain of inverters
f  F
N

F
Cload
Cg ,1
We defined the overall effective fanout, F, between the input
and load capacitance of the circuit. Using this parameter,
we can express the total delay:
t pd
 NF
 N  t p 0  1 

 

Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
43
Example: 3 Stages
S=1
S=2
S=4
In
C1
Out
1
f
f2
CL= 8 C1
CL/C1 has to be evenly distributed across N = 3 stages:
f 38 2
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
44
Delay Optimization Problem #2
Great – but what is the optimal Number of Stages?
 This is a new Optimization Problem. You are given:

» The size of the first inverter
» The size of the load that needs to be driven

Your goal:
» Minimize delay by finding optimal number and sizes of
gates

So, need to find N that minimizes:
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
 NF
t p  N  t p 0 1 


Lecture 5: Capacitances and Loads
45



Delay Optimization Problem #2
t pd

 NF
 N  t p 0  1 




Starting with a minimum sized inverter with Cg,min, and
driving a given load, Cload, we can see that:
» With a small number of stages, we get a large delay due to the
effective fanout (f, F).
» With a large number of stages, we get a large delay due to the
intrinsic delay (Ntp0)

To find the optimal number of stages, we will differentiate
and equate to zero.
dt pd
dN
Digital Microelectronic Circuits
0
N
F ln F
 F
0
N
N
The VLSI Systems Center - BGU


f opt  exp 1  
f opt 

Lecture 5: Capacitances and Loads
46
Delay Optimization Problem #2

This equation only has an analytical solution for the case of
γ=0. In this esoteric case we get:
f opt



f opt  exp 1  
f opt 

 0
 e  2.718
Nopt
 0
 ln F
If we take the typical case of γ=1, we can numerically solve
the equation and arrive at:
f opt
 1
 3.6
Digital Microelectronic Circuits
Nopt
 1
 log3.6 F
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
47
Example

We are given:
CL  64Cmin
Cin  Cmin

We need to find the optimal
number of stages, so fopt=4.
F
CL
Cin
 64
N opt  log fopt F  log 4 64  3

So we need 3 stages that will be sized 1, 4, 16.

Let’s inspect what delay we would have gotten with
various number of stages.
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
48
Example
1
8
1
4
16
2.8
8
1
N
f
tp
1
64
65
2
8
18
64
3
4
15
64
4
2.8
15.3
64
1
Digital Microelectronic Circuits
64
22.6
t pd
 NF
 N  t p 0  1 




The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
49
Normalized delay function of F

t pd
 NF
 N  t p 0  1 

 

Let’s consider the trade offs of
driving loads with various approaches:
» Unbuffered
» Two-Stages
» Optimal FO4 Chain

For a small load, F=10:
» Unbuffered delay: tpd=11tp0
» Two Stage delay: tpd=8.3tp0
» Optimal FO4 Chain: Nopt=2tpd=8.3tp0
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
50
Normalized delay function of F

For a slightly larger load, F=100:
»
»
»
»

t pd
 NF
 N  t p 0  1 

 

Unbuffered delay: tpd=101tp0
Two Stage delay: tpd=22tp0
Optimal FO4 Chain: Nopt=4 tpd=16.6tp0
We see a large benefit for one extra stage, but the
inverter chain might not be worth it.
How about a really large load, F=10000:
»
»
»
»
Unbuffered delay: tpd=10001tp0
Two Stage delay: tpd=202tp0
Optimal FO4 Chain: Nopt=7 tpd=33.1tp0
But we “pay” for this with a large number of stages and
huge final stage inverter (W=1mm)
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
51
What about Energy (and Area)?

How much additional Energy (and Area) does an
inverter chain cost?
» Using a single (minimal) inverter, our capacitance would
be:
C1 stage  Cmin   Cmin  CL
» But the capacitance of N stages
CN  stages  1    Cmin  1    fCmin  ...  1    f N 1Cmin  CL
 C1 stage  1    fCmin  ...  1    f N 1Cmin
Overhead!
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
52
What about Energy (and Area)?
So the overhead cap is:
Coverhead  1    fCmin 1  f  ...  f N  2 

 f N 1  1 
 1    fCmin 

f

1



For example:
CL  20 pF , Cmin  50 fF
20 pF
F
 400, N opt  5, f  5 400  3.3
50 fF
15  117.6 
Coverhead  2  3.3  50 10 
  9.7 pF
 4 
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
53
Example Overhead Numbers

For the previous example:
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
54
Conclusions

In order to drive a large load, we should:
» Use a chain of inverters.
» Each inverter should increase its size by the same
amount.
» To minimize the delay, we should set the effective fanout
to about 4.

Remember!
» You have to use a whole number of stages (i.e. you can’t
choose 2.5 stages).
» Therefore, choose the closest number of stages for close
to optimal effective fanout..
» Choose according to signal polarity or optimal speed.
» But fewer stages means less power!
Digital Microelectronic Circuits
The VLSI Systems Center - BGU
Lecture 5: Capacitances and Loads
55