ECOM 4023|Hardware Description
Languages Lab
Lab#2
Data Types and operations
Dr. Ruba A. Salamah
Eng. Enaam H. Rajab
Fall 2022 - 2023
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Lab Objectives:
✓ To Learn what the lexical element in VHDL.
✓ To Learn an overview of objects and types.
✓ To Learn about Data Type predefined in VHDL.
✓ To Learn how defined new Data Type.
✓ To Learn what are the operations that can performed on the object
based on Data Type for this object.
Introduction:
The concept of type is important when describing data in VHDL model.
All signals in VHDL have a declared type. A signal’s type determines the set of
values it can take and the operations that can be performed on those values.
Every signal must be declared before it is used. Signals belong to a class of
VHDL language elements called objects. An object is a named item that has a
value of a specified type.
Ports of a design entity are signals. From the viewpoint of a design entity, its
ports can be thought of as external signals, which are simply referred to as
ports.
Signals within a design entity can be thought of as local or internal signals,
which are simply referred to as signals.
A port’s name is visible in the entity declaration in which it is declared and in any
architecture bodies associated with that entity declaration.
A signal declared in the declarative part of an architecture body can only be
used within that architecture; it is not visible outside of that architecture.
VHDL code is inherently concurrent (parallel). Only statements placed inside a
process, function, or procedure are sequential. Concurrent code is also called
dataflow code.
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Lexical elements:
The lexical elements are the basic syntactical units in a VHDL program. They
include comments, identifiers, reserved words, numbers, characters, and strings.
Comments: A comment starts with two dashes, --, followed by the line comment
text comments.
Identifiers: An identifier is the name of an object in VHDL. The basic rules to
form an identifier are:
✓
✓
✓
✓
The identifier can contain only alphabetic letters, decimal digits, and underscores.
The first character must be a letter.
The last character cannot be an underscore.
No successive underscores are not allowed.
Reserved words: Some words are reserved in VHDL to form the basic language
constructs. Such as: after, process, alias, architecture, assert and so on.
Numbers, characters, and strings: A number in VHDL can be integer, such as 0,
1234 and 98E7, or real, such as 0.0, l.23456 or 9.87E6.
It can be represented in other number bases. For example, 45 can be
represented as 2#101101# and 16#2D# in base 2 and base 16 respectively.
A character in VHDL is enclosed in single quotation marks, such as ‘Z’.
A string is a sequence of characters enclosed in double quotation marks, such as
"Hello" and "10000111".
Again, note that that 2#10110010# and "10110010" are different since the
former is a number and the latter is a string.
Objects in VHDL:
An object in VHDL is a named item that holds the value of a specific data type.
There are four kinds of objects: signal, variable, constant and file.
Signals: The signal is the most common object which must be declared in the
architecture body’s declaration section. The simplified syntax of signal
declaration is:
signal signal-name, signal-name, . . . : data-type;
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Variables: A variable is a concept found in a traditional programming language.
It can be thought of as a ‘symbolic memory location‛ where a value can be
stored and modified. There is no direct mapping between a variable and a
hardware part. A variable can only be declared and used in a process and is
local to that process.
The syntax of variable declaration is similar to that of signal declaration:
variable variable-name, variable-name, . . . : data-type
Constants: A constant holds a value that cannot be changed. The syntax of
constant declaration is:
constant constant-name: d a t a - t y p e := v a l u e - e x p r e s s i o n;
Datatypes in VHDL:
The type of a data object defines the set of values that the object can assume,
as well as the set of operation that can be performed on those values.
VHDL along with its packages provides pre-defined types. Additionally, the user
can define new types.
Scalar Data Types and Operations
•
Integer Types: “integer” is a pre-defined type used to represent whole
numbers from −𝟐𝟑𝟏 𝒕𝒐 𝟐−𝟑𝟏 − 𝟏
e.g., variable x, y: integer;
✓ User can define new “integer” types using a range_constrained type
definition.
✓
e.g., type month is range 1 to 12;
type count_down is range 10 downto 0;
Operations on Integer Types: Addition: + ,Subtraction or negation: -,
Multiplication: *, Division: /, Modulo: mod, Remainder: rem, Absolute value:
abs, Exponentiation: **, Logical: =, /=, , <=, >=.
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Floating-point Types: They are used to represent real numbers.
User can define new “Floating-point” types using a range constrained type
definition.
e.g. type probability is range 0.0 to 1.0;
✓ Operations on Floating-point Types are:
+ , - , * , / , abs , **, = , /= , < , > , <=, >=.
Physical Types: They represent real world physical quantities, such as
length, mass, and time.
✓ A physical type includes the primary unit, which is the smallest represented
unit, and may include some secondary units, which are integral multiples of
the primary unit.
✓ Time is a pre_defined physical type.
✓ Operations on physical types are:
+ , - , * , / , abs , **, = , /= , < , > , <=, >=.
Enumeration Types: Useful for giving names to values of an object
(variable or signal).
e.g. type alu_func is (disable, pass, add, sub, mult, div);
✓ Predefined Enumeration types are Character, Boolean, Bit, and Standard
Logic.
▪ Characters Type:
e.g. type character is (nul, soh,…,‘a’, ‘b’, ‘c’, ………);
✓ Operations on Characters Type: =, /=, <, >, <=, >=
▪ Boolean Type:
e.g. type boolean is ( false,true);
✓ Operations on Boolean Type: and, or, nand, nor, xor, xnor, not, =,
/=, <, >, <=, >=
▪ Bit Type:
e.g. type bit is (‘0’, ‘1’);
✓ Operations on Bit Type:
Logical: =, /=, <, >, <=, >=
Boolean: and, or, nand, nor, xor, xnor, not
Shift: sll, srl, sla, sra, rol, ror
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▪
•
Standard Logic Type: is defined in the IEEE library in VHDL and can be
declared using the "std_logic" keyword.
Composite Data Types and Operations
A composite type consists of a collection of related elements that form either
an array or a record.
Arrays: An array consists of a collection of values of the same type; each
of these values has an index indicating its position in the array.
type bit_vector is array ( natural range <> ) of bit;
type word1 is array (0 to 31) of bit;
✓ This array stores values of bit type indexed by the integers from 0 to 31.
✓ Indexes may be of any scalar data type.
type state is (initial, idle, active, error);
type state_counts1 is array (state) of natural;
✓ Std_logic_vector is a one-dimensional unconstrained array of elements
of type std_logic that is defined in package STD_LOGIC_1164 as:
type std_logic_vector is array ( natural range <> ) of std_logic;
e.g. signal databyte: std_logic_vector (7 downto 0);
Multi-dimensional arrays: is declared by specifying a list of index
ranges each of them can be specified for single-dimensional array.
type symbol is (‘a’, ‘t’, ‘d’, ‘h’);
type state is range 0 to 6;
type trans_matrix is array (state, symbol) of state;
Records: is a composite value comprising elements of different types.
type time_stamp is record
seconds: integer range 0 to 59;
minutes: integer range 0 to 59;
hours: integer range 0 to 23;
end record;
✓ Each value can be selected separately using the (.) operator.
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Lab Exercise (1):
Which of the following statement(s) in the functional description of the
architecture body is (are) correct (legal VHDL)?
ARCHITECTURE exercise OF operators IS
SIGNAL bool: BOOLEAN;
SIGNAL a_int: INTEGER RANGE 0 TO 15;
SIGNAL b_int: INTEGER RANGE 0 TO 15;
SIGNAL z_int: INTEGER RANGE 0 TO 15;
SIGNAL z_bit: bit;
SIGNAL b_vec: bit_vector;
BEGIN
z_bit <= a_int = b_int; -- statement 1
bool <= a_int > b_int; -- statement 2
z_int <= b_int + "1010"; -- statement 3
z_int <= a_int + b_int; -- statement 4
END exercise;
Lab Exercise (2):
Write an entity declaration & an architecture body to adds the two input ports a
and b of the integer type, both having a range of 1 to 256 and assigns the result
to the output port with a range of 2 to 512, to accommodate the possible
maximum value of the sum. Show some random input combinations in your test
bench.
Lab Exercise (3):
Write an entity declaration & an architecture body for a program that checks
whether an integer number is even or odd.
The input port is with the integer type and having a range of 1 to 256. Show
some random input combinations in your test bench.
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Homework Exercise (1):
Write an entity declaration & an architecture body for a program that calculates
the area and perimeter of a rectangle. Show some random input combinations in
your test bench.
Homework Exercise (2):
Write an entity declaration & an architecture body for a program that calculates
the sum and product of two 8-bit unsigned numbers.
Note that we have concatenated a 0 bit to the MSB of the input numbers to
make them 9-bit and 16-bit wide for the sum and product calculations
respectively. Show some random input combinations in your test bench.
Homework Exercise (3):
Define a record type declaration that includes a day, month and year values.
Declare a variable of this record type and get its elements separately in
variables.