EEE 525: VLSI Design, L-05
Interconnect
Vidya Chhabria, vidyachhabria@asu.edu, GWC672
Highlight
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▪
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Multi-level on-chip interconnects
Interconnect parasitics
Delay and crosstalk noise
Reading: Chapter 3, Chapter 6
EEE525, ASU, V. Chhabria
Lecture 05
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Highlight
▪
▪
▪
▪
Multi-level on-chip interconnects
Interconnect parasitics
Delay and crosstalk noise
Reading: Chapter 3, Chapter 6
EEE525, ASU, V. Chhabria
Lecture 05
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Interconnect
▪ Chips are mostly made of wires
– In stick diagram, wires set size
– Transistors are little under the wires
– Many layers of wires
▪ Wires are as important as transistors
– Speed
– Power
– Noise
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Multi-layer Structure
▪ Modern processes use 6-10+ metal layers
– M1/2: thin, narrow, high density
– Mid layers: thicker and wider (density vs. speed)
– Top layers: thickest for VDD/GND, clock, global signaling
▪ Alternating layers run orthogonally
Intel 22nm
Interconnect
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Lecture 05
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More and More Important Roles
▪ Wires are as important as transistors
– Timing (35% ~ 45% time delay comes from wires)
– Power
– Noise
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Lecture 05
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Wire Length Distribution
Connection Probability
▪ Local and global wires distributed in a non-uniform way
Majority of interconnects are short local wires:
Intra cell and intra block wires
0.06
0.04
RC modeling needed
Global signals that need
better design and planning
0.02
0.2
0.4
0.6
0.8
1.0
Wire length/chip diagonal
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Lecture 05
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Tracks for Routing
▪ Imaginary lines that serve as guides for routing
interconnects.
▪ A wiring route always follows the predefined tracks
▪ Track spacing is typically the minimum allowable DRC
spacing between two wires drawn at minimum width
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Lecture 04
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Highlight
▪
▪
▪
▪
Multi-level on-chip interconnects
Interconnect parasitics
Delay and crosstalk noise
Reading: Chapter 3, Chapter 6
EEE525, ASU, V. Chhabria
Lecture 05
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Parasitic Parameters
▪ Resistive (R) and Capacitive (C)
▪ Inductive (L): only important in limited cases
▪ Impact on circuit performance
– Slow down the signal
– Increase power consumption
– Reduce reliability
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Lecture 05
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Wire Resistance
▪ R: resistance along the length
▪ ρ(·m): resistivity (Cu 1.7x10-8; Al - 2.7x10-8)
▪ (ρ/t): sheet resistance
▪ Poly gate has resistivity 100x
than that of Al
▪ Lower R:
– Smaller ρ
– Larger w and t
– Scale w and t with l
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l
t
R=
w
 l

t w
Layer
Sheet Resistance (/)
Poly
3-10
Metal1
0.08
Metal2
0.05
Metal3
0.05
Metal4
0.03
Metal5
0.02
Metal6
0.02
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Contact and Via Resistance
▪ Contacts and vias also have 2-20 
▪ Use many contacts for lower R
– Many small contacts for current crowding around periphery
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Lecture 05
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Wire Capacitance
Ccoupling
W
t
s
▪
▪
▪
▪
C: 2D extraction
Neighbor layers are modeled
: air – 1; SiO2 – 3.9
Low-k or even airgap
h
Cground
C g = C parallel − plate + C fringe
 w
=    0    + C fringe
h
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Cc = C parallel − plate + C fringe
t
=    0    + C fringe
s
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Capacitance in Scaling
▪ R: resistivity goes up because of grain boundaries
▪ C: total C goes down, but Cc/Cg increases as a result
of larger t/w; fringe capacitance can also be an issue
▪ RC delay goes up after 22nm
[IEDM 2010]
EEE525, ASU, V. Chhabria
Lecture 05
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Highlight
▪
▪
▪
▪
Multi-level on-chip interconnects
Interconnect parasitics
Delay and crosstalk noise
Reading: Chapter 3, Chapter 6
EEE525, ASU, V. Chhabria
Lecture 05
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Modeling a RC Network
▪ If Rtotal << Rdriver, then
we only need C
▪ If (RC)segment << Tr,
then we can use a
lumped RC
▪ RC delay should be
considered when
– tRC >> tgate of the driver
– Tr at the line input is
Rdriver
tgate
twire
smaller than RC
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Lecture 05
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Elmore Delay
Vin
Rd
r
Cd
r
c
r
c
r
c
Vout
CL
▪ Question: what’s the delay from Vin to each node?
▪ Look at which caps need to be charged through
which resistors to get to the node in question


T = 0.69 = 0.69  Ci   R j 
i 
j

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Lecture 05
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Delay of a Distributed RC Line
Rd
r·(L/N)
N segments
Vin
Cd
Vout
CL
c·(L/N)


T = 0.69 = 0.69  Ci   R j 
i 
j

N

 rL
 cL 
= 0.69 (Rd + rL )C L + Rd Cd +   i  + Rd   
N
 N
i =1 

N ( N + 1) rL cL


= 0.69 (Rd + rL )C L + Rd Cd +
  + Rd (cL )
2
N N




rcL2
= 0.69 (Rd + rL )C L + Rd Cd +
+ Rd (cL )
2


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Lecture 05
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Driving a Long Wire
Rd/w, Cdw
Identical receiver
rL, cL
rcL2 Rd
 Rd

(cL)
 =  + rL Cd w + Rd Cd +
+
2
w
 w

Rd cL  rcL2

= 2 Rd Cd +  rLC d w +
+
w 
2

 min : rLC d w =
Rd cL
w
c Rd
w=

r Cd
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Lecture 05
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Crosstalk Noise
▪ Crosstalk can be induced by the adjacent line
switching through the coupling capacitance (Cc)
▪ This affects both timing and signal integrity
Attacker
Cc
Victim
Cg
Cc
Noise on a quiet victim 
VDD
C g + Cc
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Lecture 05
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Impact on Timing
Attacker
V
Cc
Cg
Vdd/2
Victim
t
Victim
Ceff
Ceff = Cg + Cc  (1 − M )
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− 1 for out - phase switching

M = 0
for quiet attacker
 1 for in - phase switching

Lecture 05
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Noise Reduction
Cc
Noise on a quiet victim 
VDD
C g + Cc
▪ Crosstalk gets worse with
increasing Cc/Cg
▪ Routing: separate the lines
as far as possible
▪ Buffer insertion: break long
distance coupling
▪ Design optimization: noiseaware routing and encoding
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Lecture 05
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Summary
▪ Wiring is expensive (gates are cheap)
– Cost on delay, energy and area
– Routability depends on wiring density, number of
layers and design scale
▪ Additional issues on signal integrity
– Solutions usually involve the tradeoff between noise
reduction and wiring cost
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Lecture 05
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