Hybrid Switched Capacitor DC-DC Converter
Based On MMC
Marcus Vieira Soares
Gustavo Lambert
Yales Rômulo de Novaes
Dept. of Electrical Engineering
Santa Catarina State University
Joinville, Brazil
marcus.sov@gmail.com
Dept. of Electrical Engineering
Santa Catarina State University
Joinville, Brazil
gustavolambert@outlook.com
Dept. of Electrical Engineering
Santa Catarina State University
Joinville, Brazil
yales.novaes@udesc.br
Abstract—Different types of dc-dc converters have been subject
of research to fulfill the need of interconnecting renewable
generation sources, existing or new grids, electronic loads and
battery based systems. To deal with high voltage levels and
high power, Modular Multilevel Converter based structures have
been proposed. On the other hand, for lower power ratings,
Switched Capacitor and Hybrid Switched Capacitor converters
have emerged due to their simple structures and self voltage
balancing characteristics. In this scenario, a non-isolated Hybrid
Switched Capacitor dc-dc converter based on Modular Multilevel Converter is proposed and its unidirectional structure is
examined through circuit analysis. In the proposed converter, the
voltage static gain is independent of the number of submodules,
allowing a good regulation range of the output voltage for high
voltage applications. Moreover, the Switched Capacitor behavior
provides automatic clamp of the arms voltages, avoiding the need
of ac loops to perform the arms voltage balance. A converter
design methodology based on current spikes limitation is also
proposed. All the theoretical analysis and the design methodology
are validated through comparisons with simulated waveforms.
Index Terms—Switched Capacitor, Modular Multilevel Converter, MMC, Hybrid Switched Capacitor, Non-Isolated DC-DC
Converters.
I. I NTRODUCTION
The growth of concentrated and distributed energy generation via renewable sources, the increasing use of electronic
loads and batteries in general society, going from different
types of industries to data-centers and domestic applications,
and the continuous development of semiconductors able to
operate with higher voltages and currents has led to the
research of dc-dc converters capable to adapt the different
voltage levels used on these scenarios.
In order to deal with medium/high voltage and high power
processing, Modular Multilevel Converter (MMC) based dcdc topologies have been investigated in literature. Isolated
converters, such as the Front-to-Front Modular Multilevel
Converter [1], feature high modularity, galvanic isolation and
high voltage gain provided by the medium frequency transformer (MFT). However, the MFT has to process the total
output power and its design is still a challenge, mainly when
high dv/dt is applied on the windings [2].
This work was developed with the suport of the Programa Nacional de
Cooperação Acadêmica da Coordenação de Aperfeiçoamento de Pessoal de
Nı́vel Superior – CAPES/Brazil. The authors would like to thank FAPESC
and UDESC for their financial support.
Also based on MMC, the dc auto-transformer converters
proposed in [3] and [4] allows the reduction of the power
processed by the transformer creating a direct dc power path
between the dc input and the dc output of the converter. The
lower the difference between the input and output voltages, the
lower is the transformer processed power. Despite the presence
of the transformer in the structure, creating the ac power path
to perform the dc voltage links balancing, there is no galvanic
isolation between the dc input and output voltages.
A variety of transformerless high power dc-dc converters
based on MMC has been presented in [5]–[11], where the
ac power path needed to balance the dc voltage links is
composed by capacitors, submodules (SM) or inductors. These
structures tend to be less bulky than the dc-dc auto-transformer
converters. However, the gain provided by the transformer
turns ratio is lost which increases the losses when there is
a large difference between the input and output dc voltages.
Switched Capacitor (SC) and Hybrid Switched Capacitor
(HSC) converters have been subject of studies to be used in
different applications where the power rating is higher than
the usual for these types of converters. The scalability, the
capacitors voltage clamp and the self-voltage balancing are the
main features of these structures. However, the output voltage
control limitations and the need to attenuate the current spikes
are important drawbacks of SC and HSC converters [12]–[15].
A Hybrid Switched Capacitor dc-dc converter based on
MMC is presented in this paper. The unidirectional version
of the converter is used to describe its topological stages and
to extract the main static characteristics of the structure. A
preliminary design methodology based on the limitation of
the components current spikes is also presented and validated
by simulation.
II. P ROPOSED DC - DC CONVERTER
The proposed structure presented in this work is a nonisolated and bidirectional dc-dc converter based on hybrid
switched-capacitor converter. It can be seen as a three-level
Flying Capacitor dc-dc converter with the switches replaced
by power SMs. The SMs of the upper arms (A1 and A2)
can assume different configurations, such as Half-Bridge and
Full-Bridge, where each configuration has its particularities
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Vin
+
−
Csm
A1
Csm
A2
Lo
Csm
A3
Cf c
Co
Csm
Ro
A4
Fig. 1. DC-DC converter
regarding losses and short-circuit protection. Fig. 1 presents a
representative diagram of the proposed converter.
Each arm of the converter is composed of N series connected SM and behaves as a switch. It means that, out of
the topological stage transitions, all the arm SMs must have
their capacitors either inserted or bypassed, emulating an open
switch and a closed switch, respectively. Therefore, the arms
can be seen as switches and they must respect the following logic to avoid short-circuits and voltage inconsistencies:
A1 = A4 and A2 = A3.
Similar to the three-level Flying Capacitor dc converter, the
proposed structure is composed of a flying capacitor (Cf c ) and
an LC output filter (Lo and Co ). In order to keep the capacitor
with an average voltage equal to half the input voltage (Vin /2),
the flying capacitor must be charged and discharged equally.
This proper operation allows the generation of a voltage with
twice the switching frequency (2fs ) on the LC filter input,
providing size reduction of Lo and Co . However, a control
loop must be used to regulate the Cf c average voltage on the
correct level, which increases the system complexity.
Assuming that the Cf c average voltage is regulated on
Vin /2 and the arms to behave as complementary switches
(A1 = A4 and A2 = A3), it can be shown that the total
voltage of each arm is clamped either by the set of input
voltage source Vin and Cf c or just by Cf c . This clamping
has a switched-capacitor characteristic, since the input voltage
source, the flying capacitor and a set of SM capacitors are
periodically connected in parallel. This operation technique
keeps each arm total voltage automatically balanced, including
the external arms A1 and A4 voltages, since the Cf c voltage
is controlled. It avoids the need of an ac power path to achieve
this balancing. However, the capacitors, the on-resistances
of the semiconductors and the switching frequency must be
carefully chosen to ensure operation with low losses and low
current spikes.
As other dc based Modular Multilevel converters, the proposed structure is able to operate with a high input voltage by
the series connection of several low voltage SMs. However,
natural differences on the capacitance values and on the
switching times of the same arm SM’s can cause the SMs
capacitor voltage to deviate from each other. Therefore, a SM
voltage balance method must be applied to ensure the proper
operation of the converter.
The SM voltage balance method chosen for this structure
is the Quasi-Two-Level modulation [16], where a stepped
transition between the topological stages is made by using
the SMs individually. The steps must respect an order so that
the capacitors of the upper arms SMs with the lowest voltage
can stay in the output current-source path for a longer time,
charging more than the other capacitors of the same arm. On
the other hand, the capacitors of the lower arms SMs with the
highest voltage must stay in the output current-source path for
a longer time, discharging more than the other capacitors of the
same arm. With this procedure, the capacitors which compose
an arm achieve the voltage balance among them. Moreover, the
stepped transitions also reduce the dv/dt over the inductor Lo
when compared to the standard Two-Level modulation, since
the voltage applied on the input of the LC filter inherits the
stepped transition waveform. This characteristic is important
to ensure a good lifetime for the inductor insulation material
and to avoid parasitic currents on the converter, mainly when
high dc voltage levels are applied on the converter input.
A. Topological stages
Some considerations are made in order to simplify the
analysis of the converter topological stages:
•
•
•
•
•
•
•
•
•
A unidirectional type of the converter is used;
All the SMs are equal and configured as a Half-Bridge
circuit (bidirectional on the upper arms and unidirectional
on the lower arms);
The MOSFET switches have an on-resistance
RDSon = R;
All the diodes operate with a forward conduction resistance Rf on = R and zero forward voltage drop;
Each arm is composed by N series-connected SMs,
which are represented by an equivalent SM per arm;
The capacitance of the flying capacitor Cf c is at
least ten times higher than the total arm capacitance
Ceqx = Csm /N , where Csm is the capacitance of each
SM and x = {1, 2, 3, 4} is the arm number. This simplification is assumed to be suitable because the converter
is directed to applications with high input voltage, which
requests a relevant number of series SMs per arm. Therefore, the total arm capacitance tends to be much lower
than Cf c ;
The topological stages transition time (ttr ) is much
lower than half the switching period (Ts /2), making the
transition effects negligible;
The converter is operated only with positive inductor
current;
Only the converter operation for Vo /Vin ≤ 0.5 is approached.
The topological stages are described in Table I, where
D = 2ton /Ts is the duty cycle (0 ≤ D ≤ 1), ton is the du-
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Ceq1
Ceq1
Ceq2
Vin
+
−
Ceq2
Lo
Cf c
Vin
+
−
Ceq3
Ro
Co
Ceq4
Fig. 4. Topological state 3
Ceq1
Ceq2
Lo
Cf c
Ceq3
Co
Ro
component that compose the converter. This analysis results in
important average equations used to understand and to design
the converter.
The state space representation of each topological stage is
created from the Kirchoff’s Voltage and Current Law (KVL
and KCL, respectively). The input is Vin and the state variables
are vCf c , vCeq1 , vCeq2 , vCeq3 , vCeq4 , iLo and vCo , resulting
in the following state space equation, where i = {1, 2, 3, 4}
represents the topological stage
Ceq4
ẋ = Ai · x + Bi · u
Fig. 3. Topological state 2
ration time of the topological stages 1 and 3 and the time
intervals are defined by
⎧
Δt1 = 0 ≤ t ≤ DTs /2
⎪
⎪
⎪
⎨Δt = DT /2 ≤ t ≤ T /2
2
s
s
(1)
⎪
Δt
=
T
/2
≤
t
≤
(1
+
D)Ts /2
s
⎪ 3
⎪
⎩
Δt4 = (1 + D)Ts /2 ≤ t ≤ Ts
Interval
Ceq1
Ceq2
Ceq3
Ceq4
Cf c
Lo
Stage 2
Δt2
Inserted
Inserted
Bypassed
Bypassed
Discharge
Stage 3
Δt3
Inserted
Bypassed
Inserted
Bypassed
Discharge
Charge
Stage 4
Δt4
Inserted
Inserted
Bypassed
Bypassed
Discharge
B. Average Value Static Analysis
In this section, a static analysis via average value is demonstrated in order to describe the voltages and currents of each
(2)
In steady state, the average value of each state variable is
constant. Therefore, it is possible to define ẋ = 0. Moreover,
the matrices that represent the state space for average values
are written by multiplying the topological stages matrices by
their respective duration time and dividing by the switching
period, which results in
A = A1 ·
D
(1 − D)
D
(1 − D)
+ A2 ·
+ A3 · + A4 ·
(3)
2
2
2
2
B = B1 ·
D
(1 − D)
D
(1 − D)
+ B2 ·
+ B3 · + B 4 ·
(4)
2
2
2
2
TABLE I
T OPOLOGICAL S TAGES
Stage 1
Δt1
Bypassed
Inserted
Bypassed
Inserted
Charge
Charge
Ro
Ceq4
Fig. 2. Topological state 1
Vin
Lo
Ceq3
Co
+
−
Cf c
Using (3) and (4) in (2), the state space representation of
the converter for average values becomes
0 = A · X + B · Vin
(5)
Isolating X in (5), the average values of the state variables
are obtained by
X = −A−1 · B · Vin
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(6)
⎡
⎤
⎡
V
⎢ Cf c ⎥ ⎢
⎥ ⎢ Vin
⎢
⎢VCeq1 ⎥ ⎢
2
⎥ ⎢
⎢
⎢
⎥ ⎢ Vin
⎢VCeq2 ⎥ ⎢
2
⎢
⎥ ⎢
⎢
⎥ ⎢
⎢ Vin
⎥
=
X=⎢
⎢VCeq3 ⎥ ⎢
2
⎢
⎥ ⎢
⎢
⎥ ⎢
Vin
⎢
V
⎢ Ceq4 ⎥ ⎢ 2
⎢
⎥ ⎢
⎢
⎥
⎢ ILo ⎥ ⎢
⎣
⎦ ⎢
⎣
VCo
Vin
2
1+
DN R
2N R+Ro
1+
DN R
2N R+Ro
1−
DN R
2N R+Ro
1−
DN R
2N R+Ro
Vin D
2(2N R+Ro )
Vin DRo
2(2N R+Ro )
⎤
⎥
⎥
⎥
⎥
⎥
⎥
⎥
⎥
⎥
⎥
⎥
⎥
⎥
⎥
⎥
⎥
⎥
⎦
Ts /2. Therefore, the Cf c voltage ripple and the Lo current
ripple are defined by
ΔvCf c =
(7)
where Ro is the load equivalent resistance.
Since VCo is the converter output voltage, the converter
static gain (MV DC ) is defined by
MV DC =
VCo
DRo
=
Vin
2(2N R + Ro )
(8)
Manipulating the equation for ILo obtained in (7), the
following of equation is achieved
DVin
= ILo (2N R + Ro )
2
(9)
which represents the output characteristic of the converter.
It can be seen that it is similar to the output characteristic of Buck-type converters, with the difference that the
number of SMs per arm influences on the equivalent output
impedance (2N R). It is also noticeable that the equivalent
output impedance is independent of the duty cycle, unlike the
hybrid switched capacitor converter described in [15].
The static average state model described is valid for the
cases where the current peaks caused by the switched capacitor
characteristic of the converter are low. It is important to operate
the converter in this condition because the switching losses,
the EMI and the RMS current of the semiconductors and
capacitors tend to be reduced.
ILo DTs
2Cf c
(11)
Vo (1 − D)Ts
(12)
2Lo
Considering the vCf c and iLo trapezoidal and triangular
waveforms, respectively, the equations that describe the behavior of vCeq1 and vCeq3 , presented in (2), can be developed
st3
st3
and VCeq30
.
to achieve the equations for VCeq10
st3
st3
in (10), the
Replacing the equations of VCeq10 and VCeq30
resulting equation can be parameterized by ILo , providing the
information of how high the Cf c peak current is as regards the
output current in function of fs , D, 2N RCf c and p, where
p = ΔiLo /ILo .
At the beginning of the stage 3, the voltage difference
between Cf c and Ceq1 and between Cf c and Ceq3 tends to
increase when D → 1 and p is high, also increasing ist3
Cf c pk .
However, analyzing (12), it is noticeable that p → 0 when
D = 1 and, since p stops to influence on ist3
Cf c pk , this is not
the worst peak current case. Therefore, considering a worst
case where D = 0.99 and p = 1, two-dimensional graphs
of ist3
Cf c pk /ILo can be plotted, showing the highest Cf c peak
current cases for different values of 2N RCf c and fs . The
graphs are presented in Fig. 5 and it can be seen that the
normalized peak current is inversely proportional to 2N RCf c
and fs .
ΔiL =
D. Design Methodology
The design methodology used to perform the simulation
of the converter is presented in this section. From Fig. 5 it
can be noticed that for all the switching periods, in the worst
case, ist3
Cf c pk ≈ 1.25ILo when 2N RCf c ≈ 4Ts , which is an
acceptable peak current value for Cf c . Therefore, Cf c can be
defined by
(10)
2Ts
(13)
NR
Respecting the restriction 2N RCf c ≈ 4Ts , the proposed
converter operates with low peak values for the semiconductors and capacitors currents. Moreover, these peak values decrease slowly during the topological stages intervals.
Therefore, this converter operation can be seen as equivalent
to the Partial Charge (PC) or No Charge (NC) modes of a
conventional SC converter, defined in [17].
As explained in Section II-A, the capacitance Csm can be
defined by
st3
st3
where ΔVCf c , VCeq10
and VCeq30
are the Cf c voltage ripple,
the Ceq1 stage 3 initial voltage and the Ceq3 stage 3 initial
voltage.
√
Since Cf c ≥ 10Ceqx and the time constant 2π Lo Co tends
to be high regarding half the switching period, the Cf c voltage
can be approached as a trapezoidal waveform with period Ts ,
whereas the Lo current has a triangular waveform with period
N Cf c
(14)
10
Knowing the specification of Vo and ΔiLo , the design of
Lo and D can be done using the equations (12) and (8),
respectively.
Considering that all the ac component of iLo circulates
through the output capacitor and that this current has a
Cf c =
C. Flying Capacitor Peak Current Estimation
To ensure that the converter components operate with low
current peaks, an analysis of the capacitor Cf c initial current
during the topological stage 3 is done (the topological stage
1 can also be used), since this is the stage where the worst
current peak case occurs. Using KCL and KVL, the Cf c peak
current during stage 3 can be described by
ist3
Cf c
pk
=
st3
st3
− VCeq10
−ΔVCf c + VCeq30
2N R
Csm =
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500 Hz
1 kHz
2 kHz
5 kHz
10 kHz
25 kHz
50 kHz
ist3
Cf c
pk /ILo
102
500 Hz
101
100
50 kHz
10−5
10−4
10−3
10−2
10−1
2N RCf c
Fig. 5. Abacus relating ist3
Cf c
p=1
pk /ILo ,
2N RCf c and fs for D = 0.99 and
triangular waveform, the capacitance Co can be obtained
by calculating the area of the positive part of iCo , which
represents the total amount of charge received by Co , and
dividing it by Δvo , that is the desired output voltage ripple.
The resultant equation is given by
Co =
Vo (1 − D)Ts2
32Δvo Lo
(15)
III. S IMULATION R ESULTS
In order to verify the theoretical analysis and the design
methodology, a simulation of the converter is performed using
the software PSIM® . The specification of the converter is
shown in Table II as well as the values of the parameters
calculated using the equations specified in Section II-D. The
converter is operated in open-loop and with equal SM capacitances.
TABLE II
C ONVERTER S PECIFICATION
Parameter
Output power (Po )
Input voltage (Vin )
Output voltage (Vo )
Number of SMs per arm (N )
Semiconductors on-resistance (R)
Switching frequency (fs )
Duty cycle (D)
Output voltage ripple (ΔVo )
Inductor current ripple (ΔiLo )
Flying capacitor capacitance (Cf c )
SM capacitors capacitance (Csm )
Output capacitor capacitance (Co )
Inductor inductance (Lo )
Value
1666 W
1 kV
400 V
2
100 mΩ
10 kHz
0.803
1% of Vo
25% of ILo
1 mF
200 μF
1.63 μF
3.78 mH
The results of the simulation are shown in Fig. 6 and
Fig. 7. The average output voltage achieves 399.83 V with
4.06 V of voltage ripple, whereas the average inductor current
achieves 4.16 A with 1.05 A of current ripple. Compared to the
design specification, the voltage ripple differs −0.15 % and the
current ripple differs 0.48 %. This error is attributed to the ac
components with frequency 2fs present in both output voltage
and inductor current which modifies the average value.
The average voltage of the capacitors in the arms A1 and A2
are stabilized in 250.42 V each, whereas the average voltage of
capacitors in the arms A3 and A4 are in 294.57 V. It matches
with the values obtained from (7) (VCeq1 = VCeq2 = 500.83 V
and VCeq3 = VCeq4 = 499.15 V), since the simulated
arms average voltage are VCeq1 = VCeq2 = 500.85 V and
VCeq3 = VCeq4 = 499.17 V. It can be noticed that arms
voltage are automatically clamped by the flying capacitor,
avoiding the need of an ac power path to balance the voltage
of the upper and lower arms.
Analyzing the flying capacitor voltage it is noticeable
that it has a trapezoidal waveform as expected, since
Cf c = Csm /10N , with an average value of Vin /2. This average value must be controlled in a real converter to ensure that
it does not deviate from the correct value during the operation.
As regards the Cf c current, it can be seen that its peak is low
due to the chosen 2N RCf c . The peak value is 4.51 A, which
is about 12.5% the output current. Since D < 0.99 and p < 1,
it was expected that the peak value was lower than 25% of
ILo because the graphs from Fig. 5 consider the worst peak
current case.
As a matter of comparison, the converter was simulated with
2N RCf c = 4Ts /5 by making Cf c = 200 μF. Consequently,
Csm = 40 μF. Fig. 8 shows vo and iCf c for this case. The
average output voltage is 399.79 V and Cf c current peak value
is 6.37 A, which is 52.9 % higher than ILo . Since the output
current flows mostly through Cf c , its capacitance reduction
results in a neglegible increase of the semiconductors RMS
current. Consequently, the average output voltage remains
pratically unchanged. On the other hand, the higher current
peak values will increase the switching losses and the EMI,
jeopardizing the efficiency and the operation of the converter.
IV. C ONCLUSION
The Hybrid Switched Capacitor DC-DC Converter based
on MMC has been presented in this paper. Observing the
theoretical analysis developed, validated by simulation, the
proposed converter has a Buck-type output characteristic even
with the switched capacitor operation at the LC filter input.
This feature is interesting by the point-of-view that the equivalent output resistor is independent of the duty cycle, allowing
the converter to be designed with some freedom regarding the
voltage static gain. The 2fs frequency of the output current
ac component also helps to decrease the output inductance,
which tends to be high due to the Buck output characteristic. Moreover, the switched capacitor behavior provides self
arm voltage balancing, avoiding the need of inductor at the
converter input.
The capacitance of the flying capacitor needs to be carefully designed to avoid high peak and RMS currents on the
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vo
4.0
0.0
−5.0
3.5
vcm1,3
404
402
400
398
396
5.0
4.5
iCf c
vo
iLo
404
402
400
398
396
250.43
Time (100 μs/div)
250.42
Fig. 8. Output voltage (vo ) and flying capacitor current (iCf c ) with
2N RCf c = 4Ts /5.
250.41
vcm5,7
249.59
249.58
249.57
Time (100 μs/div)
Fig. 6. Output voltage (vo ), inductor current (iLo ), A1 and A2 SM capacitors
voltages (vcm1,3 ), A3 and A4 SM capacitors voltages (vcm5,7 )
vf c
500.1
500.0
499.9
iCf c
5.0
0.0
−5.0
Time (100 μs/div)
Fig. 7. Flying capacitor voltage (vCf c ) and current (iCf c ).
semiconductors and capacitors. It can cause this capacitance
to reach high values depending on the switching frequency,
the number of SMs and the semiconductors on-resistance.
Experimental results were not presented in this paper because the converter is still under investigation. The research
is being conducted towards a prototype construction of the
bidirectional converter version to validate experimentally the
theoretical analysis. However, the simulation software used has
shown to be a reliable tool to understand and design hybrid
switched capacitor converters.
For limited space reasons, further details regarding the
topological stages, the losses analysis and the issues related to
capacitors and semiconductors technologies will be addressed
in future papers.
R EFERENCES
[1] S. Kenzelmann, A. Rufer, D. Dujic, F. Canales, and Y. R. de Novaes,
“Isolated dc/dc structure based on modular multilevel converter,” IEEE
Transactions on Power Electronics, vol. 30, no. 1, pp. 89–98, Jan 2015.
[2] S. Milovanović and D. Dujić, “High-power dc–dc converter utilising
scott transformer connection,” IET Electric Power Applications,
April 2019. [Online]. Available: https://digital-library.theiet.org/content/
journals/10.1049/iet-epa.2018.5746
[3] A. Schön and M.-M. Bakran, “A new hvdc-dc converter for the efficient
connection of hvdc networks,” in PCIM Europe 2013 : International
Exhibition & Conference for Power Electronics, Intelligent Motion,
Renewable Energy and Energy Management. Nürnberg: VDE Verlag
GmbH, 2013, pp. 525–532.
[4] I. A. Gowaid, G. P. Adam, B. W. Williams, A. M. Massoud, and
S. Ahmed, “A dc autotransformer design for medium and high voltage
dc transmission systems,” in 2018 IEEE 12th International Conference
on Compatibility, Power Electronics and Power Engineering (CPEPOWERENG 2018), April 2018, pp. 1–6.
[5] S. Du, B. Wu, K. Tian, D. Xu, and N. R. Zargari, “A novel mediumvoltage modular multilevel dc-dc converter,” IEEE Transactions on
Industrial Electronics, vol. 63, no. 12, pp. 7939–7949, Dec 2016.
[6] S. Du and B. Wu, “A transformerless bipolar modular multilevel dcdc converter with wide voltage ratios,” IEEE Transactions on Power
Electronics, vol. 32, no. 11, pp. 8312–8321, Nov 2017.
[7] S. Du, B. Wu, and N. R. Zargari, “A transformerless high-voltage dcdc converter for dc grid interconnection,” IEEE Transactions on Power
Delivery, vol. 33, no. 1, pp. 282–290, Feb 2018.
[8] S. H. Kung and G. J. Kish, “A modular multilevel hvdc buck-boost converter derived from its switched-mode counterpart,” IEEE Transactions
on Power Delivery, vol. 33, no. 1, pp. 82–92, Feb 2018.
[9] G. J. Kish, M. Ranjram, and P. W. Lehn, “A modular multilevel dc/dc
converter with fault blocking capability for hvdc interconnects,” IEEE
Transactions on Power Electronics, vol. 30, no. 1, pp. 148–162, Jan
2015.
[10] H. You and X. Cai, “A three-level modular dc/dc converter applied in
high voltage dc grid,” IEEE Access, vol. 6, pp. 25 448–25 462, 2018.
[11] ——, “Stepped 2-level operation of non-isolated modular dc/dc converter applied in high voltage dc grid,” IEEE Journal of Emerging and
Selected Topics in Power Electronics, vol. PP, no. 99, pp. 1–1, 2017.
[12] R. L. da Silva, T. B. Lazzarin, and I. Barbi, “Reduced switch count stepup/step-down switched-capacitor three-phase ac–ac converter,” IEEE
Transactions on Industrial Electronics, vol. 65, no. 11, pp. 8422–8432,
Nov 2018.
[13] T. B. Lazzarin, R. L. Andersen, and I. Barbi, “A switched-capacitor
three-phase ac–ac converter,” IEEE Transactions on Industrial Electronics, vol. 62, no. 2, pp. 735–745, Feb 2015.
[14] R. L. Andersen, T. B. Lazzarin, and I. Barbi, “A 1-kw step-up/stepdown switched-capacitor ac–ac converter,” IEEE Transactions on Power
Electronics, vol. 28, no. 7, pp. 3329–3340, July 2013.
[15] M. D. Vecchia, M. A. Salvador, and T. B. Lazzarin, “Hybrid nonisolated
dc–dc converters derived from a passive switched-capacitor cell,” IEEE
Transactions on Power Electronics, vol. 33, no. 4, pp. 3157–3168, April
2018.
[16] I. A. Gowaid, G. P. Adam, A. M. Massoud, S. Ahmed, D. Holliday,
and B. W. Williams, “Quasi two-level operation of modular multilevel
converter for use in a high-power dc transformer with dc fault isolation
capability,” IEEE Transactions on Power Electronics, vol. 30, no. 1, pp.
108–123, Jan 2015.
[17] S. Ben-Yaakov and M. Evzelman, “Generic average modeling and
simulation of the static and dynamic behavior of switched capacitor
converters,” in 2012 Twenty-Seventh Annual IEEE Applied Power Electronics Conference and Exposition (APEC), Feb 2012, pp. 2568–2575.
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