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Design and Implementation of CDR and SerDes for High Speed
Optical Communication Networks Using FPGA
Kareem Ismail1, Tawfik Ismail2, and Hassan Mostafa1
Department of Electronics and Communications Engineering, Cairo University
2
Department of Engineering Applications of Laser, National Institute of Laser Enhanced Science,
Cairo University
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ABSTRACT
In this paper, we design and implement the Clock and Data-Recovery (CDR) with Serializer/Deserializer
(SerDes) on Spartan SP605 supports a data-rate up-to 3.2 Gbps with locking time less-than 5×10-7 s, and biterror rate less-than 10−10.
1. INTRODUCTION
A Clock and Data Recovery (CDR) is one of the most critical functions in the high-speed communication
systems [1]. The CDR circuit senses the data transitions and generates the recovered clock. Furthermore, it retimes the received data to remove the accumulated jitter during transmission. A SerDes (Serializer/Deserializer)
is de-multiplexing the single using the division multiplexing for parallel processing, and then it is remultiplexing the signal again in one line. This function is used to convert the high-speed processing into lowspeed processing, which reduces the cost of the overall system while achieves an acceptable performance for the
data receiving.
In this paper, a complete digital CDR is designed, implemented and evaluated on Spartan SP605 FPGA with
SerDes circuits to support a high-speed data rate. The proposed is designed by using two main components,
a phase-detector which senses the phase difference, and a phase-selection which picks out the phase of the
recovered clock. The implemented SerDes is based on Xilinx Source-Synchronous Serialization and
Deserialization Application Note [2] which used the ISERDES/OSERDES primitives and the BUFIO2 for clock
reception and synchronization.
2. PROPOSED CDR/SERDES ARCHITECTURE
2.1 CDR Design
The proposed CDR architecture consists of four parts, phase detector, control unit, multi-phase generation and
selection, and retiming circuit as shown in Fig. 1.
Figure 1. The proposed CDR architecture.
The phase detector (PD) is providing two essential functions: data transition detection and phase difference
detection. It uses two D-FF’s to sample the incoming data in different time slots, and then performing XOR
operations on their outputs. The width of the XOR output signal represents the phase difference between the
incoming data stream sampling clock and the recovered clock. This technique achieves high speed and low
power dissipation at the same time, also it is minimizing the ripples on the phase selection stage [3].
The control unit consists of a control logic module and an UP-Down counter. The control logic converts the
input UP and DOWN signals to output increment, decrement, and memory signals. If UP and DOWN signals
have high-amplitude simultaneously they fed-in, else the increment or the decrement signal is raised and the
memory signal raises. If only one of them is high, this prompts the control logic unit to generate the
978-1-5090-1467-5/16/$31.00 ©2016 IEEE
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corresponding output. The Up-Down Counter takes the output of the counter from an internal memory block and
updates its output according to the incoming controls. The difference between each two successive phases is
defined by the minimum increment of (1UI/N) [4]. The selection unit consists of Nx1 multiplexer and its
selection lines are connected to the Up-Down counter output. It is used to pick-out the matching phase with the
incoming data.
Finally, the data is retimed by using the retiming circuit with consists of one delay-unit and two D-FF. One
operating on the rising edge of the in-phase clock and the other operating on the falling edge of the in-phase
clock. As the data is retimed, the BER of a CDR circuit is actually related to the jitter.
2.2 SerDes Design
In SerDes design, each input/output bank of the Spartan-6 FPGA can function as deserializer or serializer by
using the primitive ISERDES/OSERDES. The Spartan-6 can achieve higher conversion rates, when it uses
differential inputs/outputs by cascading ISERDESs/OSERDEs. As a result, the splitting ratio can be increased to
8 times [5].
In deserializer process, the incoming data stream is received by using a BUFIO2 primitive to drive the inputs
in the half edge of the input clock. Furthermore, the BUFIO2 is used for dividing down the input clock to lower
components which are used for the processing of the deserialized data as shown in Fig. 2. The possible ratio that
can be achieved using this method is 1:8. For example, let the received input data is 3.2 GHz, and the deserialzed
parameter of BUFIO2 primitives to 8. The lower clock will be 400 MHz, which is suitable to be processed by
Spartan-6 FPGA due to its maximum internal operating frequency limitation.
In serializer process, The low rate components of the internally processed data is multiplexed into one
differential serial output with a rate of the Nxf where ‘N’ is the division ratio and ‘f’ is the internal processing
frequency. The incoming local receiver source clock is connected to two BUFIO2s, which can be used to
generate a doubled clock inside the output SerDes associated with the forwarded clock(2 transitions per 1 data
bit), whereas the output SerDes associated with the output data lines uses the undoubled clock as shown in
Fig. 3. A division ration of up to 8:1 can be handled using this topology.
Figure 2. Data reception using BUFIO2.
Figure 3. Data transmission using 2 BUFIO2s.
3. SIMULATION AND IMPLEMENTATION RESULTS
The RTL of the CDR block diagram which is extracted from ISE is shown in Fig. 4. This RTL is implemented
based on phase shift feature of the built-in clock manager (DCM) inside the FPGA. It is used to generate
multiple phases of the reference clock. The clock manager is able to generate up to 6 phases either the reference
phase. Figure 5 represents the simulation results of the proposed CDR. The timing report of the ISE14.7 states
that the minimum period: 2.331ns (Maximum Frequency: 429.092MHz) on Spartan 6 FPGAs.
Figure 6 shows the RTL block diagram of the SerDes interface with 4 CDRs. This design is able to achieve
up to around 1.7GHz Input/Output processing frequencies with 420MHz CDRs internal frequency. The
simulation result in Fig. 7 is the ISERDES, 4 CDRs and OSERDES topology with input data rate of 1.2 Gb/s and
27 MHz reference clock input to the DCM which generates the 6 300MHz phase shifted components required by
the phase detector. As seen in Fig.7, the recovered data from the OSERDES is delayed by 15ns from the input
data of the ISERDES. There is a major challenge here, each CDR's DCM requires 7 BUFGs (one input source
clock and 6 for the phase shifted outputs) and the Spartan605 with a XC6SLX45T Family FPGA on board has
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only 18 BUFGs. This expected to be overridden in the future work by using multiple FPGAs or by using a
higher FPGA family (like Vertex-7).
Figure 8 shows the input and the recovered clock after synthesizing on the SP605 kit captured by Tektronix
TLA5201 Logic Analyzer. For the sake of realization of this experiment, the input data need to be varied with
the phase of its clock. So that, an external control on SP605 kit (dip switches) is linked to the phase of the input
data's reference clock. This process ensures that the data varies in phases to test the performance of the CDR
among all possible phase shifts that happens on a real data transmission system.
Figure 4. CDR RTL block diagram.
Figure 6. 1:4/4:1 SERDESs with 4 CDRs RTL block
DIAGRAM.
Figure 5. CDR behavioral simulation results.
Figure 7. 1:4/4:1 SERDESs with 4 CDRs results.
Figure 8. Input and recovered clocks on Tektronix logic analyzer.
4. CONCLUSIONS
The proposed CDR with SerDes architecture have been designed and implemented using a Matlab/Simulink and
ISE14.7 on Xilinx SP605 Evaluation Kit, respectively. In this work, we are succeed to reach up to 3.2Gbps using
8 parallel CDRs. The future work includes implementing the proposed CDR with SerDes over Vertix-7 FPGA
with 32 channels and 700MHz speed. This work can be used for high speed optical access network with 22Gbps
transmission rate.
REFERENCES
[1] I. Haller: High-speed clock recovery for low-cost FPGAs, Design, Automation Test in Europe Conference
Exhibition (DATE), Mar. 2010.
[2] N. Sawyer: Source-synchronous serialization and deserialization (up to 1050 Mb/s), Xilinx Application
Note: Spartan-6 FPGAs.
[3] B. Razavi: Design of Integrated Circuits for Optical Communication, McGraw-Hill, 1st. Ed, 2003.
[4] S. I. Ahmed: An all-digital data recovery circuit optimization using matlab-simulink, Circuits and Systems,
ISCAS 2005.
[5] Xilinx: Spartan-6 FPGA SelectIO Resources, User Guide UG381 (v1.6), Feb. 14, 2014.
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