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CMOS DESIGN -ECL312
PROJECT REPORT
Submitted to
IIIT NAGPUR
Under the Guidance of
DR. PARITOSH PESHWE
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DEPARTMENT OF
ELECTRONICS AND COMMUNICATION ENGINEERING
IIIT NAGPUR
SUBMITTED BY
B. VARUN RAO (BT19ECE061)
CONTENTS
Objective
Introduction
Software tools
Circuit Diagram
Procedure
Netlist
Netlist output
Cmos layout
Output
OBJECTIVE
We have to design the cmos layout for Binary to BCD
converter and also Write the netlist and Verify it using
ngspice.
INTRODUCTION :
BCD is a binary coded decimal number, where each digit of a
decimal number is respected by its equivalent binary number.
That means, LSB of a decimal number is represented by its
equivalent binary number and similarly other higher
significant bits of decimal number are also represented by
their equivalent binary numbers.
TRUTH TABLE :
The input is a 4-bit binary code (A B C D) so 16(2^4)
combinations are possible. Hence the output should have
8-bit, but first three bits will all be a 0 for all combinations of
inputs, the output can be treated as 5-bit BCD code (W X Y Z
E) .
SOFTWARES USED :
Ngspice,Microwind
CIRCUIT DIAGRAM :
CIRCUIT DIAGRAM BY CMOS TECHNOLOGY :
NETLIST:**Binary to BCD converter
.subckt inverter 1 2 3
.model pmod pmos Vto=-1V Kp=80u
.model nmod nmos Vto=1V Kp=200u
mp 2 1 3 3 pmod w=100u l=1u
mn 2 1 0 0 nmod w=40u l=1u
.ends
Vdd 23 0 dc 5V
Va 1 0 pulse(0 5 0 0 0 5ns 10ns)
Vb 2 0 pulse(0 5 0 0 0 10ns 20ns)
Vc 3 0 pulse(0 5 0 0 0 20ns 40ns)
xBbar 2 19 23 inverter
xCbar 3 20 23 inverter
XDbar 1 21 23 inverter
.model pmod pmos Vto=-1V Kp=80u
.model nmod nmos Vto=1V Kp=200u
mA 5 0 23 23 pmod w=100u l=1u
mB 13 0 23 23 pmod w=100u l=1u
mC 17 0 23 23 pmod w=100u l=1u
mD 10 0 23 23 pmod w=100u l=1u
m1 5 1 4 0 nmod w=40u l=1u
m2 4 2 0 0 nmod w=40u l=1u
m3 4 3 0 0 nmod w=40u l=1u
m4 13 1 12 0 nmod w=40u l=1u
m5 12 19 11 0 nmod w=40u l=1u
m6 11 20 0 0 nmod w=40u l=1u
m7 16 21 0 0 nmod w=40u l=1u
m8 16 3 0 0 nmod w=40u l=1u
m9 17 2 16 0 pmod w=40u l=1u
m10 10 1 8 0 nmod w=40u l=1u
m11 8 2 7 0 nmod w=40u l=1u
m12 7 20 0 0 nmod w=40u l=1u
m13 9 3 0 0 nmod w=40u l=1u
m14 10 21 9 0 nmod w=40u l=1u
xw 5 6 23 inverter
xx 13 15 23 inverter
xy 17 18 23 inverter
xz 10 14 23 inverter
.tran 0.1ns 100ns
.control
run
plot V(1)
plot V(2)
plot V(3)
plot V(6)
plot V(15)
plot V(18)
plot V(14)
.endc
.end
NGSPICE OUTPUT:-
CMOS LAYOUT :
OUTPUT :
CONCLUSION :
I have successfully completed the circuit design and verified it
in ngspice and also designed the layout for it in microwind.