Solutions Manual to Accompany
FUNDAMETALS OF
SEMICONDUCTOR
FABRICATION
G. S. May
Motorola Foundation Professor
School of Electrical & Computer Engineering
Georgia Institute of Technology
Atlanta, GA, USA
S. M. SZE
UMC Chair Professor
National Chiao Tung University
National Nano Device Laboratories
Hsinchu, Taiwan
1
John Wiley and Sons, Inc
New York. Chicester / Weinheim / Brisband / Singapore / Toronto
2
Contents
Ch.1 Introduction ----------------------------------------------------------------------------- N/A
Ch.2 Crystal Growth ------------------------------------------------------------------------ 1
Ch.3 Silicon Oxidation ---------------------------------------------------------------------- 8
Ch.4 Photolithography------------------------------------------------------------------------12
Ch.5 Etching -----------------------------------------------------------------------------------15
Ch.6 Diffusion ---------------------------------------------------------------------------------18
Ch.7 Ion Implantation ------------------------------------------------------------------------26
Ch.8 Film Deposition -------------------------------------------------------------------------32
Ch.9 Process Integration ---------------------------------------------------------------------40
Ch.10 IC Manufacturing----------------------------------------------------------------------65
Ch.11 Future Trends and Challenges--------------------------------------------------------78
0
CHAPTER 2
1. C0 = 1017 cm-3
k0(As in Si) = 0.3
CS= k0C0(1 - M/M0)k0-1
= 0.3×1017(1- x)-0.7 = 3×1016/(1 - l/50)0.7
0
0.2
0.4
0.6
0.8
0.9
l (cm)
0
10
20
30
40
45
CS (cm-3)
3×1016
3.5×1016
4.28×1016
5.68×1016
1.07×1017
1.5×1017
0
20
40
ND (10
16
-3
cm )
x
16
14
12
10
8
6
4
2
0
10
30
50
l ( cm)
2. (a) The radius of a silicon atom can be expressed as
3
a
8
r=
so r =
3
× 5.43 = 1.175Å
8
(b) The numbers of Si atom in its diamond structure are 8.
So the density of silicon atoms is
n=
8
8
=
= 5.0 × 10 22 atoms/cm 3
3
3
a
(5.43Å)
(c) The density of Si is
ρ =
M / 6.02 × 10 23
1/ n
=
28.09 × 5 × 10 22
6.02 × 10
23
1
g / cm 3 = 2.33 g / cm3.
3. k0 = 0.8 for boron in silicon
M / M0 = 0.5
The density of Si is 2.33 g / cm3.
The acceptor concentration for ρ = 0.01 Ω–cm is 9×1018 cm-3.
The doping concentration CS is given by
C s = k 0 C 0 (1 −
M k0 −1
)
M0
Therefore
C0 =
Cs
9 × 1018
=
M k 0 −1 0.8(1 − 0.5) − 0.2
)
k 0 (1 −
M0
= 9.8 × 1018 cm − 3
The amount of boron required for a 10 kg charge is
10,000
× 9.8 × 1018 = 4.2 × 10 22 boron atoms
2.338
So that
10.8g/mole ×
4.2 × 10 22 atoms
= 0.75g boron .
6.02 × 10 23 atoms/mole
4. (a) The molecular weight of boron is 10.81.
The boron concentration can be given as
number of boron atoms
volume of silicon wafer
5.41 × 10 −3 g / 10.81g × 6.02 × 10 23
=
10.0 2 × 3.14 × 0.1
= 9.78 × 1018 atoms/cm 3
nb =
(b) The average occupied volume of everyone boron atoms in the wafer is
2
V =
1
1
=
cm 3
18
nb 9.78 × 10
We assume the volume is a sphere, so the radius of the sphere ( r ) is the
average distance between two boron atoms. Then
r=
3V
= 2.9 × 10 −7 cm .
4π
5. The cross-sectional area of the seed is
2
 0.55 
2
π
 = 0.24 cm
 2 
The maximum weight that can be supported by the seed equals the product of the
critical yield strength and the seed’s cross-sectional area:
(2 × 10 6 ) × 0.24 = 4.8 × 10 5 g = 480 kg
The corresponding weight of a 200-mm-diameter ingot with length l is
2
 20.0 
( 2.33g/cm )π 
 l = 480000 g
 2 
∴ l = 656 cm = 6.56 m.
3
6. We have
k0 −1
 M
Cs / C0 = k0 1− 
 M0 
Fractional 0
solidified
Cs /C0
0.05
0.2
0.4
0.06
0.6 0.8 1.0
0.08
3
0.12
0.23
∞
Cs/Co
0.21
0.11
0.01
0
0.2
0.4
0.6
0.8
1
Fraction Solidified
7. The segregation coefficient of boron in silicon is 0.72. It is smaller than unity, so the solubility of B in
Si under solid phase is smaller than that of the melt. Therefore, the excess B atoms will be thrown-off
into the melt, then the concentration of B in the melt will be increased. The tail-end of the crystal is the
last to solidify. Therefore, the concentration of B in the tail-end of grown crystal will be higher than
that of seed-end.
8. The reason is that the solubility in the melt is proportional to the temperature, and the temperature is
higher in the center part than at the perimeter. Therefore, the solubility is higher in the center part,
causing a higher impurity concentration there.
9. The segregation coefficient of Ga in Si is 8 ×10-3
From Eq. 18
C s / C 0 = 1 − (1 − k )e − kx / L
We have
x=
L  1− k
ln
k  1 − C s / C 0




2
1 − 8 × 10 − 3

ln
8 × 10 -3  1 − 5 × 1015 / 5 × 1016
= 250 ln(1.102)
=
= 24 cm.
10. We have from Eq.18
Cs = C0[1 − (1 − ke ) exp(−ke x / L)]
4



So the ratio Cs / C0 = [1 − (1 − ke ) exp(−ke x / L)]
= 1 − (1 − 0.3) • exp(−0.3 × 1) = 0.52
= 0.38
at x / L = 1
at x/L = 2.
11. For the conventionally-doped silicon, the resistivity varies from 120 Ω-cm to 155 Ω-cm. The
corresponding doping concentration varies from 2.5×1013 to 4×1013 cm-3. Therefore the range of
breakdown voltages of p+ - n junctions is given by
VB ≅
=
ε s Ec 2
2q
( N B ) −1
1.05 × 10 −12 × (3 × 10 5 ) 2
( N B ) −1 = 2.9 × 1017 / N B = 7250 to 11600 V
−19
2 × 1.6 × 10
∆V B = 11600 − 7250 = 4350 V
 ∆V 
∴  B  / 7250 = ±30%
 2 
For the neutron irradiated silicon, ρ = 148 ± 1.5 Ω-cm. The doping concentration is 3×1013 (±1%).
The range of breakdown voltage is
V B = 1.3 × 10 17 / N B = 2.9 × 10 17 / 3 × 10 13 ( ±1%)
= 9570 to 9762 V .
∆V B = 9762 − 9570 = 192 V
 ∆V
∴ B
 2

 / 9570 = ±1% .

12. We have
M s weight of GaAs at Tb C m − C l s
=
=
=
M l weight of liquid at Tb C s − C m l
Therefore, the fraction of liquid remained f can be obtained as following
5
f =
Ml
l
30
=
≈
= 0.65 .
M s + M l s + l 16 + 30
13. From the Fig.2.11, we find the vapor pressure of As is much higher than that of the Ga. Therefore,
the As content will be lost when the temperature is increased. Thus the composition of liquid GaAs
always becomes gallium rich.
 − 88.8 

 (T / 300) 
14. n s = N exp(− E s / kT ) = 5 × 10 22 exp(2.3 eV / kT ) = 5 × 10 22 exp 
= 1.23 × 10 −16 cm −3 ≈ 0 at 27 0 C = 300 K
= 6.7 × 1012 cm −3
at 900 0 C = 1173 K
= 6.7 × 1014 cm −3
at 1200 0 C = 1473 K .
15. n f = NN ` exp(− E f / 2kT )
= 5 × 10 22 × 1 × 10 27 e −3.8eV / kT × e −1.1eV / 2 kT = 7.07 × 10 24 × e −94.7 /(T / 300 )
= 5.27 × 10 −17 at 27oC = 300 K
=2.14×1014 at 900oC = 1173 K.
16. 37 × 4 = 148 chips
In terms of litho-stepper considerations, there are 500 µm space tolerance between the mask
boundary of two dice. We divide the wafer into four symmetrical parts for convenient dicing,
and discard the perimeter parts of the wafer. Usually the quality of the perimeter parts is the worst
due to the edge effects.
6
7
CHAPTER 3
1. From Eq. 11 (with τ=0)
x2+Ax = Bt
From Figs. 3.6 and 3.7, we obtain B/A =1.5 µm /hr, B=0.47 µm 2/hr, therefore A= 0.31 µm. The
time required to grow 0.45µm oxide is
t=
1 2
1
(x + Ax) =
(0.45 2 + 0.31 × 0.45) = 0.72 hr = 44 min .
B
0.47
2. After a window is opened in the oxide for a second oxidation, the rate constants are
B = 0.01 µm 2/hr, A= 0.116 µm (B/A = 6 ×10-2 µm /hr).
If the initial oxide thickness is 20 nm = 0.02 µm for dry oxidation, the value ofτcan be obtained
as followed:
(0.02)2 + 0.166(0.02) = 0.01 (0 +τ)
or
τ= 0.372 hr.
For an oxidation time of 20 min (=1/3 hr), the oxide thickness in the window area is
x2+ 0.166x = 0.01(0.333+0.372) = 0.007
or
x = 0.0350 µm = 35 nm (gate oxide).
For the field oxide with an original thickness 0.45 µm, the effectiveτis given by
τ=
1 2
1
(0.45 2 + 0.166 × 0.45) = 27.72 hr.
( x + Ax) =
B
0.01
x2+ 0.166x = 0.01(0.333+27.72) = 0.28053
or x = 0.4530 µm (an increase of 0.003µm only for the field oxide).
3.
x2 + Ax = B (t + τ )
(x +
A 2 A2
) −
= B (t + τ )
2
4
(x +
 A2

A 2
) =B
+ (t + τ )
2
 4B

8
when t >> τ , t >>
A2
,
4B
then, x2 = Bt
similarly,
when t >> τ , t >>
then, x =
A2
,
4B
B
(t + τ )
A
4. At 980℃(=1253K) and 1 atm, B = 8.5×10-3 µm 2/hr, B/A = 4×10-2 µm /hr (from Figs. 3.6 and 3.7).
Since A ≡2D/k , B/A = kC0/C1, C0 = 5.2×1016 molecules/cm3 and C1 = 2.2×1022 cm-3 , the diffusion
coefficient is given by
D=
Ak A  B C1
=  ⋅
2
2  A C0
 B  C1 
 = 

 2  C0 
8.5 × 10 −3 2.2 × 10 22
µm 2 / hr
2
5.2 × 1016
= 1.79 × 10 3 µm 2 / hr
=
= 4.79 × 10 -9 cm 2 / s.
5. For impurity in the oxidation process of silicon,
segregation coefficeint =
6.
κ=
equilibrium concentration of impurity in silicon
.
equilibrium concentration of impurity in SiO 2
3 × 1011
3
=
= 0.006 .
13
500
5 × 10
7. The SUPREM input file for the first oxidation step is:
TITLE
Problem 3-7a
COMMENT
Initialize silicon substrate
INITIALIZE
<100> Silicon
COMMENT
Oxidize the wafer for 60 minutes at 1100 C in dry O2
DIFFUSION
Time=60 Temperature=1100 DryO2
PRINT
Layers
STOP
End Problem 3-7a
The result of the PRINT Layers command is:
9
layer
material type
(microns)
2
1
(microns)
thickness
dxmin
top
bottom no.
0.1088 0.0100 0.0010
1.9521 0.0100 0.0010
798
805
804
1000
node
OXIDE
SILICON
dx
node
This indicates an oxide thickness of 0.1088 µm, which means 0.44 * 0.1088 µm = 0.0479 µm of
silicon has been consumed during the process (i.e., the Si/SiO2 interface is 0.0479 µm below the
original Si surface). The figure below is a graphical representation.
For the half of the wafer, the oxide is removed, and the wafer is re-oxidized in wet O2. For this half,
we use the following SUPREM input file:
TITLE
Problem 3-7b
COMMENT
Initialize silicon substrate
INITIALIZE
<100> Silicon
COMMENT
Oxidize the wafer for 60 minutes at 1100 C in dry O2
DIFFUSION
Time=60 Temperature=1100 DryO2
COMMENT
Remove the oxide
ETCH
Oxide All
COMMENT
Oxidize the wafer for 30 minutes at 1000 C in wet O2
DIFFUSION Time=30 Temperature=1000 WetO2
PRINT
Layers
STOP
End Problem 3-7b
The result of this PRINT Layers command is:
layer
no.
material type
thickness
(microns)
dx
dxmin top bottom
(microns)
node node
2
OXIDE
0.2291 0.0100 0.0010
803
814
1
SILICON
1.8513 0.0100 0.0010
815
1000
This indicates a final oxide thickness of 0.2291 µm on the etched side, which means an additional 0.44
10
* 0.2291 µm = 0.1008 µm of silicon has been consumed during the process. The total distance from
the Si/SiO2 interface to the original Si surface on this side is therefore 0.0479 µm + 0.1008 µm =
0.1487 µm.
The unetched side is simulated using the SUPREM input file:
TITLE
Problem 3-7c
COMMENT
Initialize silicon substrate
INITIALIZE
<100> Silicon
COMMENT
Oxidize the wafer for 60 minutes at 1100 C in dry O2
DIFFUSION
Time=60 Temperature=1100 DryO2
COMMENT
Oxidize the wafer for 30 minutes at 1000 C in wet O2
DIFFUSION Time=30 Temperature=1000 WetO2
PRINT
Layers
STOP
End Problem 3-7c
The result of this PRINT Layers command is:
layer
no.
2
1
material type
OXIDE
SILICON
thickness
(microns)
dx
dxmin top bottom
(microns)
node node
0.2897 0.0100 0.0010
1.8725 0.0100 0.0010
798
813
812
1000
On this side, a total of 0.44 * 0.2897 µm = 0.1275 µm of Si is consumed. The total distance from the
Si/SiO2 interface to the original Si surface on this side is 0.44 * 0.2987 µm = 0.1275 µm. The figure
below is a graphical representation of the final structure.
11
The step heights on the surface and in the substrate are 0.0818 µm and 0.0212 µm, respectively.
12
CHAPTER 4
1. With reference to Fig. 2 for class 100 clean room we have a total of 3500 particles/m3 with
particle sizes ≥ 0.5 µm
21
× 3500 = 735 particles/m2 with particle sizes ≥ 1.0 µm
100
4.5
× 3500 = 157 particles/m2 with particle sizes ≥ 2.0 µm
100
Therefore, (a) 3500-735 = 2765 particles/m3 between 0.5 and 1 µm
(b) 735-157 = 578 particles/m3 between 1 and 2 µm
(c)
157 particles/m3 above 2 µm.
2.
9
Y = Π e − D1 A
n =1
A = 50 mm2 = 0.5 cm2
Y = e −4( 0.1×0.5) × e −4 ( 0.25×0.5) × e −1(1×0.5) = e −1.2 = 30.1% .
3. The available exposure energy in an hour is
0.3 mW2/cm2 × 3600 s =1080 mJ/cm2
For positive resist, the throughput is
1080
= 7 wafers/hr
140
For negative resist, the throughput is
1080
= 120 wafers/hr .
9
4. (a) The resolution of a projection system is given by
l m = k1
λ
NA
DOF = k 2
(b)
= 0 .6 ×
0.193μm
= 0.178 µm
0.65
λ
 0.193µm 
= 0.228 µm
= 0 .5 
2 
( NA)
 (0.65) 
2
We can increase NA to improve the resolution. We can adopt resolution enhancement
techniques (RET) such as optical proximity correction (OPC) and phase-shifting Masks
(PSM). We can also develop new resists that provide lower k1 and higher k2 for better
13
resolution and depth of focus.
(c) PSM technique changes k1 to improve resolution.
5. (a) Using resists with high γ value can result in a more vertical profile but throughput decreases.
(b) Conventional resists can not be used in deep UV lithography process because these resists
have high absorption and require high dose to be exposed in deep UV. This raises the
concern of damage to stepper lens, lower exposure speed and reduced throughput.
6. (a)
A shaped beam system enables the size and shape of the beam to be varied, thereby
minimizing the number of flashes required for exposing a given area to be patterned.
Therefore, a shaped beam can save time and increase throughput compared to a Gaussian
beam.
(b)
We can make alignment marks on wafers using e-beam and etch the exposed marks. We can
then use them to do alignment with e-beam radiation and obtain the signal from these marks
for wafer alignment.
X-ray lithography is a proximity printing lithography. Its accuracy requirement is very high,
therefore alignment is difficult.
(c) X-ray lithography using synchrotron radiation has a high exposure flux so X-ray has better
throughput than e-beam.
7. (a) To avoid the mask damage problem associated with shadow printing, projection printing
exposure tools have been developed to project an image from the mask. With a 1:1
projection printing system is much more difficult to produce defect-free masks than it is with
a 5:1 reduction step-and-repeat system.
(b) It is not possible. The main reason is that X-rays cannot be focused by an optical lens. When
it is through the reticle. So we can not build a step-and-scan X-ray lithography system.
8. All of the above values can be entered from the Parameters menu or by clicking on the appropriate
14
icon on the toolbar. The resulting resist profile is shown in the figure below.
In comparison to Example 3, we see that no resist feature is printed under the modified process
conditions. The combination of the long pre-bake time and low exposure dose prevents the feature
from being defined.
15
CHAPTER 5
1.
As shown in the figure, the profile for each case is a segment of a circle with origin at the
initial mask-film edge. As overetching proceeds the radius of curvature increases so that the
profile tends to a vertical line.
2.
(a) 20 sec
0.6 × 20/60 = 0.2 µm…..(100) plane
0.6/16 × 20/60 = 0.0125 µm……..(110) plane
0.6/100 × 20/60 = 0.002 µm…….(111) plane
Wb = W0 − 2l = 1.5 − 2 × 0.2 = 1.22 µm
(b) 40 sec
0.6 × 40/60 = 0.4 µm….(100)plane
0.6/16 × 40/60 = 0.025 µm…. (110) plane
0.6/100 × 40/60 = 0.004 µm…..(111) plane
Wb = W0 − 2l = 1.5 − 2 × 0.4 = 0.93 µm
(c)
60 sec
0.6 ×1 = 0.6 µm….(100)plane
0.6/16 ×1 = 0.0375 µm…. (110) plane
0.6/100 ×1= 0.006 µm…..(111) plane
Wb = W0 − 2l = 1.5 − 2 × 0.6 = 0.65 µm.
3.
Using the data in Prob. 2, the etched pattern profiles on <100>-Si are shown in below.
(a) 20 sec
l = 0.012 µm, W0 = Wb = 1.5 µm
16
(b) 40 sec
l = 0.025 µm, W0 = Wb = 1.5 µm
(c) 60 sec l = 0.0375 µm W0 = Wb = 1.5 µm.
4. If we protect the IC chip areas (e.g. with Si3N4 layer) and etch the wafer from the top, the
width of the bottom surface is
W = W1 + 2l = 1000 + 2 × 625 = 1884 µm
The fraction of surface area that is lost is
(W 2 − W12 ) / W 2 × 100%=(18842-10002) /18842× 100% = 71.8 %
In terms of the wafer area, we have lost
71.8 % × π (15 / 2) 2 =127 cm2
Another method is to define masking areas on the backside and etch from the back. The width of
each square mask centered with respect of IC chip is given by
W = W1 − 2l = 1000 − 2 × 625 = 116 µm
Using this method, the fraction of the top surface area that is lost can be negligibly small.
5. 1 Pa = 7.52 m Torr
PV = nRT
7.52 /760 × 10-3 = n/V ×0.082 × 273
n/V = 4.42 × 10-7 mole/liter = 4.42 × 10-7 × 6.02 × 1023/1000 =2.7 ×1014 cm-3
mean–free–path
λ = 5 × 10 −3 / P cm = 5× 10-3 ×1000/ 7.52 = 0.6649 cm = 6649 µm
150Pa = 1128 m Torr
PV = nRT
17
1128/ 760 × 10-3 = n/V × 0.082 × 273
n/V = 6.63 × 10-5 mole/liter = 6.63 ×10-5×6.02×1023/1000 = 4 × 1016 cm-3
mean-free-path
λ = 5 × 10 −3 / P cm = 5× 10-3 ×1000/1128 = 0.0044 cm = 44 µm.
6. Si Etch Rate (nm/min) = 2.86 × 10-13 × n F × T
1
-13
= 2.86 × 10
2
×e
− Ea
RT
15
×3×10 × (298)
1
2
×e
−2.48×103
1.987× 298
= 224.7 nm/min.
7. SiO2 Etch Rate (nm/min) = 0.614× 10
-13
15
×3×10 × (298)
1
2
×e
−3.76×103
1.987×298
= 5.6 nm/min
Etch selectivity of SiO2 over Si =
5.6
= 0.025
224.7
Or etch rate (SiO2)/etch rate (Si) =
0.614 ( −3.76+ 2.48)1.987×298
×e
= 0.025 .
2.86
8. A three–step process is required for polysilicon gate etching. Step 1 is a nonselective etch
process that is used to remove any native oxide on the polysilicon surface. Step 2 is a high
polysilicon etch rate process which etches polysilicon with an anisotropic etch profile. Step 3 is a
highly selective polysilicon to oxide process which usually has a low polysilicon etch rate.
9. If the etch rate can be controlled to within 10 %, the polysilicon may be etched 10 % longer or for
an equivalent thickness of 40 nm. The selectivity is therefore
40 nm/1 nm = 40.
10. Assuming a 30% overetching, and that the selectivity of Al over the photoresist maintains 3. The
minimum photoresist thickness required is
18
(1+ 30%) × 1 µm/3 = 0.433 µm = 433.3 nm.
11.
ωe =
qB
me
1.6 × 10 −19 × B
2π × 2.45 × 10 =
9.1 × 10 −31
9
B = 8.75 × 10-2(tesla)
= 875 (gauss).
12. Traditional RIE generates low-density plasma (109 cm-3) with high ion energy.
ECR and ICP generate high-density plasma (1011 to 1012 cm-3) with low ion energy.
Advantages of ECR and ICP are low etch damage, low microloading, low
aspect-ratio dependent etching effect, and simple chemistry. However, ECR and
ICP systems are more complicated than traditional RIE systems.
13. The corrosion reaction requires the presence of moisture to proceed. Therefore, the
first line of defense in controlling corrosion is controlling humidity. Low humidity
is essential,. especially if copper containing alloys are being etched. Second is to
remove as much chlorine as possible from the wafers before the wafers are
exposed to air. Finally, gases such as CF4 and SF6 can be used for fluorine/chlorine
exchange reactions and polymeric encapsulation. Thus, Al-Cl bonds are replaced
by Al-F bonds. Whereas Al-Cl bonds will react with ambient moisture and start
the corrosion process , Al-F bonds are very stable and do not react. Furthermore,
fluorine will not catalyze any corrosion reactions.
19
CHAPTER 6
1. Ea(boron) = 3.46 eV, D0 = 0.76 cm2/sec
From Eq. 6,
D = D0 exp(
− Ea
− 3.46


−15
2
) = 0.76 exp
 = 4.142 × 10 cm /s
−5
kT
 8.614 × 10 × 1223 
L = Dt = 4.142 × 10 −15 × 1800 = 2.73 × 10 −6 cm
From Eq. 9, C ( x ) = C s erfc(
x
x


) = 1.8 × 10 20 erfc 
−6 
2L
 5.46 × 10 
If x = 0, C (0) = 1.8 × 10 20 atoms /cm 3 ; x = 0.05 ×10-4, C(5× 10-6) = 3.6 × 1019
atoms/cm3; x = 0.075 ×10-4 , C(7.5×10-6) = 9.4 ×1018 atoms/cm3; x = 0.1×10-4,
C(10-5) = 1.8 × 1018 atoms/cm3;
x = 0.15× 10-4, C(1.5×10-5) = 1.8× 1016 atoms/cm3.
The x j = 2 Dt (erfc -1
C sub
) = 0.15µm
Cs
Total amount of dopant introduced = Q(t)
=
2
π
C s L = 5.54 × 1014 atoms/cm2.
− 3.46
 − Ea 


−14
2
2. D = D0 exp
 = 0.76 exp
 = 4.96 × 10 cm /s
−5
kT
×
×
8
.
614
10
1323




From Eq. 15, C S = C (0, t ) =
S
πDt
= 2.342 × 1019 atoms/cm 3
x
 x 


C ( x) = C S erfc  = 2.342 × 1019 erfc
−5 
 2L 
 2.673 × 10 
If x = 0, C(0) = 2.342 × 1019 atoms/cm3; x = 0.1×10-4, C(10-5) = 1.41×1019 atoms/cm3;
x = 0.2×10-4, C(2×10-5) = 6.79×1018 atoms/cm3; x = 0.3×10-4, C(3×10-5) = 2.65×1018
20
atoms/cm3;
x = 0.4×10-4, C(4×10-5) = 9.37×1017 atoms/cm3; x = 0.5×10-4, C(5×10-5) = 1.87×1017
atoms/cm3;
x = 0.6×10-4, C(6×10-5) = 3.51×1016 atoms/cm3; x = 0.7×10-4, C(7×10-5) = 7.03×1015
atoms/cm3;
x = 0.8×10-4, C(8×10-5) = 5.62×1014 atoms/cm3.
The x j = 4 Dt ln
S
C B πDt
= 0.72 µm .


10 −8

3. 1 × 1015 = 1 × 1018 exp
−13 
4
2
.
3
10
t
×
×


t = 1573 s = 26 min
For the constant-total-dopant diffusion case, Eq. 15 gives C S =
S
πDt
S = 1 × 1018 π × 2.3 × 10 −13 × 1573 = 3.4 × 1013 atoms/cm 2 .
4. The process is called the ramping of a diffusion furnace. For the ramp-down situation, the
furnace temperature T is given by
T = T0 - rt
where T0 is the initial temperature and r is the linear ramp rate. The effective Dt product
during a ramp-down time of t1 is given by
( Dt ) eff = ∫
t1
0
D (t )dt
In a typical diffusion process, ramping is carried out until the diffusivity is
negligibly small. Thus the upper limit t1 can be taken as infinity:
21
1
T
=
1
T0 − rt
≈
1
T0
(1 +
rt
T0
+ ...)
and
− Ea
 = D exp  − E a (1 + rt + ...) = D (exp − E a )(exp − rE a t ...) ≈ D (T ) exp − rE a t
D = D0 exp
0
0
0

 kT
2
2
kT 

T0
kT0
kT0
kT0

 0
where D(T0) is the diffusion coefficient at T0. Substituting the above equation into the
expression for the effective Dt product gives
∞
( Dt ) eff ≈ ∫ D (T0 ) exp
0
− rE a t
kT0
2
2
dt = D (T0 )
kT0
rE a
Thus the ramp-down process results in an effective additional time equal to kT02/rEa at the
initial diffusion temperature T0.
For phosphorus diffusion in silicon at 1000°C, we have from Fig. 6.4:
D(T0) = D (1273 K) = 2× 10-14 cm2/s
1273 − 773
r=
20 × 60
= 0.417 K / s
Ea = 3.66 eV
Therefore, the effective diffusion time for the ramp-down process is
kT
2
0
rE
a
=
1.38 × 10
−23
(1273)
0.417( 3.66 × 1.6 × 10
2
−19
)
= 91s ≈ 1.5 min .
5. For low-concentration drive-in diffusion, the diffusion is given by Gaussian distribution.
The surface concentration is then
C (0, t ) =
S
S
 E 
=
exp a 
πDt
πD0 t
 2kT 
22
dC
S
 E  − t 3 / 2
=
exp a 
dt
πD 0
 2kT  2
or
dC
C
= −0.5 ×

C
 = −0.5 ×
t

dt
t
which means 1% change in diffusion time will induce 0.5% change in surface
concentration.
dC
S
 E  − E a
exp a 
=
2
dT
πD0 t
 2kT  2kT
or
dC
C
=
−E
a
2 kT
×
dT
T
=
E

 = −C a 2
2kT

− 3.6 × 1.6 × 10 −19
2 × 1.38 × 10
− 23
× 1273
×
dT
T
= −16.9 ×
dT
T
which means 1% change in diffusion temperature will cause 16.9% change in
surface concentration.
6. At 1100°C, ni = 6×1018 cm-3. Therefore, the doping profile for a surface concentration
of 4 × 1018 cm-3 is given by the “intrinsic” diffusion process:
 x
C ( x, t ) = C s erfc
 2 Dt



where Cs = 4× 1018 cm-3, t = 3 hr = 10800 s, and D = 5x10-14 cm2/s. The diffusion
length is then
Dt = 2.32 × 10 −5 cm = 0.232µm
x


The distribution of arsenic is C ( x) = 4 × 1018 erfc
−5 
 4.64 × 10 
The junction depth can be obtained as follows
xj



1015 = 4 × 1018 erfc
−5 
4
.
64
10
×


xj = 1.2× 10-4 cm = 1.2 µm.
23
7. At 900°C, ni = 2× 1018 cm-3. For a surface concentration of 4×1018 cm-3, given by
the “extrinsic” diffusion process
D = D0 e
− Ea
kT
−4.05×1.6×10 −19
4 × 1018
n
− 23
× = 45.8e 1.38×10 ×1173 ×
= 3.77 × 10 −16 cm 2 /s
ni
2 × 1018
x j = 1.6 Dt = 1.6 3.77 × 10 −16 × 10800 = 3.23 × 10 −6 cm = 32.3 nm .
8. Intrinsic diffusion is for dopant concentration lower than the intrinsic carrier
concentration ni at the diffusion temperature. Extrinsic diffusion is for dopant
concentration higher than ni.
9. The SUPREM input file for this problem is:
TITLE
Problem 6-9
COMMENT
Initialize silicon substrate
INITIALIZE
Thickness = 5 <100> Silicon Phosphor Concentration=1e16
COMMENT
Diffuse Boron
DIFFUSIONT
ime=15 Temperature=850 Boron Solidsol
COMMENT
Perform Drive-In
DIFFUSIONT
ime=360 Temperature=1175
PRINT
Layers Active Concentration Phosphorus Boron Net
PLOT
Active Net Cmin=1e12
STOP
End Problem 6-9
Note that the thickness of the structure has been increased to 5 µm (in the INITIALIZE
statement) to accommodate an anticipated deeper junction. The resulting plot is shown
below. The junction depth occurs at approximately 3.48 µm.
24
10. The SUPREM input file for this problem is:
TITLE
Problem 6-10
COMMENT
Initialize silicon substrate
INITIALIZE
Thickness = 5 <100> Silicon Phosphor Concentration=1e16
COMMENT
Boron Predep
DIFFUSION
ime=15 Temperature=850 Boron Solidsol
COMMENT
Boron Drive-In
DIFFUSION
Time=360 Temperature=1175
COMMENT
Phosphorus Predep
DIFFUSION
Time=30 Temperature=850 Phosphor Solidsol
COMMENT
Phosphorus Drive-In
DIFFUSION
Time=30 Temperature=1000
PRINT
PLOT
Layers Active Concentration Phosphorus Boron Net
Active Net Cmin=1e13
25
STOP
End Problem 6-10
The resulting plot is shown below. There are 2 pn junctions formed. The junction
depths occur at approximately 0.45 and 3.49 µm, respectively.
26
CHAPTER 7
1. The ion dose per unit area is
It 10 × 10 −6 × 5 × 60
N q
1.6 × 10 −19
= =
= 2.38 × 1012 ions/cm 2
10 2
A A
π ×( )
2
From Eq. 1 and Example 1, the peak ion concentration is at x = Rp. Figure 7.6
indicates the σp is 20 nm.
Therefore, the ion concentration is
S
σ p 2π
2.
=
2.38 × 1012
20 × 10
−7
2π
= 4.74 × 1017 cm −3 .
From Fig. 7.6, the Rp = 230 nm, and σp = 62 nm.
The peak concentration is
S
σ p 2π
=
2 × 1015
62 × 10
−7
2π
= 1.29 × 10 20 cm −3
From Eq. 1,
 − (x j − Rp )2 
1015 = 1.29 × 10 20 exp 

2
2σ p


xj = 0.53 µm.
3. Dose per unit area =
Q C 0 ∆VT
3.9 × 8.85 × 10 −14 × 1
=
=
= 8.6 × 1011 cm − 2
q
q
250 × 10 −8 × 1.6 × 10 −19
From Fig. 7.6 and Example 1, the peak concentration occurs at 140 nm from the
surface. Also, it is at (140-25) = 115 nm from the Si-SiO2 interface.
27
4. The total implanted dose is integrated from Eq. 1
QT = ∫
S
∞
0
σp
 − (x − Rp )2 
R p   S
S  
S
=
+
−
1
1
erfc
(
)  = [2 − erfc( 2.3)] = × 1.9989
exp 
dx



2
2  
2
σ p 2   2
2π
 2σ p


The total dose in silicon is as follows (d = 25 nm):
Q Si = ∫
S
∞
d
σp
− (x − Rp )2 
R p − d   S
S  
S
dx
1
1
erfc
(
)  = [2 − erfc(1.87)] = × 1.9918
=
+
−
exp 



2
2  
2
σ p 2   2
2π
 2σ p


the ratio of dose in the silicon = QSi/QT = 99.6%.
5. The projected range is 150 nm (see Fig. 7.6).
The average nuclear energy loss over the range is 60 eV/nm (Fig. 7.5).
60× 0.25 = 15 eV (energy loss of boron ion per each lattice plane)
the damage volume = VD = π (2.5 nm)2(150 nm) = 3× 10-18 cm3
total damage layer = 150/0.25 = 600
displaced atom for one layer = 15/15 = 1
damage density = 600/VD = 2×1020 cm-3
2×1020/5.02×1022 = 0.4%.
6.
The higher the temperature, the faster defects anneal out. Also, the solubility of
electrically active dopant atoms increases with temperature.
7.
∆V t = 1 V =
Q1
C ox
where Q1 is the additional charge added just below the oxide-semiconductor
surface by ion implantation. COX is a parallel-plate capacitance per unit area
given by C ox =
εs
d
(d is the oxide thickness, ε s is the permittivity of the semiconductor)
28
1V × 3.9 × 8.85 × 10 −14 F/cm
C
Q1 = ∆Vt C ox =
= 8.63 × 10 −7
−6
cm 2
0.4 × 10 cm
8.63 × 10 −7
= 5.4 ×1012 ions/cm2
−19
1.6 × 10
Total implant dose =
8.
5.4 × 1012
= 1.2 × 1013 ions/cm2.
45%
The discussion should mention much of Section 7.3. Diffusion from a surface film
avoids problems of channeling. Tilted beams cannot be used because of
shadowing problems. If low energy implantation is used, perhaps with
preamorphization by silicon, then to keep the junctions shallow, RTA is also
necessary.
9.
From Eq.11
Sd 1
 0.4 − 0.6 
= erfc
 = 0.84
S
2
 0.2 2 
The effectiveness of the photoresist mask is only 16%.
Sd 1
 1 − 0.6 
= erfc
 = 0.023
S
2
 0.2 2 
The effectiveness of the photoresist mask is 97.7%.
10.
2
e -u
T=
= 10 −5
u
2 π
1
∴u = 3.02
d = Rp + 4.27 σ p = 0.53 + 4.27 × 0.093 = 0.927 µm
29
11. The SUPREM input file for this problem is:
TITLE
Problem 7-11
COMMENT Initialize silicon substrate
INITIALIZE <100> Silicon Phosphor Concentration=1e14
COMMENT Implant Boron
IMPLANT
Boron Energy=30 Dose=1e13
PRINT
Layers Active Concentration Phosphorus Boron Net
PLOT
Active Net Cmin=1e11
STOP
End Problem 7-11
The resulting doping profile is shown in the figure below.
Examining this figure and the SUPREM output file gives:
(a) The peak of the implanted boron occurs at a depth of 0.11 µm.
(b) The boron concentration at the peak is 8.59e17 cm-3.
(c) The junction depth is 0.4492 µm.
30
12. The SUPREM input parameters that must be determined are the dose and
implant energy. The dose can be determined from Eq. 11 in Chapter 6 as
Q(t ) ≅ 1.13Cs Dt
where Cs can be read directly from the SUPREM output file for Example 3 in
Chapter 6 as 4.6e19 cm-3, D ≈ 2.3e − 16 cm2/s for boron at 850 oC (see Figure
6.4), and t = 900 s. Substituting these numbers into the above expression gives
a dose of 2.36e13 cm-2.
The implant energy required can be approximated by matching the diffused
and implanted concentration profiles at the surface (x = 0) and at the junction
and using Eq. 1 to solve for Rp and σp simultaneously. Note from the
SUPREM output file corresponding to Example 3 in Chapter 6 that the
junction occurs at xj = 0.0555 µm, at which point the doping concentration is
1016 cm-3. As stated before, the surface concentration is 4.6e19 cm-3.
These equations cannot be solved analytically, but after several iterations, the
approximate values of Rp and σp required are found to be 0.011 µm and 0.008
µm, respectively. These values correspond to an implant energy of 5 keV
(extrapolating from Figure 7.6a). The require SUPREM input file is therefore:
TITLE
COMMENT
INITIALIZE
COMMENT
IMPLANT
PRINT
PLOT
STOP
Problem 7-12
Initialize silicon substrate
<100> Silicon Phosphor Concentration=1e16
Implant Boron
Boron Energy=5 Dose=2.36e13
Layers Active Concentration Phosphorus Boron Net
Active Net Cmin=1e11
End Problem 7-12
The resulting doping profile appears in the figure below.
31
32
CHAPTER 8
ν av =
1.
∫
∫
∞
0
∞
0
vf v dv
=
f v dv
4  M 
Where fν =


π  2kT 
8kT
πM
3/ 2
 Mν 2
 2kT
ν 2 exp −



M: Molecular mass
k: Boltzmann constant = 1.38×10-23 J/k
T: The absolute temperature
ν: Speed of molecular
So that
2. λ =
π
0.66
cm
P( in Pa )
∴P =
3.
2 × 1.38 × 10 −23 × 300
= 468 m/sec = 4.68 × 10 4 cm/sec .
29 × 1.67 × 10 − 27
2
ν av =
0.66
λ
=
0.66
= 4.4 × 10 −3 Pa .
150
For close-packing arrange, there are 3 pie shaped sections in the equilateral
triangle. Each section corresponds to 1/6 of an atom. Therefore
1
3×
number of atoms contained in the triangle
6
=
Ns =
area of the triangle
1
3
d×
d
2
2
=
2
3d 2
=
2
3 (4.68 × 10 −8 ) 2
= 5.27 × 1014 atoms/cm 2 .
33
dd
4.
(a) The pressure at 970°C (=1243K) is 2.9×10-1 Pa for Ga and 13 Pa for As2. The
arrival rate is given by the product of the impringement rate and A/πL2 :
 P  A 
Arrival rate = 2.64×1020 
 2 
 MT  πL 
 2.9 × 10 −1  5 

= 2.64×1020 
2 
 69.72 × 1243  π × 12 
= 2.9×1015 Ga molecules/cm2 –s
The growth rate is determined by the Ga arrival rate and is given by
(2.9×1015)×2.8/(6×1014) = 13.5 Å/s = 810 Å/min .
(b) The pressure at 700ºC for tin is 2.66×10-6 Pa. The molecular weight is 118.69.
Therefore the arrival rate is
 2.66 × 10 −6  5 

2.64 × 10 20 
= 2.28 × 1010 molecular/cm 2 ⋅ s
2 
π
12
×

 118.69 × 973 
If Sn atoms are fully incorporated and active in the Ga sublattice of GaAs, we
have an electron concentration of
 2.28 × 1010

15
 2.9 × 10
 4.42 × 10 22

2


 = 1.74 × 1017 cm -3 .

5. The x value is about 0.25, which is obtained from Fig. 8.7.
34
6. The lattice constants for InAs, GaAs, Si and Ge are 6.05, 5.65,5.43, and 5.65 Å,
respectively. Therefore, the f value for InAs-GaAs system is
f = (5.65 − 6.05) 6.05 = −0.066
And for Ge-Si system is
f = (5.43 − 5.65) 5.65 = −0.39 .
7. (a) For SiNxHy
Si 1
= = 1.2
N x
∴ x = 0.83
atomic % H =
100 y
= 20
1 + 0.83 + y
∴ y = 0.46
The empirical formula is SiN0.83H0.46.
(b) ρ= 5× 1028e-33.3×1.2 = 2× 1011 Ω-cm
As the Si/N ratio increases, the resistivity decreases exponentially.
8.
Set Ta2O5 thickness = 3t, ε1 = 25
SiO2 thickness = t, ε2 = 3.9
Si3N4 thickness = t, ε3 = 7.6, area = A
then
C Ta 2O5 =
1
C ONO
C ONO
C Ta 2 O5
C ONO
=
ε 1ε 0 A
3t
t
+
t
+
t
ε 2ε 0 A ε 3ε 0 A ε 2ε 0 A
εεε A
= 2 3 0
(ε 2 + 2ε 3 )t
=
ε 1 (ε 2 + 2ε 3 ) 25(3.9 + 2 × 7.6)
=
= 5.37 .
3ε 2 ε 3
3 × 3.9 × 7.6
35
9.
Set
BST thickness = 3t, ε1 = 500, area = A1
SiO2 thickness = t, ε2 = 3.9, area = A2
Si3N4 thickness = t, ε3 = 7.6, area = A2
then
ε 1ε 0 A1
3t
=
ε 2 ε 3ε 0 A2
(ε 2 + 2ε 3 )t
A1
= 0.0093.
A2
10. Let
Ta2O5 thickness = 3t, ε1 = 25
SiO2 thickness = t, ε2 = 3.9
Si3N4 thickness = t, ε3 = 7.6
area = A
then
ε 1ε 0 A
3t
d=
=
3ε 2 t
ε1
ε 2ε 0 A
d
= 0.468t.
36
11. The deposition rate can be expressed as
r = r0 exp (-Ea/kT)
where Ea = 0.6 eV for silane-oxygen reaction. Therefore for T1 = 698 K
  1
r (T2 )
1  
 
= 2 = exp 0.6
−
r (T1 )
  kT1 kT2  
ln 2 =
0.6  300 300  
 
−

0.0259  698 T2  
4 T2 =1030 K= 757 ℃.
12. We can use energy-enhanced CVD methods such as using a focused energy
source or UV lamp. Another method is to use boron doped P-glass which will
reflow at temperatures less than 900 .
13.
Moderately low temperatures are usually used for polysilicon deposition, and
silane decomposition occurs at lower temperatures than that for chloride reactions.
In addition, silane is used for better coverage over amorphous materials such
SiO2.
14. There are two reasons. One is to minimize the thermal budget of the wafer,
reducing dopant diffusion and material degradation. In addition, fewer gas phase
reactions occur at lower temperatures, resulting in smoother and better adhering
films. Another reason is that the polysilicon will have small grains. The finer
grains are easier to mask and etch to give smooth and uniform edges. However,
for temperatures less than 575 ºC the deposition rate is too low.
15. The flat-band voltage shift is
∆VFB = 0.5 V ~
C0 =
ε ox
d
=
Qot
C0
3.9 × 8.85 × 10 −14
= 6.9 × 10 −8 F/cm − 2 .
500 × 10 −8
∴ Number of fixed oxide charge is
37
0.5C 0 0.5 × 6.9 × 10 −8
=
= 2.1 × 1011 cm -2
−19
q
1.6 × 10
To remove these charges, a 450℃ heat treatment in hydrogen for about 30
minutes is required.
16.
20/0.25 = 80 sqs.
Therefore, the resistance of the metal line is
5×50 = 400 Ω .
17.
For TiSi2
30 × 2.37 = 71.1nm
For CoSi2
30 × 3.56 = 106.8nm.
18.
For TiSi2:
Advantage:
low resistivity
It can reduce native-oxide layers
TiSi2 on the gate electrode is more resistant to
high-field-induced hot-electron degradation.
Disadvantage: bridging effect occurs.
Larger Si consumption during formation of TiSi2
Less thermal stability
For CoSi2:
Advantage:
low resistivity
High temperature stability
No bridging effect
A selective chemical etch exits
Low shear forces
Disadvantage: not a good candidate for polycides
38
19. (a) R = ρ
εA
C=
d
L
1
= 2.67 × 10 − 6 ×
= 3.2 × 10 3 Ω
−4
−4
A
0.28 × 10 × 0.3 × 10
=
εTL
S
3.9 × 8.85 × 10 −14 × 0.3 × 10 −4 × 1 × 10 4 × 10 −6
= 2.9 × 10 −13 F
0.36 × 10 − 4
=
RC = 3.2 × 10 5 × 2.9 × 10 −15 = 0.93 ns
(b) R = ρ
L
1
= 1.7 × 10 − 6 ×
= 2 × 10 3 Ω
−4
−4
A
0.28 × 10 × 0.3 × 10
εA
εTL
2.8 × 8.85 × 10 −14 × 0.3 × 10 −4 × 1
= 2.1 × 10 −13 F
−4
d
S
0.36 × 10
3
−13
RC = 2 × 10 × 2.1 × 10 = 0.42 ns
C=
=
=
(c) We can decrease the RC delay by 55%. Ratio =
20. (a)
R=ρ
εA
0.42
= 0.45.
093
1
L
= 2.67 × 10 − 6 ×
= 3.2 × 10 3 Ω
4
4
A
0.28 × 10 × 0.3 × 10
εTL
3.9 × 8.85 × 10 −14 × 0.3 × 10 −4 × 1 × 3
= 8.7 × 10 −13 F
C=
=
=
4
d
S
0.36 × 10
RC = 3.2 ×103 ×8.7 × 10-13 = 2.8 ns.
.
(b) R = ρ
C=
1
L
= 1.7 × 10 − 6 ×
= 2 × 10 3 Ω
4
4
A
0.28 × 10 × 0.3 × 10
εA
d
=
εTL
S
=
2.8 × 8.85 × 10 −14 × 0.3 × 10 −4 × 1 × 3
= 6.3 × 10 −13 F
4
0.36 × 10
RC = 2 × 10 3 × 8.7 × 10 −13 = 2.5 ns
RC = 3.2 × 10 3 × 8.7 × 10 −13 = 2.5 ns.
21.
(a) The aluminum runner can be considered as two segments connected in
series: 20% (or 0.4 mm) of the length is half thickness (0.5 µm) and the
remaining 1.6 mm is full thickness (1µm). The total resistance is
A
 0.16

A 
0.04
+ −4
R = ρ  1 + 2  = 3 × 10 − 6  − 4
−4
−4 
10 × (0.5 × 10 ) 
10 × 10
 A1 A2 
39
= 72 Ω.
The limiting current I is given by the maximum allowed current density times
cross-sectional area of the thinner conductor sections:
I = 5×105 A/cm2× (10-4×0.5×10-4) = 2.5×10-3 A = 2.5 mA.
The voltage drop across the whole conductor is then
V = RI = 72Ω × 2.5 × 10 −3 A = 0.18V.
22.
0.5 µm
0.5 µm
40 nm
Cu
=
Al
60 nm
h: height , W : width , t : thickness, assume that the resistivities of the cladding
layer and TiN are much larger than ρ AA and ρ Cu
R Al = ρ Al ×
A
A
= 2.7
h ×W
(0.5 − 0.1) × 0.5
RCu = ρ Cu ×
A
A
= 1.7
h ×W
(0.5 − 2t ) × (0.5 − 2t )
When R Al = RCu
Then
⇒
2.7
1.7
=
0.4 × 0.5 (0.5 − 2t ) 2
t = 0.073 µm = 73 nm .
40
CHAPTER 9
1.
Each U-shape section (refer to the figure) has an area of 2500 µm × 8 µm = 2 × 104
µm2. Therefore, there are (2500)2/2 ×104 = 312.5 U-shaped section. Each section
contains 2 long lines with 1248 squares each, 4 corner squares, 1 bottom square,
and 2 half squares at the top. Therefore the resistance for each section is
1 kΩ /□ (1248×2 + 4×0.65 +2) = 2500.6 kΩ
The maximum resistance is then
312.5×2500.6 = 7.81 × 108 Ω = 781 MΩ
2. The area required on the chip is
41
A=
Cd
ε ox
=
(30 × 10 −7 )(5 × 10 −12 )
= 4.35 × 10 −5 cm 2
−14
3.9 × 8.85 × 10
= 4.35 × 103 µm2 = 66 × 66 µm
Refer to Fig.9.4a and using negative photoresist of all levels
(a) Ion implantation mask (for p+ implantation and gate oxide)
(b) Contact windows (2×10 µm)
(c) Metallization mask (using Al to form ohmic contact in the contact window and
form the MOS capacitor).
Because of the registration errors, an additional 2 µm is incorporated in all critical
dimensions.
42
3. If the space between lines is 2 µm, then there is 4 µm for each turn (i.e., 2×n, for one
turn). Assume there are n turns, from Eq.6, L ≈ µ0n2r ≈ 1.2 × 10-6n2r, where r can be
replaced by 2 × n. Then, we can obtain that n is 13.
43
4. (a) Metal 1, (b) contact hole, (c) Metal 2.
(a) Metal 1,
(b) contact hole,
(c) Metal 2.
44
5. The circuit diagram and device cross-section of a clamped transistor are shown in (a)
and (b), respectively.
6.
(a) The undoped polysilicon is used for isolation.
(b) The polysilicon 1 is used as a solid-phase diffusion source to form the
extrinsic base region and the base electrode.
(c) The polysilicon 2 is used as a solid-phase diffusion source to form the emitter region
and the emitter electrode.
7. (a) For 30 keV boron, Rp = 100 nm and ∆Rp = 34 nm. Assuming that Rp and ∆Rp for
45
boron are the same in Si and SiO2 the peak concentration is given by
S
2π ∆R p
8 × 1011
=
= 9.4 × 1016 cm −3
2π (34 × 10 )
−7
The amount of boron ions in the silicon is
 (x − R p )2
∞
Q
S
exp  −
=∫
d
q
2 ∆R p2
2π ∆R p

=
 Rp − d
S
2 − erfc
 2 ∆R
2
p


=
8 × 1011
2

dx






 750 

2 − erfc
 2 × 340 

= 7.88 × 1011 cm − 2
Assume that the implanted boron ions form a negative sheet charge near the Si-SiO2
interface, then
Q 
1.6 × 10 −19 × (7.88 × 1011 )
= 0.91 V
∆VT = q  / C ox =
3.9 × 8.85 × 10 −14 / (25 × 10 − 7 )
q
(b) For 80 keV arsenic implantation, Rp = 49 nm and ∆ Rp = 18 nm. The peak arsenic
concentration is
S
2π ∆R p
=
1016
π × (18 × 10 )
−7
46
= 2.21 × 10 21 cm − 3 .
8.
(a) Because (100)-oriented silicon has lower (~ one tenth) interface-trapped charge and a
lower fixed oxide charge.
(b) If the field oxide is too thin, it may not provide a large enough threshold
voltage for adequate isolation between neighboring MOSFETs.
(c) The typical sheet resistance of heavily doped polysilicon gate is 20 to
30 Ω /□, which is adequate for MOSFETs with gate lengths larger than 3 µm. For
shorter gates, the sheet resistance of polysilicon is too high and will cause large RC
47
delays. We can use refractory metals (e.g., Mo) or silicides as the gate material to
reduce the sheet resistance to about 1 Ω /□.
(d) A self-aligned gate can be obtained by first defining the MOS gate structure, then
using the gate electrode as a mask for the source/drain implantation. The
self-aligned gate can minimize parasitic capacitance caused by the source/drain
regions extending underneath the gate electrode (due to diffusion or
misalignment).
(e)
P-glass can be used for insulation between conducting layers, for diffusion and
ion implantation masks, and for passivation to protect devices from impurities,
moisture, and scratches.
9. The lower insulator has a dielectric constant ε1/ε0 = 4 and a thickness d1= 10 nm The
upper insulator has a dielectric constant ε2/ε0 = 10 and a thickness d2 = 100 nm. Upon
application of a positive voltage VG to the external gate, electric field E1 and E2 are
established in the d1 and d2 respectively. We have, from Gauss’ law, that ε1E1 = ε2E2 +Q
and VG = E1d1 + E2d2
where Q is the stored charge on the floating gate. From these above two equations, we
obtain
E1 =
VG
Q
+
d1 + d 2 (ε 1 / ε 2 ) ε 1 + ε 2 (d1 / d 2 )
48


10 × 10 7
−7 
+
J = σE1 = 10 
10 + 100 4 

 10 


Q

5
 = 0.2 − 2.26 × 10 Q

 10 
−14 
4 + 10 100  × 8.85 × 10 




(a) If the stored charge does not reduce E1 by a significant amount (i.e., 0.2 >> 2.26×105 Q,
we can write
Q = ∫ σE1 dt ' ≈ 0.2∆t = 0.2 × (0.25 × 10 − 6 ) = 5 × 10 −8 C
t
0
∆VT =
5 × 10 −8
Q
=
= 0.565 V
C2
10 × 8.85 × 10 −14 / 100 × 10 −7
(
)(
)
(b) when t → ∞, J → 0 we have Q → 0.2 / 2.26 × 10 5 ≅ 8.84×10-7 C.
Then ∆VT =
8.84 × 10 −7
Q
=
= 9.98 V.
C2
10 × 8.85 × 10 −14 / 10 −5
(
)
10.
49
50
11. The oxide capacitance per unit area is given by
C ox =
ε SiO
d
2
= 3.5 × 10 − 7 F/cm2
and the maximum current supplied by the device is
I DS ≈
1W
1 5µm
2
µC ox (VG − VT )2 =
3.5 × 10 −7 (VG − VT ) ≈ 5 mA
2 L
2 0.5µm
51
and the maximum allowable wire resistance is 0.1 V/5 mA, or 20Ω. Then, the
length of the wire must be
L≤
R × Area
ρ
=
20Ω × 10 −8 cm 2
= 0.074 cm
2.7 × 10 −8 Ω − cm
or 740 µm. This is a long distance compared to most device spacing. When
driving signals between widely spaced logic blocks however, minimum feature
sized lines would not be appropriate.
12.
52
13. To solve the short-channel effect of devices.
14. The device performance will be degraded from the boron penetration. There are
53
methods to reduce this effect: (1) using rapid thermal annealing to reduce the time
at high temperatures, consequently reduces the diffusion of boron, (2) using
nitrided oxide to suppress the boron penetration, since boron can easily combine
with nitrogen and becomes less mobile, (3) making a multi-layer of polysilicon to
trap the boron atoms at the interface of each layer.
15.
Total capacitance of the stacked gate structure is :
C=
ε1
d1
×
ε2
d2
 ε1 ε 2 
7 25  7
25 
 =
 +
×
+  = 2.12

0.5 10  0.5 10 
 d1 d 2 
3.9
= 2.12
d
∴d =
3.9
=1.84 nm.
2.12
16. Disadvantages of LOCOS: (1) high temperature and long oxidation time cause VT
shift, (2) bird’s beak, (3) not a planar surface, (4) exhibits oxide thinning effect.
Advantages of shallow trench isolation: (1) planar surface, (2) no high
temperature processing and long oxidation time, (3) no oxide thinning effect, (4)
no bird’s beak.
17. For isolation between the metal and the substrate.
18. GaAs lacks of high-quality insulating film.
19. Answers will vary. If we ignore the contributions of isolation region processing, the
structure can be simulated using four SUPREM input decks. The first deck simulates
54
processing in the active region of the device, up to the point of the isolation oxidation.
The second deck starts with the results from the first deck and completes all processing
in the active regions. This allows the doping profile through the emitter to be plotted
(for part b). The third deck is similar to the second, except it eliminates the emitter
implant and facilitates plotting of the doping profile through the base region (for part a).
The final deck is also similar to the second, except that it eliminates the base implant
and facilitates plotting the doping profile through the collector region (for part c). The
complete process sequence is as follows:
1) Begin with a high-resistivity, <100>, p-type silicon substrate.
2) Grow a 1 µm SiO2 layer.
3) Remove the oxide in the areas where the buried layers are to be placed.
4) Implant antimony at a dose of 1e15 cm-2. Drive in the buried layer for 5 hours at
1150 oC.
5) Etch the silicon dioxide from the surface.
6) Grow a 1.6 µm arsenic-doped epitaxial layer.
7) Grow a 400 Å pad oxide.
8) Deposit 800 Å of silicon nitride.
9) Etch the oxide and nitride from the isolation regions.
10) Etch the silicon halfway through the epi-layer.
55
11) Implant boron in the field regions with a dose of 1e13 cm-2 at an energy of 50
keV.
12) Oxidize the field regions to a thickness approximately one-half that of the
epi-layer.
13) Implant the base region with boron at a dose of 1e14 cm-2 at an energy of 50
keV.
14) Etch the oxide from the emitter region.
15) Implant emitter collector contact regions with arsenic at a dose of 5e15 cm-2 at
an energy of 100 keV.
16) Drive-in the arsenic and activate the base diffusion.
The SUPREM input decks are as follows:
TITLE
BJT – Deck 1
COMMENT
Initial Active Region Processing
COMMENT
Initialize silicon substrate
INITIALIZE
<100> Silicon Boron Concentration=5e14
COMMENT
Grow masking oxide for non-active regions
DIFFUSION
Time=100 Temperature=1150 WetO2
COMMENT
Etch oxide over buried layer regions
ETCH
Oxide
COMMENT
Implant and drive-in antimony buried layer
IMPLANT
Antimony Dose=5e14 Energy=120
DIFFUSION
Time=15 Temperature=1150 DryO2
DIFFUSION
Time=300 Temperature=1150
COMMENT
Etch the oxide
ETCH
Oxide
COMMENT
Grow 1.6 µm of arsenic-doped epi
EPITAXY
Temperature=1050 Time=4 Growth.Rate=0.4 Arsenic Gas.Conc=5e15
56
COMMENT
Grow 400 A pad oxide
DIFFUSION
Time=20 Temperature=1060 DryO2
COMMENT
Deposit nitride to mask the field oxidation
DEPOSITION
Nitride Thickness=0.08
SAVEFILE
Structur Filename=bjtactiveinit.str
STOP
End BJT 1
TITLE
BJT – Deck 2
COMMENT
Final Active Region Processing for Emitter Profile
COMMENT
Start with previous results
INITIALIZE
Structur=bjtactiveinit.str
COMMENT
Field oxide growth
DIFFUSION
Time=30 Temperature=800 t.rate=10
DIFFUSION
Time=15 Temperature=1000 DryO2
DIFFUSION
Time=210 Temperature=1100 Wet02
DIFFUSION
Time=15 Temperature=1100
DIFFUSION
Time=10 Temperature=1100 t.rate=-30
COMMENT
Etch the oxide and nitride layers
ETCH
Oxide
ETCH
Nitride
ETCH
Oxide
COMMENT
Implant boron base
IMPLANT
Boron Dose=1e14 Energy=50
COMMENT
Remove oxide from emitter region
ETCH
Oxide
COMMENT
Implant arsenic emitter and collector contacts
IMPLANT
Arsenic Dose=5e15 Energy=100
COMMENT
Drive-in emitter and collector contact regions
DIFFUSION
Time=20 Temperature=1000
PRINT
Layers
PLOT
Chemical Boron Arsenic Phosphor Net
STOP
End BJT 2
TITLE
BJT – Deck 3
COMMENT
Active Region Processing for Base Profile
COMMENT
Start with previous results
57
DryO2
INITIALIZE
Structur=bjtactiveinit.str
COMMENT
Field oxide growth
DIFFUSION
Time=30 Temperature=800 t.rate=10
DIFFUSION
Time=15 Temperature=1000 DryO2
DIFFUSION
Time=210 Temperature=1100 Wet02
DIFFUSION
Time=15 Temperature=1100
DIFFUSION
Time=10 Temperature=1100 t.rate=-30
COMMENT
Etch the oxide and nitride layers
ETCH
Oxide
ETCH
Nitride
ETCH
Oxide
COMMENT
Implant boron base
IMPLANT
Boron Dose=1e14 Energy=50
COMMENT
Remove oxide from emitter region
ETCH
Oxide
COMMENT
Drive-in emitter and collector contact region
DIFFUSION
Time=20 Temperature=1000
PRINT
Layers
PLOT
Chemical Boron Arsenic Phosphor Net
STOP
End BJT 3
TITLE
BJT – Deck 4
COMMENT
Active Region Processing for Collector Profile
COMMENT
Start with previous results
INITIALIZE
Structur=bjtactiveinit.str
COMMENT
Field oxide growth
DIFFUSION
Time=30 Temperature=800 t.rate=10
DIFFUSION
Time=15 Temperature=1000 DryO2
DIFFUSION
Time=210 Temperature=1100 Wet02
DIFFUSION
Time=15 Temperature=1100
DIFFUSION
Time=10 Temperature=1100 t.rate=-30
COMMENT
Etch the oxide and nitride layers
ETCH
Oxide
ETCH
Nitride
ETCH
Oxide
COMMENT
Remove oxide from emitter region
ETCH
Oxide
58
DryO2
DryO2
COMMENT
Implant arsenic emitter and collector contacts
IMPLANT
Arsenic Dose=5e15 Energy=100
COMMENT
Drive-in emitter and collector contact regions
DIFFUSION
Time=20 Temperature=1000
PRINT
Layers
PLOT
Chemical Boron Arsenic Phosphor Net
STOP
End BJT 4
The resulting doping profiles though the base, emitter, and collector (parts a, b, and c),
respectively, are shown in the following three figures:
(a)
59
(b)
60
(c)
20. Answers will vary. For the sake of simplicity, we will ignore isolation-related
processing. The structure can be simulated using four SUPREM input decks (one for
each requested profile). The complete process sequence is as follows:
61
1)
Start with a <100>, n-type silicon substrate.
2)
Grow a 0.9 µm SiO2 layer.
3)
Remove the oxide in the p-well areas.
4)
Implant boron well at a dose of 5e14 cm-2 at 50 keV.
5)
Drive in the p-well for 6 hours at 1150 oC.
6)
Remove oxide in PMOS source/drain regions.
7)
Implant boron for PMOS source/drain at a dose of 1e14 cm-2 at 20 keV.
8)
Drive in the PMOS source/drain regions for 2.5 hours at 1100 oC.
9)
Etch oxide in NMOS source/drain regions.
10) Implant phosphorus for NMOS source/drain at a dose of 1e14 cm-2 at 20 keV.
11) Drive in the NMOS source/drain regions for 2.5 hours at 1100 oC.
12) Etch oxide in gate areas.
13) Grow 500 Å gate oxide.
14) Deposit and pattern polysilicon gates.
15) Grow passivation oxide.
16) Deposit and pattern metallization.
The SUPREM input decks are and corresponding outputs as follows:
TITLE
CMOS – Deck 1
COMMENT
PMOS source/drain
COMMENT
Initialize silicon substrate
INITIALIZE
<100> Silicon Phosphorus Concentration=5e15 Thickness=5
62
COMMENT
Grow field oxide
DIFFUSION
Time=120 Temperature=1100 WetO2
COMMENT
Etch oxide after p-well implant
ETCH
Oxide
COMMENT
P-well drive-in
DIFFUSION
Time=900 Temperature=1150 DryO2
COMMENT
Etch the oxide prior to PMOS source/drain implant
ETCH
Oxide
COMMENT
PMOS source/drain implant
IMPLANT
Boron Dose=1e14 Energy=20
COMMENT
PMOS source/drain drive-in
DIFFUSION
Time=150 Temperature=1100 DryO2
COMMENT
NMOS source/drain drive-in and gate oxidation
DIFFUSION
Time=150 Temperature=1100 DryO2
COMMENT
Etch oxide
ETCH
Oxide
COMMENT
Deposit metal
DEPOSITION
Aluminum Thickness=1.0
PRINT
Layers
PLOT
Chemical Boron Phosphor Net
STOP
End CMOS 1
63
(a)
TITLE
CMOS – Deck 2
COMMENT
PMOS Gate
COMMENT
Initialize silicon substrate
INITIALIZE
<100> Silicon Phosphorus Concentration=5e15 Thickness=5
COMMENT
Grow field oxide
DIFFUSION
Time=120 Temperature=1100 WetO2
COMMENT
Etch oxide after p-well implant
ETCH
Oxide
COMMENT
P-well drive-in
DIFFUSION
Time=900 Temperature=1150 DryO2
64
COMMENT
Etch the oxide prior to PMOS source/drain implant
ETCH
Oxide
COMMENT
PMOS source/drain drive-in
DIFFUSION
Time=150 Temperature=1100 DryO2
COMMENT
NMOS source/drain drive-in and gate oxidation
DIFFUSION
Time=150 Temperature=1100 DryO2
COMMENT
Deposit polysilicon
DEPOSITION
Polysilicon Thickness=0.5
COMMENT
Grow passivation oxide
DIFFUSION
Time=30 Temperature=1000 DryO2
PRINT
Layers
PLOT
Chemical Boron Phosphor Net
STOP
End CMOS 2
65
(b)
TITLE
CMOS – Deck 3
COMMENT
NMOS source/drain
COMMENT
Initialize silicon substrate
INITIALIZE
<100> Silicon Phosphorus Concentration=5e15 Thickness=5
COMMENT
Grow field oxide
DIFFUSION
Time=120 Temperature=1100 WetO2
COMMENT
Etch oxide in p-well region
ETCH
Oxide
COMMENT
P-well implant
66
IMPLANT
Boron Dose=5e14 Energy=50
COMMENT
P-well drive-in
DIFFUSION
Time=900 Temperature=1150 DryO2
COMMENT
PMOS source/drain drive-in
DIFFUSION
Time=150 Temperature=1100 DryO2
COMMENT
Etch the oxide prior to NMOS source/drain implant
ETCH
Oxide
COMMENT
NMOS source/drain implant
IMPLANT
Phosphorus Dose=1e14 Energy=20
COMMENT
NMOS source/drain drive-in and gate oxidation
DIFFUSION
Time=150 Temperature=1100 DryO2
COMMENT
Etch oxide
ETCH
Oxide
COMMENT
Deposit metal
DEPOSITION
Aluminum Thickness=1.0
PRINT
Layers
PLOT
Chemical Boron Phosphor Net
STOP
End CMOS 3
67
(c)
TITLE
CMOS – Deck 4
COMMENT
NMOS gate
COMMENT
Initialize silicon substrate
INITIALIZE
<100> Silicon Phosphorus Concentration=5e15 Thickness=5
COMMENT
Grow field oxide
DIFFUSION
Time=120 Temperature=1100 WetO2
COMMENT
Etch oxide in p-well region
ETCH
Oxide
68
COMMENT
P-well implant
IMPLANT
Boron Dose=5e14 Energy=50
COMMENT
P-well drive-in
DIFFUSION
Time=900 Temperature=1150 DryO2
COMMENT
PMOS source/drain drive-in
DIFFUSION
Time=150 Temperature=1100 DryO2
COMMENT
Etch the oxide prior to NMOS source/drain implant
ETCH
Oxide
COMMENT
NMOS source/drain drive-in and gate oxidation
DIFFUSION
Time=150 Temperature=1100 DryO2
COMMENT
Deposit polysilicon
DEPOSITION
Polysilicon Thickness=0.5
COMMENT
Grow passivation oxide
DIFFUSION
Time=30 Temperature=1000 DryO2
PRINT
Layers
PLOT
Chemical Boron Phosphor Net
STOP
End CMOS 4
69
(d)
70
CHAPTER 10
1. x -chart: Center = µ = 0.75 V
UCL = µ +
LCL = 3-
3σ
3(0.1)
= 0.75 +
= 0.845 V
n
10
3σ
= 0.655 V
n
s-chart: Center = s = c4σ = 0.9727(0.1) = 0.0973 V
1
2
UCL = s + 3 σ 1 − c = 0.973 + 3(0.1)(1 − 0.9727) = 0.167 V
2
4
LCL = s - 3 σ 1 − c42 = 0.028 V
2. x -chart: Center = x = 0.734 V
UCL = x +
LCL = x −
3s
= 0.846 V
c4 n
3s
c4 n
= 0.622 V
s-chart: Center = s = 0.125 V
s
UCL = s + 3
1 − c 42 = 0.215 V
c4
LCL = s − 3
s
1 − c42 = 0.036 V
c4
3. Let ED = exposure dose, DT = develop time, BT = bake temperature
ED DT BT Y (1) (2) (3) Div. Eff. ID
60 137 264 534 8 66.75
Avg.
71
+
+
+
+
+
+
+
+
+
+
+
+
77
59
68
57
83
45
85
127
140
130
17
9
26
40
270
26
66
-10
-10
-8
14
92
-20
6
6
40
0
22
4
4
4
4
4
4
4
23
-5
1.5
1.5
10
0
5.5
ED
DT
ED x DT
BT
ED x BT
DT x BT
ED x DT x BT
4. Let: days = blocks (i.e., n = 3)
processes = treatments (i.e., k = 5)
Then we have:
Day 1
Day 2
Day 3
yt
A
B
C
D
E
yi
509
505
465
493
512
507
472
497
532
542
498
524
506
520
483
503
509
519
475
501
513.6
518.6
478.6
y = 503.6
ANOVA Table:
Source
Average (SA)
Blocks (SB)
Treatments (ST)
Residual (SR)
Sum of Squares
3,804,194.4
4,750
1,737.6
210
Degrees of Freedom
1
2
4
8
where: S A = nky 2 = 3,804,194.4
n
2
S B = k ∑ ( y i − y ) , DF = n – 1
i =1
k
2
S T = n∑ ( y t − y ) , DF = k – 1
t =1
k
2
n
S R ∑∑ ( y ti − y i − y t + y ) , DF = (n – 1)(k – 1)
t =1 i =1
Now:
s B2 / s R2 = 90.48
72
Mean Square
3,804,194.4
2,375
( s B2 )
434.4
( sT2 )
26.25
( s R2 )
sT2 / s R2 = 16.55
A. Significance level for the null hypothesis that the blocks are the same is very
low, since
P( F 2,8 > 90.48) ~0
B. The same is true for the hypothesis that the treatments are the same, since:
P ( F4,8 > 16.55) ~ 0
I.
II.
The processes are significantly different.
The processing dates have significant differences.
5. From Eq. 33: Y = exp(-AcD0)N = exp(-NAcD0)
where: Y = 0.95
N = 100,000
Ac = WL = (10e-4 cm)(1e-4 cm) = 1e-7 cm2
=> D =
− ln Y
= 5.13 cm-2
NAc
∞
6. Murphy’s Yield Integral (Eq. 34): Y = ∫ e − Ac D f ( D)dD
0
Uniform defect distribution: f ( D) = 1 / 2 D0 for 0 ≤ D ≤ 2 D0
Y=
2 D0
∫
0
e − Ac D
1 e − Ac D
dD =
2 D0
2 D0 − Ac
=> Yuniform =
2 D0
0
1 − e −2 D0 Ac
2 D0 Ac
Triangular defect distribution: f ( D) = D / D02 for 0 ≤ D ≤ D0
=−
73
D
2
+
for D0 ≤ D ≤ 2D0
2
D0 D0
D0
Y = ∫e
− Ac D
0
D
dD +
D02
2 D0
∫e
− Ac D
D0
 D
2 
 − 2 +
dD
 D0 D0 
1 e − AD
1 e − Ac D
2 e − Ac D
D
2 D0
(
)
Y = 2 2 (− Ac D − 1) 0 0 − 2
−
A
D
−
1
+
c
D0
D0 Ac
D0 Ac2
D0 − Ac
=> Ytriangular
 1 − e − D0 Ac
= 
 D0 Ac
Exponential Defect Distribution: f ( D) =



2 D0
D0
2
− D
1

exp
D0
D
 0 
∞
∞
∞
 − D(1 + Ac D0 ) 
 − D(1 + Ac D0 ) 
1 − Ac D − D / D0
1
1
exp 
exp 
Y =∫
e
e
dD =

dD =
∫
1 + Ac D0
D0
D0 0
D0
D0
0



0
=> Yexp onential =
1
1 + D0 Ac
7. Use Murphy’s Yield Integral (Eq. 34):
Y = ∫ e − AD f ( D)dD ,
0.1
Y=
∫e
−100 D
where: A = 100cm2, f(D) = -100D+10
(− 100 D + 10)dD
0.05
= -100
=
0.1
0.1
0.05
0.05
−100 D
−100 D
∫ De dD + 10 ∫ e dD
− 100 −100 D
( AD − 1) 00..105 − 10 e −100 D
e
4
100
10
0.1
0.05
=> Y = 0.094 %
74
CHAPTER 11
1. (a)
A 
1
 L 
RC =  ρ  ε ox  = 10 −5 ×
d 
1 × 0.5 × 10 −8
 A 
1 × (1 × 10 −4 )

−14
3
.
9
8
.
85
10
×
×
×


0.5 × 10 − 4 

= 2000 × (69.03 × 10 −14 ) = 1.38 × 10 − 9 s = 1.38 ns.
(b) For a polysilicon runner
L 
A

RC =  Rsquare  ε ox 
W 
d

 1 
= 30 − 4  69.03 × 10 −14 = 2.07 × 10 −7 s
 10 
= 207 ns
(
)
Therefore the polysilicon runner’s RC time constant is 150 times larger than the
aluminum runner.
2. When we combine the logic circuits and memory on the chip, we need multiple
supply voltages. For reliability issue, different oxide thicknesses are needed for
different supply voltages.
3. (a) 1
C total =
1
hence EOT
C Ta 2 O5
3.9
+ 1
= 75
25
C nitride
+ 10 = 17.3 Å
7
(b) EOT = 16.7 Å.
75