State of the Art of Lead-Free
Solder Joint Reliability
John H. Lau
1
Introduction
2
Thirty years ago, the author asked the key people in solder
materials, solder mechanics, and solder manufacturing to write a
book chapter in their expertise areas. The result was a book called
Solder Joint Reliability: Theory and Applications [1], published in
1991. Today, students, engineers, and researchers all over the
world still use the book as their references.
In the past 30 years, soldering technology has been changed
dramatically. In order to comply with RoHS (restriction of the use
of certain hazardous substances) regulations, the most challenging
one is from tin-lead solders to lead-free solders. Thus, the leadfree solder joint reliability is under scrutiny.
Reliability engineering consists of three major tasks, namely
design for reliability (DFR), reliability testing and data analysis,
and failure analysis, as schematically shown in Fig. 1. Usually,
the procedure starts with a design of the interconnects of a particular semiconductor integrated circuit (IC) package with, e.g., the
given chip size, the solder alloys, the molding compound, and the
corresponding printed circuit board (PCB) and demonstrates that
the design is electrically, thermally, mechanically, and chemically
sound. As an example, the DFR activity is often performed with a
finite element simulation using the structural geometry, material
properties of all the structural elements, and the imposed boundary conditions. The next step in the process is for a certain number
of samples of the sound or reliable design to be built and tested
under certain conditions for a certain period of time. The test data
(failures) then are analyzed and fitted into a life-distribution designation for the interconnects. Next, failure analysis should be done
on the failed samples to find out the root cause and understand the
reason for their failure. In this study, reliability testing and data
analysis and DFR of lead-free solder joints will be discussed and
demonstrated through examples. Some recommendations will also
be proposed.
Contributed by the Electronic and Photonic Packaging Division of ASME for
publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received March 27,
2020; final manuscript received July 22, 2020; published online September 3, 2020.
Assoc. Editor: Kaushik Mysore.
Journal of Electronic Packaging
Reliability Testing and Data Analysis
2.1 Definition of Reliability. In this study, reliability of an
interconnect (e.g., solder bump, solder joint, or microbump) of a
particular package in an electronic product is defined as the probability that the interconnect will perform its intended function for a
specified period under a given operating condition without failure
[2–26]. Numerically speaking, reliability is the percent of survivors; that is, R(x) ¼ 1 – F(x), where R(x) is the reliability (survival) function and F(x) is the cumulative distribution function
(CDF). Life distribution is a theoretical population model used to
describe the lifetime of an interconnect and is defined as the CDF,
that is, F(x) for the interconnect population. Thus, the one and
only way to determine the interconnect reliability is by reliability
testing to determine the F(x).
2.2 Objective of Reliability Test. The objective of reliability
tests is to obtain failures (the more, the better) and to best fit the
failure data to determine the parameters of the CDF of a chosen
probability distribution (e.g., Weibull and lognormal). The number of items (i.e., sample size) to be tested should be such that the
final data are statistically significant. The reliability test time is
unknown, but usually takes a while (e.g., a few months for thermal cycling tests). It should be noted and emphasized that as soon
as the life distribution F(x) of the interconnects is estimated by
reliability testing, the reliability R(x), failure rate, cumulative failure rate, average failure rate, mean-time-to-failure, etc. of the
interconnects are readily determined [2–26].
Most reliability tests are accelerated tests, with increased intensity of exposure to aggressive environmental conditions and realistic sample sizes and test times. Thus, acceleration models are
needed to map (transfer) the failure probability, reliability function, failure rate, and mean-time-to-failure from a test condition to
an operating condition. In establishing the acceleration models for
lead-free interconnects, their surrounding materials (e.g., solder,
molding plastic, ceramic, copper, fiber-reinforced glass epoxy,
and silicon), loadings (e.g., stress, strain, temperature, humidity,
current density, and voltage), and failure mechanisms and modes
C 2021 by ASME
Copyright V
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Fellow ASME
Research and Development Department,
Unimicron Technology Corporation,
Taoyuan 33341, Taiwan
e-mail: John_Lau@Unimicron.com
The state of the art of lead-free solder joint reliability is investigated in this study.
Emphasis is placed on the design for reliability (DFR) and reliability testing and data
analysis. For DFR: (a) the Norton power creep constitutive equations and examples for
Au20Sn, Sn58Bi, Sn3.8Ag0.7Cu, and Sn3.8Ag0.7Cu0.03Ce, (b) the Wises two power
creep constitutive equations and examples for Sn3.5Ag and Sn4Ag0.5Cu, (c) the Garofalo
hyperbolic sine creep constitutive equations and examples for Sn3.5Ag, Sn3Ag0.5Cu,
Sn3.9Ag0.6Cu, Sn3.8Ag0.7Cu, Sn3.5Ag0.5Cu, and Sn3.5Ag0.75Cu, Sn4Ag0.5Cu, Sn(3.53.9)Ag(0.5-0.8)Cu, 100In, Sn52In, Sn3.8Ag0.7Cu0.03Ce, and Au20Sn, and (d) the Anand
viscoplasticity constitutive equations and examples for Sn3.5Ag, Sn3Ag0.5Cu,
Sn3.8Ag0.7Cu, Sn3.8Ag0.7CuCe, Sn3.8Ag0.7CuAl, Au20Sn, Sn3.5Ag with temperature
and strain rate-dependent parameters, and Sn1Ag0.5Cu, Sn2Ag0.5Cu, Sn3Ag0.5Cu, and
Sn4Ag0.5Cu after extreme aging will be discussed. For reliability testing and data analysis: (a) the Weibull and lognormal life distributions for lead-free solder joints under
thermal-cycling and drop tests, (b) the true Weibull slope, true characteristic life, and
true mean life, and (c) the linear acceleration factors for various lead-free solder alloys
based on: (i) frequency and maximum temperature, (ii) dwell time and maximum temperature, and (iii) frequency and mean temperature will be presented. Some recommendations will also be provided. [DOI: 10.1115/1.4048037]
(e.g., overload, fatigue, corrosion, and electromigration) must be
considered.
2.4 Test Methods. Some common tests for semiconductor
packaging and interconnection are
temperature cycling tests (e.g., 25 ! 125 C),
power cycling tests (depend on devices),
functional cycling tests (depend on devices),
high-/low-temperature storage tests (120 C/20 C),
biased 85/85 tests (85 C/85% relative humidity, 1.8 V),
high-voltage extended life tests (100 C, 1.8 V),
pressure cook tests (autoclave tests) (121 C, 2 atm),
salt atmosphere test (MIL-STD-883D),
moisture sensitivity tests (e.g., IPC/JEDEC-020C),
shock (drop) tests (e.g., JESD 22-B111),
vibration tests (e.g., JESD 22-B103),
mechanical bending, shearing, and twisting tests (e.g., IPC/
JEDEC-9702),
It should be noted that these test methods can be applied to reliability and qualification. The key differences between reliability
tests and qualification tests are: (1) number of failures; (2) sample
size; (3) test setup; (4) data acquisition system; (5) data extraction
method; (6) computer software; and (7) test duration. For leadfree solder joint reliability, the thermal cycling test and drop test
are the most used tests and thus they will be briefly mentioned
first.
2.4.1 Thermal Cycling Test. Thermal cycling is the most
common test in solder joint reliability. For example, the solder
joint reliability of a fan-out wafer-level package of a
10 mm 10 mm chip on a PCB [18–22], as shown in Fig. 2,
subjected to thermal cycling has been reported. The package
dimensions are 13.4 mm 13.4 mm, and there are three
redistribution-layers (RDLs) and has 908 solder balls at 0.2 mmdiameter on 0.4 mm-pitch. The dimensions of the PCB are
103 mm 52 mm 0.65 mm. The PCB has six layers and is made
of fiber glass-4 and the pad finishing is organic solderability preservative. It is nonsolder mask defined and the solder mask opening diameter is 0.28 mm. There are four packages on a PCB as
shown in Fig. 2. There are daisy chains on package solder-ball
pads. The solder balls are made of Sn3Ag0.5Cu.
A ten temperature zones nitrogen 150 N oven is used for the
reflow of the fan-out packages on the PCB. The temperature profile is shown in Fig. 3. It can be seen that the maximum temperature is 245 C and the time above 217 C is 85 s. Figure 3 also
Fig. 1 Reliability engineering: design for reliability, reliability test and data analysis, and failure analysis
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2.3 Objective of Qualification Test. Unlike reliability tests,
the objective of qualification tests is “PASS” or “NOT PASS” and
the test time is well defined ahead of time. As soon as there is a
failure before the agreed test time, the test will usually stop and
failure analysis is performed to find out why it fails. After all the
changes, e.g., redesign, a new qualification test will start again.
The sample size of qualification tests is usually less than that of
reliability tests. In short, the objective of qualification tests is not
intended to obtain failures nor life distribution (or reliability).
electromigration test (e.g., JEP154),
others
shows the cross section of one of the package PCB assembly. It
can be seen that the solder joints are properly made (no bridging
and head-in-pillow), and the daisy chain on the PCB pads is
clearly seen. The pads on both package and PCB are interconnected in an alternating pattern so as to provide a daisy chain connection (for continuous measurement during testing) after they are
assembled.
Fifteen boards (each with four packages) are used for the temperature cycling tests. The sample size is 60 packages. Thermal
cycling is performed in a Votsch 7027-15 environmental chamber.
This unit is capable of achieving chamber temperature as high as
190 C and as low as 70 C. Heating and cooling are achieved
by forced convection, and the maximum ramp rate is 15 C per
minute. All of the boards are placed vertically in the chamber as
shown in Fig. 4(a). The temperature input to the chamber (measured in the air of the chamber) is from room temperature to 85 C
and stay there for 15 min, then ramp down to 40 C and stay
there for 15 min, then ramp up to 85 C and stay there for 15 min,
and so for. The ramp up and ramp down times are 15 min each.
The acquisition system is an Agilent 30970A data logger as shown
in Fig. 4(b).
The thermal cycling test results of the fan-out package solder
joint (without underfill) are fitted into a Weibull distribution and
are shown in Fig. 4(c). The thermal cycling test stops at 1100
cycles and there are 14 failures (including one early failed at 58
cycles.) The failure criterion is when the resistance of the daisy
Journal of Electronic Packaging
chain of the PCB fan-out package assembly increases by 50%.
The cycle at which the first solder joint of the package failed is
considered as the cycle-to-failure of the lead-free package. It can
be seen that the characteristic life (63.2% failed) of the Weibull
plot is 2382 cycles which is more than adequate for the expecting
life (usually is less than 3 years) of mobile product such as the
smartphones and tablets.
The failure locations occur at the package corner solder joints,
see Fig. 4(d), and at the corner solder joints right underneath the
chip corners. The failure mode is the cracking of the solder interface between the RDL3 of the fan-out package and the bulk solder
as shown in Fig. 4(e).
2.4.2 Drop Test. For mobile products, completing a drop test
is a very important task. The package and the PCB are the same
as those [18–22] for the thermal cycling test. The drop test setup
is according to JEDEC Standard JESD22—B111 as shown in
Fig. 5. After more than 20 tries, the right height of the drop table
is obtained which yields the drop spectrum with 1500 G/ms as
shown in Fig. 6.
The drop condition is 1000 drops. There are 24 samples. The
ones without underfill failed very early and the failure mode is the
broken of the Cu conductor wiring of the RDL near the solder
joint. Another 24 PCB assemblies (samples) are made and underfilled. The material properties of the underfill are: the filler content ¼ 25%, the maximum filler size ¼ 5 lm, the average filler
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Fig. 2 Fan-out wafer-level package of a 10 mm 3 10 mm chip and the solder joint reliability test PCB
size ¼ 1–2 lm, the curing time and curing temperature ¼ 8 min at
135 C or 5 min @ 150 C. Young’s modulus, Poisson’s ratio, and
thermal expansion coefficient are, respectively, 4–5 GPa, 0.35,
and 50–52 106/ C. The drop condition is also 1000 drops. The
results (with Weibull distribution) are shown in Fig. 6. It can be
seen that the characteristic life of the RDLs under drop test is
1271 drops and all 24 samples passed 480 drops without failure.
Thus, the solder joints and RDLs of the package should be reliable
under drop for mobile applications. The first failure occurs after
500 drop and the failure modes are shown in Fig. 7. It can be seen
that the RDLs of the fan-out package are broken. In this case, the
epoxy molding compound of the fan-out package has cracks and
the underfill between the package and PCB also has cracks. However, the solder joint did not fail during the drop test.
2.4.3 More Examples on Thermal Cycling and Drop Tests. In
automotive electronics, the trends are driving lead-free solder
joint reliability for new functions such as the advanced driverassistance systems. Under-the-hood operations often require high
sustained heating/cooling temperatures. Sharmaet al. [26] have
been providing some reliability results. Figure 8(a) shows the fanout wafer-level package with two lead-free (SnAgCu-A (SACA)
and SnAgCu-B (SACB)) solder balls. For both solder joints, one
is with under bump metallurgy (UBM) and the other is not. The
package size is 7 mm 7 mm with 249 solder balls on 0.4 mm
pitch. The temperature condition is 40 ! 125 C for the PCB
level test. The Weibull plot of the test results is shown in Fig. 9. It
can be seen that (a) for both solders, the one with UBM performs
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better than the one without, and (b) solder joints with SACB alloy
perform much better than those with SACA alloy.
The failure modes are shown in Figs. 8(b) and 8(c), respectively, for the SACA without UBM (at 475 cycles) and SACA
with UBM (at 525 cycles). It can be seen that with the presence of
UBM, which improves the strain/strength of the solder ball/UBM
interface, the primary failure mode shifts to solder ball/PCB pad
interface.
The PCB level drop test (1500 g/0.5 ms) results are shown in
Fig. 10. It can be seen that: (a) the solder joints with SACB alloy
w/o UBM perform better than those of SACA without UBM; (b)
for the SACB with UBM assembly there is only one fail at 679
drops and the test stopped at 1000 drops; (c) for the SACB without UBM, there is only one fail at 432 drops and the test stopped
at 1000 drops; and (d) for the SACA without UBM, the first fail at
35 drops and the 50% failures at 500 drops.
2.5 Statistical Analysis of Reliability Data—Weibull
2.5.1 Weibull PDF, CDF, Reliability, Failure Rate, and
MTTF. The three-parameter (c, h, b) Weibull probability density
function (PDF) is given by [27–34]
" #
b x c b1
xc b
exp 0
f ð xÞ ¼
h
h
h
x c;
1 < c > þ1;
h > 0;
(1)
b>0
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Fig. 3 Reflow temperature profile of the fan-out package on PCB with daisy chains
The reliability function, R(x) is given by
" #
xc b
Rð xÞ ¼ 1 Fð xÞ ¼ exp h
f ðxÞ b x c b1
¼
RðxÞ h
h
ð1
0
1
xf ð xÞdx ¼ c þ hC 1 þ
b
(5)
Ð1
where CðtÞ is the gamma function, CðtÞ ¼ 0 ed dt1 dd:
The median life, or T50 point for the Weibull is found by letting
F(T50) ¼ 0.5 to yield
1
T50 ¼ c þ hðln2Þb
(6)
2.5.2 Weibull Parameters Estimation. Equation (2) can be
rewritten as follows:
1
¼ blnð x cÞ blnh
(7)
ln ln
1 FðxÞ
n h
io
1
or Y ¼ aX þ b where Y ¼ ln ln 1FðxÞ
; X ¼ lnð x cÞ; a ¼ b;
(3)
The failure rate, h(x) is
hð xÞ ¼
Eð xÞ ¼ MTTF ¼
(4)
The expected value, E(x), or mean-time-to-failure, MTTF (or
mean life) is
b ¼ blnh:
Equation (7) represents a straight line with a slope, a (or b), and
intercept (b) on the Cartesian X-Y coordinates. Hence, a plot of
lnlnf[1/(1 F(x))]g against ln(xc) will also be a straight line
with a slope, a (or b). However, it is cumbersome to calculate X
and Y for each application as shown in chapter 2 of Ref. [6]. A
Weibull probability paper with the vertical scale as lnlnf[1/(1 F(x))]g and the horizontal axis as ln-scale can expedite the conversion. The Weibull plots shown in Figs. 4, 6, 9, and 10 are some
of the examples.
Fig. 4 (a) Thermal cycling chamber. (b) Data acquisition system. (c) Weibull plot of the thermal cycling test results of the fanout PCB assembly. (d) Failure location of solder joints. (e) Failure mode of the solder joint.
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where x is the random variable (e.g., life or cycles), c is the
expected minimum value of x (it also referred to as the location
parameter), h is the characteristic value or the scale parameter,
which could be used to represent the quality of a product, and b is
the Weibull slope, or the shape parameter, which is a measure of
the uniformity of a product (the larger the slope, the more uniform
is the product). It is frequently reasonable to assume that the
expected minimum value of life (c) of the population, i.e., the
lower bound of life of the population, is equal to zero, then we
have the two-parameter (h, b) Weibull distribution.
The Weibull CDF is given by [27–34]
" #
ðx
xc b
f ðtÞdt ¼ 1 exp (2)
F ð xÞ ¼
h
1
Drop test setup
2.5.3 Ranking. Rankings are values assigned to items in a
sample to determine their relative (failure) occurrence in a population. The median of these values (numbers) is then used as a true
rank of the failure out of the group tested. This is known as
median, or 50% rank, which can be approximated by
F(x) ¼ ( j 0.3)/(n þ 0.4), where j ¼ failure order number and
n ¼ sample size. In Figs. 4, 6, 9, and 10, the Weibull plots are
with the median (50%) rank.
In order to make sure the estimated parameters (e.g., the characteristic life) are within the intervals for a given confidence level,
Fig. 6 Drop test spectrum. Weibull plot of the drop test results.
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Fig. 5
rankings other than the median are necessary. For other required
ranking (G), the percent rank (z) can be determined by (z is the
percent rank of the jth value in n samples) [27–34]
nðn 1Þ 2
n
n1
n2
z ð1 zÞ
1 ð1 zÞ nzð1 zÞ
2!
nðn 1Þ ðn j þ 1Þ j1
njþ1
z ð1 zÞ
¼G
ð j 1Þ!
Weibull distribution (i.e., c ¼ 0). In this case, the characteristic
life (h) can be determined at
Fðx ¼ hÞ ¼ 1 exp fðh=hÞb g ¼ 0:632 ¼ 63:2%
(8)
Figure 11 shows the Weibull plot of the test data at median rank.
It can be seen that the Weibull slope (b) ¼ 2.8 and the characteristic life (h) ¼ 5478 cycles. Once the b and h are experimental estimated, important reliability questions such as the following can
be readily answered:
What is the probability that the 256-pin lead-free PBGA will
fail by 1500 cycles?
F(1500) ¼ 1 exp[(1500/5478)2.8] ¼ 0.026, i.e., 2.6% of
the lead-free PBGA will fail at 1500 cycles.
If we use 1000 units of them, how many do we expect to fail
in the first 1500 cycles?
We will expect 1000 0.026 ¼ 26 lead-free PBGAs will fail
in the first 1500 cycles.
What is the probability that the 256-pin PBGA lead-free solder joints will survive 1200 cycles?
R(1200) ¼ exp[(1200/5478)2.8] ¼ 0.9859, i.e., 98.59% of
the lead-free PBGA will survive at 1200 cycles.
What is the failure rate of the 256-pin lead-free PBGA at
1500 cycles? h(1500) ¼ (2.8/5478)(1500/5478)1.8 ¼ 49,657
109 per cycle ¼ 49,657 FITs (ppm/k)
Fig. 7 Failure modes of the fan-out lead-free package PCB assembly subjected to a drop test (>500 drops). (a) The fan-out
package PCB assembly. (b) Cross section of the assembly. (c) and (d) Close-up of a cracked RDL; a cracked epoxy molding
compound; and a cracked underfill (but no crack in the solder joint).
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For example, given the sample size n ¼ 10 and the required ranking G ¼ 95%. The percent failure rank (z) is 25.89% for j ¼ 1;
39.42% for j ¼ 2; 50.69% for j ¼ 3; 60.76% for j ¼ 4; 69.65% for
j ¼ 5; 77.76% for j ¼ 6; 85% for j ¼ 7; 91.27% for j ¼ 8; 96.32%
for j ¼ 9; and 99.49% for j ¼ 10. The 95% failure rank of the lowest of ten measurements is 25.89%. This means that in 95% of the
cases the lowest of ten would represent as much as 25.89% of the
population. Only in 5% of cases would the lowest of ten represent
even more than 25.89% of the population.
Let’s consider the thermal cycling test of a 256-pin plastic ball
grid array (PBGA) package on a PCB with Sn3Ag0.5Cu solder
joints (Fig. 11). The test condition is 25 ! 125 C, one cycle
per hour, 15 min ramp time and 15 min dwell time. The sample
size is 20 and the failure criterion is a 50% increase in resistance.
The test results are tabulated in Table 1 along with their median
rank percent failed, F(x). First, we consider the two-parameter
(9)
What is the MTTF of the 256-pin lead-free PBGA?
MTTF ¼ 5478 C(1 þ 1/2.8) ¼ 5478 C(1.357) ¼ 5478 0.89 ¼ 4875 cycles.
Now, let’s consider the three-parameter Weibull distribution
(i.e., c 6¼ 0). A try-and-error of the c is necessary. The c which fits
the test data into a curve is the correct one. Figure 12 shows the
curve fitting of the three parameter Weibull plot at median rank.
Fig. 9 Thermal cycling results of the 249 fan-out PCB assembly (Weibull plots)
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Fig. 8 (a) Fan-out package with 249 SAC solder joints. (b) Failure mode of SACA solder joint without UBM. (c) Failure mode of
SACA solder joint with UBM.
The two-parameter Weibull plot at median rank is also shown for
comparison purpose. It can be seen that both the three-parameter
and two-parameter plots agree very well at percent failed ⭌ 4%.
However, at lower percent failed, e.g., at 1% failed, the twoparameter Weibull plot over predicts the solder joint life. From
here on, only two-parameter Weibull will be considered, i.e.,
c ¼ 0.
2.5.4 True Weibull Slope. Confidence is defined as the probability that a given interval determined from the test data will contain the population parameters, such as (using Weibull as an
example) the mean/characteristic life and Weibull slope.
Confidence applies to the test itself and reliability applies to the
product!
To predict the true Weibull slope (bt) of the population, it is
necessary to estimate the Weibull slope error in relation to the
sample size and the required confidence level. The error (E) in the
Weibull slope depends on the number of failures (N) and the
required confidence level (C), which can be searched from the following equation [27–34]:
1
pffiffiffi
p
ffi
ð Epffiffiffiffi
2N
1
t2
e 2 dt ¼
1þC
2
(10)
Fig. 11 A 256-pin PBGA package. Weibull plot of the PBGA PCB solder joints subjected to thermal cycling test.
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Fig. 10 Drop test results of the 249 fan-out PCB assembly (Weibull plots)
Table 1 Test results of a lead-free 256-pin PBGA with median
rank, 5% rank, and 95% rank
Failure
order
F(x) median
rank
F(x) 5%
rank
F(x) 95%
rank
1650
2100
2650
3100
3500
3800
4200
4500
4600
4800
5000
5150
5300
5450
5600
5900
3.4
8.3
13.2
18.1
23.0
27.9
32.8
37.7
42.6
47.5
52.5
57.4
62.3
67.2
72.1
77.0
0.3
1.8
4.3
7.3
10.5
14.0
17.9
21.8
25.9
30.3
34.7
39.6
44.3
49.3
54.4
59.6
13.9
21.8
28.6
34.8
40.4
45.6
50.7
56.7
60.4
65.3
69.7
74.1
78.1
82.2
86.0
89.5
The integral in Eq. (10) cannot be carried out in close-form and is
approximated by the following:
ð pffiffiffiffiffi
1 E 2N t2
pffiffiffiffiffiffi
e 2 dt ¼ 1Zð xÞ b1 tþb2 t2 þb3 t3 þb4 t4 þb5 t5 þeð xÞ
2p 1
where
1
x2
Z ð xÞ ¼ pffiffiffiffiffiffi e 2
2p
1
t¼
1 þ px
pffiffiffiffiffiffi
x ¼ E 2N
2.5.5 True Characteristic Life. For a given C (the confidence
level), in order to predict the population (true) mean (l) or population (true) characteristic value (ht) from the sample test data, it
is necessary to determine the CDFs (life distributions) with certain
percent ranks for the required confidence interval from Eq. (8).
The lower percent ranks and upper percent ranks for C ¼ 95% are
respectively 2.5% and 97.5%; for C ¼ 90% are 5% and 95%; for
C ¼ 80% are 10% and 90%; for C ¼ 70% are 15% and 85%; and
for C ¼ 60% are 20% and 80%.
For example, for a given confidence level C ¼ 0.9, the true
characteristic life (63.2% failed), ht, of the 265-pin PBGA
SnAgCu solder joints will happen (by determining the life distributions for the 95% rank and 5% rank) within the intervals 4493
cycles ht 6029 cycles as shown in Fig. 14.
2.5.6 True Mean Life. The mean life, i.e., MTTF from test
samples can be determined by Eq. (5) with h ¼ 5478 and b ¼ 2.8,
and is equal to [MTTF ¼ 5478U(1 þ 1/2.8) ¼ 5478U(1.357)
¼ 5478 0.89 ¼ 4875 cycles], which occurs at 51.4% failed [by
Eq. (2) with x ¼ 4875, h ¼ 5478 and b ¼ 2.8]. The true mean life,
l, of the 265-pin PBGA SnAgCu solder joints will happen within
the intervals 3846 l 5578 cycles. The values of the intervals
have been determined by rewriting Eq. (2) and with the following
forms:
1
x ¼ h½lnð1 FðxÞÞ b
llower ¼ h95% Rank ½lnð1 0:514Þ 1=b95% Rank ¼ 4493½0:72 1=2:1
¼ 3846 cycles
lupper ¼ h5% Rank ½lnð1 0:514Þ 1=b5% Rank ¼ 6029½0:72 1=4:2
¼ 5578 cycles
Fig. 12 Three-paramater versus two-parameter Weibull plots
of the 256-pin PBGA PCB solder joints subjected to thermal
cycling test
020803-10 / Vol. 143, JUNE 2021
Fig. 13 Weibull slope error
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Cycles-to-failure
and p ¼ 0.2316419, b1 ¼ 0.31938153, b2 ¼ 0.356563782, b3 ¼
1.781477937, b4 ¼ 1.821255978, b5 ¼ 1.330274429, and
je(x)j < 7.5 108.
Thus, for a given C (the confidence level) and N (the number of
failures), the E (error) can be searched from the above equations.
For engineering practice convenience, Eq. (10) has been plotted
into a design chart (Fig. 13) for various values of C and N. For
example, for a given confidence C ¼ 0.9 (that means in 90 out of
100 cases) the Weibull slop error of the example shown in Fig. 11
(with N ¼ 16 failures) is (by Fig. 13) E ¼ 0.3. Thus, the true Weibull slope bt of the 256-PBGA SnAgCu solder joints will be happened in the intervals of (2.8 0.3 2.8) bt (2.8 þ 0.3 2.8)
or 1.96 bt 3.64.
The reliability of the lognormal distribution is given as
ð1
1
ðt lÞ2
Rð xÞ ¼ 1 Fð xÞ ¼ 1 pffiffiffiffiffiffi
exp dt
2r2
r 2p lnðxÞ
(14)
The MTTF of the lognormal distribution is given by
MTTF ¼ exp l þ
r2
2
(15)
The median of the lognormal distribution (T50) is given as
Fig. 14 Weibull plots of the 256-pin PBGA SAC solder joints at
90% confidence
where h5% rank ¼ 6029, b5% rank ¼ 4.2 and h95%
¼ 2.1 have been substituted.
rank ¼ 4493,
b95%
rank
T50 ¼ expðlÞ
or
l ¼ lnT50
(16)
2.6.2 Lognormal Parameters Estimation. Rewrite Eq. (12)
into the following form:
2.6 Statistical Analysis of Reliability Data—Lognormal
2.6.1 Lognormal PDF, CDF, Reliability, Failure Rate, and
MTTF. If time-to-failure has a lognormal distribution, then the
(natural) logarithm of the time-to-failure has a normal distribution
with mean (l) and standard deviation (r). The PDF of the standard two-parameter lognormal distribution is given as [27–34]
1
ð lnx lÞ2
(11)
f ð xÞ ¼ pffiffiffiffiffiffi exp 2r2
xr 2p
where x is the random variable of the lognormal distribution, r is
the shape parameter (of the standard deviation of the normal distribution), and l is the location parameter (of the mean of the normal distribution).
The CDF of the standard two-parameter lognormal distribution
is given as [27–34]
ð1
ð1
1
ðt lÞ2
lnx l
f ðtÞdt ¼ pffiffiffiffiffiffi
exp dt
¼
U
F ð xÞ ¼
r
2r2
r 2p lnðxÞ
x
(12)
where A(z) denotes the CDF of the standard normal distribution.
Fig. 15 Lognormal plot of the 256-pin PBGA solder joints
Journal of Electronic Packaging
logx ¼
r 1
U ½FðxÞ þ logT50
ln10
(17)
where U1 denotes the inverse function for the standard normal
distribution. Letting Y ¼ x and X ¼ U1[F(x)], then log Y is linear
in X with slop ¼ r/ln10 and intercept (when F(x) ¼ 0.5) of log T50.
On a lognormal probability plot, use a logarithmic Y axis. Use the
plotting position estimates for F(xi) to calculate pairs of (Xi, Yi)
points. If the data are consistent with a lognormal distribution, the
resulting plot will have points that line up roughly on a straight
line with slope ¼ r/ln10 and intercept T50 on the log Y axis.
Figure 15 shows the lognormal plot (50% rank) of the 256-pin
PBGA package on a PCB with Sn3Ag0.5Cu solder joints shown
in Fig. 11. The lognormal plots of the 256-pin PBGA with 5%
rank and 95% rank are shown in Fig. 16. With these plots, the life
interval of the 256-pin PBGA lead-free solder joints for different
percent failures at 90% confidence can be determined.
Another example on using lognormal distribution for lead-free
solder joints has been given by Vasudevan and Fan [35]. Their
test board is shown in Fig. 17. There are 15 FC (flip chip) ball
grid array (BGA) packages on the board. Each package consists of
a chip with size of 9 mm 11.7 mm and an organic substrate with
size of 37.5 mm 37.5 mm. The solder ball diameter is 0.56 mm,
on a 1 mm-pitch, and made of Sn4.0Ag0.5Cu. The temperature
range of the thermal cycling test is 40 ! 85 C. Two different
dwell times of 15 min and 30 min, respectively, are applied.
Figure 17 shows the lognormal plot of the Sn37Pb and
Sn4Ag0.5Cu solder joints at two different dwell times (15 and
30 min). It can be seen that the longer dwell time (30 min) reduces
the thermal fatigue life significantly for both SnPb and SnAgCu
solders. However, SnPb shows a smaller reduction compared to
Sn4Ag0.5Cu solder. It also can be seen that the difference in thermal fatigue life between Sn4Ag0.5Cu and SnPb is reduced as
dwell time is increased.
The cross section showing the crack propagation of the SnPb
solder joints near the chip edge, after 1400 cycles with a longer
(4-hour) dwell time, is shown in Fig. 18(a). The cross section
showing the crack propagation of the Sn-4.0Ag-0.5Cu solder
joints near the chip edge, after 1400 cycles with a longer (4-hour)
dwell time, is shown in Fig. 18(b). They look similar, except there
are more cracks in the SnPb solder joints and the crack length in
the SnPb solder joints is longer.
JUNE 2021, Vol. 143 / 020803-11
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The failure rate of the lognormal distribution is given as
1
ð lnx lÞ2
pffiffiffiffiffiffi exp 2r2
xr ð 2p
hð xÞ ¼
1
1
1 tl 2
pffiffiffiffiffiffi exp2ð r Þ dt
1
lnðxÞ r 2p
(13)
2.8 Why Acceleration Models? In reliability tests, the most
idea situation is to have the test conditions very close to the use
(operating) conditions. However, because of time-to-market and
costs saving, this is almost impossible. The practical way is to run
accelerated tests with increased intensity, and realistic sample
sizes and test times. (Thus, most reliability tests are accelerated
tests.) In this case, the price to pay is to construct the acceleration
factors to map (transfer) the failure probability, reliability function, mean life, and failure rate from a test condition to the service
operating (use) condition. Acceleration models are needed for
determining the acceleration factors [36].
As mentioned earlier, the best-fit Weibull life distribution of a
set of lead-free interconnects is
" #
xT b T
(18)
FT ðxT Þ ¼ 1 exp hT
where FT, xT, hT, and bT are the life distribution, time-to-failure,
characteristic life, and shape parameter (or Weibull slope), respectively, at the test condition. Let’s consider the following acceleration model (transformation or mapping) [36]:
xo ¼ axgT
(19)
where xo is the time-to-failure at operating condition, a is the
acceleration factor, and g is a larger than zero real number, e.g.,
8.8. Then, we have
Fo ðxo Þ ¼ 1 exp ½ðxo =ho Þbo
(20)
Ro ðxo Þ ¼ exp ½ðxo =ho Þbo
(21)
ho ðxo Þ ¼
bo xo bo 1
ho ho
(22)
bT
g
(23)
ho ¼ ahgT
(24)
bo ¼
where Fo, Ro, ho, xo, ho, and bo are the life distribution, reliability,
failure rate, time-to-failure, characteristic life, and Weibull slope,
respectively, at the operating condition.
2.8.1 Linear
acceleration [36]
Acceleration. When
g ¼ 1,
i.e.,
linear
xo ¼ axT
(25)
bo ¼ bT
(26)
ho ¼ ahT
(27)
Fo ðxo Þ ¼ 1 exp ½ðxo =ahT ÞbT
(28)
then we have
ho ðxo Þ ¼
Fig. 16 Lognormal plots of the 256-pin PBGA SAC solder
joints at 90% confidence
020803-12 / Vol. 143, JUNE 2021
bT 1
bT
xo
ahT ahT
(29)
It can be seen that, for a linear acceleration (g ¼ 1), the Weibull
CDF plots of the operating condition and testing condition should
have the same Weibull slope (i.e., the shape parameter remains
the same), and the characteristic life is different by a factor of the
acceleration factor. It should be pointed out and emphasized that
the same Weibull slope is not an assumption but just came out naturally for linear acceleration [36]. Thus, if two or more different
test cells (with different temperature conditions) of the same leadfree interconnects yield very different Weibull slopes, then either
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2.7 A Note on Failure Criteria. As mentioned earlier, the
one and only way to determine the reliability, failure rate, characteristic life, mean life, etc., of lead-free solder joints is by reliability tests. The most important factor in reliability tests is the failure
criteria.
During reliability tests, we continuously perform the resistance
measurements. The failure criterion is defined as the resistance
increases to certain (e.g., 1 to 1) percentages of the original
resistance. Usually daisy chains, which connect the solder interconnects of the chip/package and substrate/PCB, allow the measurements. Since most solder joints under fatigue loadings will go
through crack initiation, crack propagation, and crack rupture
sooner or later, the daisy chains’ resistance will increase accordingly, that is, from small to large, and become 1 when the solder
joint is totally cracked (opened). (Most people unintentionally
pick the last one.) Since the exact “resistance versus crack length”
relations of various lead-free solder joints do not exist today, people just randomly pick a number, which is from 1 to 1 percent of
the initial resistance. That is one of the reasons why there are so
many different Weibull/lognormal plots in the lectures, even with
the same package, PCB, solder paste, sample size, test condition,
and test period.
Figure 19 shows the Weibull plots of a 208-pin plastic quad flat
pack (PQFP) with a lead-free solder paste subject to 40 !
125 C thermal cycling. A computer stored all the resistance
measurements. Let’s define one failure criterion as 10% resistance
increase and the other as 40% increase. It can be seen from the
Weibull plots that: (1) the life distribution is many times different
from the failure criterion based on the 10% resistance increase
and the 40% resistance increase; (2) for the same percent failures,
the life taken from the failure criterion based on higher resistance
increases is longer; and (3) as expected, there are more failures
with the failure criterion based on lower resistance increases.
Another important factor affecting the results of reliability testing is data extraction. During tests, how many measurements
should we take at each cycle? It could be four measurements,
eight measurements, or measure at every minute. In order to avoid
false failures, it is recommended to compare the measurements of
every channel at every two consequence cycles (no matter if it is
four measurements, eight measurements, or measure at every
minute.) A three-cycle moving average method is recommended.
Please read [12] for more details.
the linear acceleration model is not good (i.e., g 6¼ 1), or the Weibull distribution is not fitted with the test data, or both. Usually,
the Weibull distribution adequately represents fatigue failures;
thus, higher/lower acceleration models (g 6¼ 1) may need to be
determined. All the papers in the literature have been using the
linear acceleration, i.e., g ¼ 1, or xo ¼ / xT or No ¼ / NT .
2.8.3 Square-Root Acceleration. Finally, let’s consider g ¼ 1/2
(square-root acceleration, xo ¼ axT1/2) [36], then we have
(bo ¼ 2bT and ho ¼ a冑hT)
pffiffiffiffiffi
Fo ðxo Þ ¼ 1 exp ½ðxo =a hT Þ2bT
(33)
2.8.2 Quadratic Acceleration. When g ¼ 2 (quadratic acceleration, xo ¼/ xT 2 Þ [36]. Then we have (bo ¼ bT/2 and ho ¼ ahT2)
pffiffiffiffiffi
Ro ðxo Þ ¼ 1 exp ½ðxo =a hT Þ2bT
(34)
2bT 1
2bT
xo
pffiffiffiffiffi
ho ðxo Þ ¼ pffiffiffiffiffi
a hT a hT
(35)
Fo ðxo Þ ¼ 1 exp ½ðxo =ah2T ÞbT =2
(30)
Ro ðxo Þ ¼ exp ½ðxo =ah2T ÞbT =2
(31)
bT xo 2T 1
2ah2T ah2T
b
ho ðxo Þ ¼
(32)
In this case, the Weibull slope of the operating condition is half of
that of the test condition, while the characteristic life of the operating condition is ahT times of that of the test condition.
Fig. 18 (a) Failure mode for SnPb solder joints. (b) Failure
mode for Sn4Ag0.5Cu solder joints.
Journal of Electronic Packaging
Fig. 19 Weibull plots for a 208-pin PQFP with 10% and 40%
resistant change failure criterions
JUNE 2021, Vol. 143 / 020803-13
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Fig. 17 Flip chip BGA test board with Sn4Ag0.5Cu solder joints. Thermal cycling test results (lognormal plots).
2.9 Acceleration Factors
2.9.1 Determination of Acceleration Factors. How to determine a (the acceleration factor)? The answer is that you need an
acceleration model, which has been discussed in the previous section. How do you choose an acceleration model? The answer is
tests and failure mechanisms!
2.9.2 Some Well-Known Linear Acceleration Factors. For
SnPb solder joints, the following Norris–Landzberg linear acceleration factor, Eq. (2.68) of Ref. [6], has been frequently used
c
q fo
DTT
exp ½1414ð1=To 1=TT Þ
(36)
a¼
fT
DTo
In these equations, TT, fT, DTT, and To, fo, DTo, are the maximum
temperature during cycling (in Kelvin), the temperature cycling
frequency, and the temperature range (in degree Celsius), respectively, at testing condition and at operating condition. For SnPb
solders, q ¼ 1/3, and c ¼ 1.9 – 2.0 have been used.
2.9.3 Linear Acceleration Factor for Sn3Ag0.5Cu in
Terms of Dwell Time and Maximum Temperature. For
Sn3Ag0.5Cu, Pan et al. [37] proposed a modification of the classical Norris–Landzberg Eq. (36) by replacing the cyclic frequency
(f) with dwell time at high temperature (t). For a nonlinear curve
fit of the temperature cycling data of the CBGA (ceramic ball grid
array), chip scale package (CSP), and thin small outline package
(TSOP) on PCB at various temperature ranges such as 0 ! 60 C,
0 ! 100 C, and 25 ! 125 C, Pan et al. [37] obtained the following acceleration factor:
a¼
DTt
DTo
2:65 0:136
tt
1
1
exp 2185
Tmax; o Tmax; t
to
(37)
where tt and to are the dwell time at high temperature, DTt and
DTo are the temperature range (in degree Celsius) during thermal
cycling, and Tmax,t and Tmax,o are the maximum (peak) temperature (in Kelvin) attained during thermal cycling, respectively, at
testing condition and at operating condition. It should be noted
that the effect of dwell time on the acceleration factor is (tt/to).
Since to (operating dwell) is usually longer than tt (testing dwell),
thus for a positive power, (tt/to) is a deceleration factor. This is
just like the effect of (fo/ft) in the classical Norris–Landzberg
model, Eq. (36); usually, ft (testing frequency) is larger than fo
(operating frequency).
As an example based on the above discussion, consider the test
conditions are: 0 ! 100 C with the dwell time at high temperature ¼ 15 min and the operating conditions are: 20 ! 70 C with
the dwell time at high temperature ¼ 720 min. Then the acceleration factor is:
a¼
0:136
2:65 100
15
1
1
exp 2185
50
720
273 þ 70 273 þ 100
¼ 6:18
For other surface mount devices (SMDs) and test conditions, Miremadi et al. [38] obtained the following linear acceleration factor
with Sn3Ag0.5Cu solder alloy:
a¼
DTt
DTo
A B
tt
1
1
exp C
Tmax;o Tmax;t
to
(38)
The constants A, B, and C are shown in Table 2 for three SMDs
and test conditions.
2.9.4 Linear Acceleration Factor for Sn3Ag0.5Cu in Terms of
Frequency and Maximum Temperature. For Sn3Ag0.5Cu, some
of the researchers still use the classical Norris–Lanzberg acceleration model, Eq. (36), i.e., in terms of the cyclic frequency and
maximum temperature during thermal cycling. For PBGA, fcPBGA, CBGA (ceramic ball grid array), CSP, quad flat pack, flip
chip, etc. with test conditions such as DT ¼ 135 C and
DT ¼ 180 C, Lall et al. [39] obtained the following acceleration
factor for Sn3Ag0.5Cu:
a¼
Fig. 20 Weibull plots from test and for various acceleration
models
020803-14 / Vol. 143, JUNE 2021
DTt
DTo
2:3 0:3
fo
1
1
exp 4562
Tmax; o Tmax; t
ft
(39)
For example, in the thermal cycling test of the fan-out lead-free
(Sn3Ag0.5Cu) package of the 10 mm 10 mm chip, Figs. 2–4,
the test conditions are 40 ! 85 C with 24 cycles per day, and
we know that the product can survive 280 cycles. However, we
also need to know if this value of 280 cycles is sufficient to meet
the 5-year operating condition given by 20 ! 60 C with 1 cycle
per day (see the calculations below).
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It can be seen that, in this case, the Weibull slope at the operating
condition is two times of that at test condition, while the characteristic life at operating condition is equal to the acceleration factor times the square-root of the characteristic life at test condition.
Similar results can be generated for other values of n, i.e., other
accelerations.
Figure 20 shows the Weibull plot of a set of lead-free test data
with bT ¼ b1 ¼ 4 and hT ¼ g1 ¼ 3000. Assuming a ¼ 2, then the
acceleration models for g ¼ 1, 1.5, and 0.5 are given in Fig. 20. It
can be seen that when g ¼ 1, the Weibull plot is parallel to the
tested one.
In most solder joint reliability tests of IC packages on PCBs,
luxury of running multiple thermal cycling conditions is not available (due to the test time, chamber occupation, and manpower).
Thus, acceleration models are required to predict the life distribution and failure rate of the solder joints under anticipated service
conditions. In the literature, for SnPb and lead-free solders, the
linear acceleration has been assumed.
It should be emphasized that the linear acceleration, Eq. (25)
with g ¼ 1 is only one form of accelerations. There are many other
accelerations, e.g., g 6¼ 1 and x0 ¼ axgT þ fxnT . More reliability tests
should be performed for a variety of IC packages and temperature
cycling conditions to establish the suitable acceleration
model [36].
a¼
2:3 0:3
125
1
1
1
exp 4562
40
24
273 þ 60 273 þ 85
Table 3 Linear acceleration factors for various lead-free solders in terms of frequency and mean temperature [40]
¼ 13:79
The product with SAC305 will survive 13.79 280 cycles per
day ¼ 3861 365 ¼ 10.5 years > 5 years.
a¼
DTt
DTo
a b
fo
1
1
exp c
Tmean; o Tmean; t
ft
¼ 4:73
3
cycles
c
SAC305
SAC405
SAC205
SAC105
SAC0307
SN100C
SN100C-SAC305
SAC105-Ni
SAC107
2.728
3.380
2.974
3.292
3.094
3.126
2.833
2.517
2.738
0.345
0.352
0.274
0.309
0.230
0.215
0.240
0.302
0.341
1602
2234
1888
1883
1926
1766
1379
1287
2078
DTt
DT0
a b
fo
1
1
exp C
Tmean;0 Tmean;t
ft
(40)
2:728 0:345
100
1
1
1
exp 1602
40
24
273 þ 40 273 þ 50
The
product will
survives
4.73 990
day ¼ 4682.7 365 ¼ 12.82 years > 10 years.
b
a¼
where a, b, and c are the coefficients for the temperature range
(DT), frequency (f), and mean temperature during cycling (Tmean),
respectively. A nonlinear curve fit of the temperature cycling data
of the ChipArray BGA and Thin ChipArray BGA on PCB at various temperature ranges such as 0 ! 100 C, 40 ! 100 C, 40
! 125 C, 25 ! 125 C, and 15 ! 125 C, the constants a, b,
and c of the above equation have been obtained by Osterman [40]
and are tabulated in Table 3.
For example, for Sn3Ag0.5Cu (SAC305), a ¼ 2.728, b ¼ 0.345,
and c ¼ 1602, the test conditions are: 0 ! 100 C with 24 cycles
per day and find the product survives 990 cycles. Is it sufficient
for a 10-year operating conditions of 20 ! 60 C with 1 cycle per
day?
a¼
a
per
provide comparison between structural geometries.
Figure 21 shows the simple key DFR steps
first identify and define the structural geometry and materials
construction,
then apply the kinetic and kinematics boundary conditions,
it is followed by problem definition, e.g., overload, or
fatigue, or both,
then use a commercial available computer code to solve the
equations, and
it is followed by post processing (data analysis) and life
prediction.
For DFR of lead-free solder joints, the constitutive equation of
the solder is the most important property.
3.1 Constitutive Equations for Solder Alloys. In the literatures, there are many constitutive equations for DFR of lead-free
solder joints. In this study, we will discuss four different kinds,
namely (1) Norton power creep [41–52, and 53], (2) Wises twopower creep [46,47,50,51, and 54–62], (3) Garofalo hyperbolic
sine creep [41–43,49,51,52,54,63–89, and 90], and (4) Anand viscoplasticity [41,51,54,63–65,68,91–102, and 103–105].
Design for Reliability
In the past three decades, DFR of solder joints is becoming
very important. DFR is usually performed by a mathematical
modeling based on the material properties and geometries of the
structure, and laws of engineering and physics in order to:
eliminate trial-and-error of reliability tests,
reduce cost,
reduce test and failure analysis cycles,
reduce time-to-market,
provide insight into the physical, electrical, mechanical, and
thermal behaviors of the solder joints, e.g., (a) the maximum
stress–strain locations—to help test-board designs to capture
the most likely (solder joint) failure locations and to help
failure analysis to find these failures sites, and (b) the failure
mode—to help failure analysis to look for crack and
delamination,
provide comparison between material properties, and
Table 2
3.2 Norton Power Creep. Figure 22(a) shows a typical creep
curve that can be obtained from “long-time” uni-axial test at constant load and constant temperature [106]. The slope of this curve
(_e ¼ de/dt, e ¼ strain and t ¼ time) is referred to as the creep rate
(_e Þ. At the first stage, the creep rate is undefined and the initial
creep strain consists of either entirely elastic strain or partially
elastic strain and partially plastic strain. During the second stage,
the creep rate decreases with time because the effect of strain
hardening is greater than that of annealing (recovery). These two
effects are in equilibrium (balance) during the third stage and the
creep rate reaches essentially a steady-state and changes very little
with time. However, during the fourth stage, the creep rate
increases rapidly with time until fracture occurs. This is because
the reduced cross-sectional area (either due to necking or to internal void formation) causes an increase in stress.
The second stage of creep is called primary creep. During this
period, the primary creep is dominated by transient creep. The
Linear acceleration factors for Sn3Ag0.5Cu solder in terms of dwell time and maximum temperature [38]
Test components and conditions
(i) For CSP component with a sample size of 10 and test condition ¼25 ! 100 C
(ii) For LCCC and CBGA with a sample size of 67 and test condition ¼ 25 ! 100 C
(iii) For TSOP and TQFP with a sample size of eight and test condition ¼ 25 ! 100 C
a¼
DTt
DT0
A
B
C
2.86
1.07
2.14
0.077
0.18
0.21
4532
4286
274
A B
tt
1
1
exp C
Tmax;0 Tmax;t
t0
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2.9.5 Linear Acceleration Factor for Sn3Ag0.5Cu and Other
Lead-Free Solders in Terms of Frequency and Mean Temperature. Osterman [40] proposed another modification of the classical
Norris–Landzberg Eq. (36) by replacing the maximum temperature during thermal cycling with mean temperature during thermal
cycling. The revised equation takes the following form:
Lead-free solders
third stage of creep is called secondary creep or steady-state creep.
The average value of creep rate during secondary creep is called
the minimum creep rate. Log-log plots of stress versus minimum
creep rate for various temperatures are essentially straight lines
for many metals. The fourth stage of creep is called tertiary creep,
which is often associated with microstructural changes such as
coarsening of precipitate particles, recrystallization, or diffusional
changes in the phases that are present.
Figure 22(b) shows a family of creep curves test at constant
temperature and various stress conditions (r4 > r3 > r2 > r1). The
angles of the minimum creep rate at various creep curves (u ¼ e_ Þ
are u4 > u3 > u2 > u1. Figure 22(c) also shows the corresponding
stress versus minimum creep rate curves at various constant temperature (T4 > T3 > T2 > T1). Finally, Fig. 22(d) shows the stress
versus creep strain rate (_e Þ at constant temperature. These curves
can be used to fit (determine) the constitutive equation for creep
analysis of structure.
The Norton power creep law is given by [53]
n Q
(41)
e_ ¼ Ar
RT
where e_ is the steady-state creep stain rate (1/s), r is the applied
stress (MPa), R is the Boltzmann’s constant (7.617 105 eV/K),
and T is the absolute temperature (Kelvin). The constants A, n,
and Q for a particular lead-free solder can be determined from the
creep curve of that solder such as that shown in Fig. 22.
3.2.1 Norton Power Creep Constitutive Equation for Au20Sn,
Sn58Bi, Sn3.8Ag0.7Cu, and Sn3.8Ag0.7Cu0.03Ce Solder Alloys.
For Au20Sn [6,107,108], Sn58Bi [6,107,108], Sn3.8Ag0.7Cu
[49], and Sn3.8Ag0.7Cu0.03Ce [49], the constants A, n, and Q in
Eq. (41) have been experimentally determined and are given in
Table 4. These are the material property inputs for finite element
codes such as ANSYS and ABAQUS.
3.2.2 Example on Using the Norton Power Creep Constitutive
Equation of Au20Sn and Sn58Bi. Figure 23 schematically details
the construction of a vertical-cavity surface-emitting lasers
(VCSEL) assembly [107,108]. The GaAs chip is mounted on a silicon substrate with four flip chip solder joints. The 2 2 solder
joints have a 250 lm pitch. Both the AlGaAs light source and the
copper pad have 80 lm diameters and 5 lm thicknesses. The
assembled joint height is 75 lm.
This study compares the effects of thermal conductivity of the
Au20Sn solder with that of Sn58Bi to simulate potential inservice operating temperature distributions. These temperature
distributions are then applied to the VCSEL assembly over a 24 h
period to assess the stresses in the AlGaAs pads and the
020803-16 / Vol. 143, JUNE 2021
3.3 Wises Two-Power Creep. Wises et al. [59–62] proposed
to modify Norton power creep Eq. (41) into the sum of two power
law terms as shown in Fig. 26 and the followings:
n1
n2
r
r
Q1
r
Q2
exp exp þ A2
(42)
e ¼_ þ A1
E
rn
rn
RT
RT
The first term is for the initial stress (elastic), the second term corresponds to the creep behavior at low stresses, where co-operative
climb processes are dominant, and the third term corresponds to
the creep behavior at high stresses, where combined glide/climb
processes dominate (Fig. 26). The commercial finite element
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Fig. 21 Key steps in design for reliability of solder joints
accumulated creep damage at the solder joints for each candidate
material.
The finite element model is shown in Fig. 23. Due to the geometric symmetry that exists in the package, only one octant was
modeled. On the external surfaces, convection coefficients, as
depicted in Fig. 24, are applied. Heat flow is prohibited across the
cut symmetry planes.
Initially, a transient analysis was performed to evaluate the
time-temperature response of the VCSEL. Figure 24 presents the
time-temperature response at the center of the AlGaAs pad during
the first minute of the analysis. (The AuSn and SnBi solder joints
behave almost the same.) This representative data indicate that the
VCSEL achieves a steady-state temperature distribution within
approximately 20 s.
Since the structural analysis that follows examines the VCSEL
over a 24 h period and due to the brevity of the time-dependent
thermal response, the transient analysis was discarded in favor of
a steady-state thermal analysis. The resulting temperature profiles
are shown in Fig. 24. While the results do not demonstrate temperature differences of engineering significance based on solder
alloy, still it can be seen at the laser (AlGaAs pad) that the temperature of the device with AuSn (106.52 C) is smaller than that
(106.77 C) with SnBi.
Temperatures from the thermal analysis are applied as nodal
thermal loads in the structural analysis. Two load steps are evaluated. For both load steps, the package is assumed to be stress
free at 20 C. The first has duration of 1 s and the second has duration of 24 h. In the first load step, which is a reasonable approximation of powering up the VCSEL, the nodal temperatures ramp
from room temperature to the values determined in the thermal
analysis. In the subsequent 24 h load step, the node temperatures
are held constant at the thermal analysis values.
Thermal stresses and creep strains within the solder joint are
evaluated during the course of the 24 h power-on case. Figure 25
details the creep shear strains at 1 s and 6 h in the AuSn and SnBi
solder joints. A number of trends are evident. The first is that the
creep occurs almost instantly in the SnBi solder joints while the
AuSn solder joints’ creep strain develops rather slowly. The magnitude of the creep shear strain is significantly lower in the AuSn
solder joints than that in the SnBi solder joints. The dramatically
lower creep strain value in the AuSn solder alloy, when compared
with that in the SnBi solder joints, is particularly evident. Thus,
from solder joint reliability points of view, AuSn provides longer
thermal fatigue life.
Figure 25 also depicts the time-history of the shear stress at the
edge of the AlGaAs pad at the midthickness location. This stress
is primarily due to the global (GaAs chip and Si substrate) and
local (AlGaAs pad and the solder joint) thermal expansion mismatches. The pad shear stresses associated with the stiff and
creep-resistant AuSn solder are relatively high and unabated
through the 24 h period. The SnBi alloy has a significantly greater
creep rate than the AuSn alloy and this results in pad stresses that
rapidly decrease during the course of the analysis. The consideration of the solder joint influence on the AlGaAs pad stresses suggests that the SnBi alloy may be a better lead-free choice than the
AuSn alloy.
codes such as ABAQUS and ANSYS can take this form of constitutive
equation.
3.3.1 Wises Two-Power Creep Constitutive Equation for
Sn3.5Ag and Sn4Ag0.5Cu Solder Alloys. The creep data of
Sn3.5Ag and Sn4Ag0.5Cu bulk solders at different loadings and
temperatures have been obtained by Wises et al. [59–62] and are
shown in Fig. 26. The constants, E, A1, A2, rn, n1, n2, Q1, Q2, and
R for Eq. (42) have also been obtained by curve fitting the data
[59–62] and shown in Table 5.
3.3.2 Example on Using the Wises Two-Power Creep Constitutive Equation for Sn4Ag0.5Cu. Fan et al. [56] used the similar
two-power creep equation (Table 5) to perform finite element
analysis of a flip-chip BGA package on PCB as shown in Fig. 27.
It can be seen from the quarter model (the upper drawing) that
half of the solder joints under the chip shadow region have a
refined mesh pattern and the rest of the solder joints are modeled
with a relatively coarse mesh. The refined mesh pattern is shown
in the lower left-hand side of Fig. 27.
A global/local modeling is also adopted in Ref. [56] and shown
in the lower right-hand side of Fig. 27. It can be seen that the size
of the local model is equal to one solder ball pitch. The temperature cycle profile is 25 ! 100 C with dwell time at each
extreme ¼ 15 min and up/down ramp time ¼ 8 min.
The accumulated equivalent creep strain (CEEQ) per cycle for
the fine mesh full model and the global/local model are shown in
Fig. 28. It can be seen that the average value difference between
these two models is within 1.5%. The maximum value difference
between these two models is up to 7%. These values are calculated at the solder joints under the chip corners. For other solder
Journal of Electronic Packaging
joints underneath the chip shadow, the maximum value difference
can be as high as 20%.
The peak von Mises stress per cycle (which occurs at the beginning of low temperature dwell) for the fine mesh full model and
the global/local model are shown in Fig. 28. It can be seen that the
average value difference between these two models is within
1.5%. The maximum value difference between these two models
is 5%.
3.4 Garofalo Hyperbolic Sine Creep. Garofalo–Arrhenius
creep constitutive equation is expressed by [90]
Table 4 Parameters in the Norton power creep constitutive
equation for Au20Sn, Sn58Bi, Sn3.8Ag0.7Cu, and Sn3.8Ag0.7Cu0.03Ce solder alloys
e_ ¼ Arn
Q
RT
Au20Sn [6,107,108]
Sn58Bi [6,107,108]
Sn3.8Ag0.7Cu [49]
Sn3.8Ag0.7Cu0.03Ce [49]
A
n
Q
1.3977 1021
9.82 1024
1.5 109
6.2 1011
2.55
4.05
8.2
8
9516
8483
8540
9622
R is the Boltzmann’s constant ¼ 7.617 105 eV/K.
T (Kelvin), e_ (1/s).
For Au20Sn and Sn58Bi, r is in Pa.
For Sn3.8Ag0.7Cu and Sn3.8Ag0.7Cu0.03Ce, r is in MPa.
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Fig. 22 (a) Creep curve. (b) Creep curves with constant temperature and various stress. (c) Stress versus creep strain rate for
various temperature. (d) Stress versus creep strain rate at constant temperature.
dc
G
s n
Q
¼C
sinh x
exp dt
H
G
kH
(43)
If the solder obeys the von Mises criterion [110], then Eq. (44)
can be rewritten as [111]
de
C4
C3
¼ C1 ½sinhðC2 rÞ exp (45)
dt
T
where the constants, A, B, n, and Q or C1, C2, C3, and C4 are determined by creep tests (curves) at various sets of constant stress and
temperature shown in Fig. 22. It should be noted that Eq. (45) is
exactly the same as the input form of the implicit creep model in
ANSYS and ABAQUS. In the above two Eqs. (44) and (45), r is the
effective normal stress; s is the shear stress; and de/dt is the effective normal creep strain rate.
3.4.2 Examples on Using Garofalo Hyperbolic Sine
Creep Constitutive Equation for Sn3.9Ag0.6Cu, Sn3.8Ag0.7Cu,
Sn4Ag0.5Cu, Sn3Ag0.5Cu, 100In, and Sn52In Solder Alloys.
Equation (45) has been used for a few lead-free solder joint studies. For example, Fig. 29 schematically shows a silicon chip PCB
assembly under consideration. The dimensions of the chip are:
9 9 0.51 mm. It has 121 peripheral pads (0.06 0.06 mm)
with a spacing of 0.1 mm. After wafer-level redistribution [10],
the pads (0.3 mm in diameter) are in an area-arrayed format with
0.75 mm pitch. Figure 29 also shows the microvia buildup PCB
assembly of the lead-free solder bumped wafer-level chip scale
package (WLCSP). It can be seen that the PCB is 1.575 mm thick
and is made of fiber glass-4 epoxy glass. The copper pad thickness
is 0.0178 mm. The diameters of the microvia are varying from
0.1 mm to 0.15 mm (Fig. 30). The thickness of the electroplated
copper microvia is 0.025 mm. The thickness of the buildup resin
is about 0.125 mm. The solder joint height is 0.1524 mm and is
made of lead-free (96.6Sn3.5Ag) solder alloy. The temperature
boundary condition is shown in Fig. 29, which is a 60-minute
Fig. 23 Finite element modeling of a VCSEL assembly with lead-free solder joints, GaAs chip, and silicon substrate
020803-18 / Vol. 143, JUNE 2021
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where c is the creep shear strain, dc/dt is the creep shear strain rate, t
is the time, C is a material constant, G is the modulus, H is the absolute temperature (Kelvin), x defines the stress level at which the
power law stress dependence breaks down, s is the shear stress, n is
the stress exponent, Q is the activation energy for a specific diffusion
mechanism (for example, dislocation diffusion, solute diffusion, lattice self-diffusion, and grain boundary diffusion), and k is the
Boltzmann’s constant (7.617 105eV/oK). Equation (43) can be
rearranged by lumping certain coefficients and expressed as [109]
n
dc
s
Q
¼ A sinh
(44)
exp dt
B
kT
3.4.1 Garofalo Hyperbolic Sine Creep Constitutive Equation for Sn3.5Ag, Sn3.9Ag0.6Cu, Sn3.8Ag0.7Cu/Sn3.5Ag0.5Cu/
Sn3.5Ag0.75Cu, Sn4Ag0.5Cu, Sn3Ag0.5Cu, Sn(3.5-3.9)Ag(0.50.8) Cu, 100In, Sn52In, Au20Sn, and Sn3.8Ag0.7Cu0.03Ce
Solder Alloys. For Sn3.5Ag [66,67], Sn3.9Ag0.6Cu [36],
Sn3.8Ag0.7Cu/Sn3.5Ag0.5Cu/Sn3.5Ag0.75Cu [72], Sn4Ag0.5Cu
[71], Sn3Ag 0.5Cu [74], Sn(3.5-3.9)Ag(0.5-0.8)Cu [89], 100In
[66,67], Sn52In [83,112], Au20Sn [70], and Sn3.8Ag0.7Cu0.03Ce
[103] solder alloys, the constants C1, C2, C3, and C4 of Eq. (45)
have been determined and are shown in Table 6.
The results are shown in Fig. 33 for the equivalent total strain
time-history and strain energy time-history. It can be seen that for
both strain and strain energy, the Sn3.9Ag0.6Cu solder yields
the lowest values comparing with the Sn3Ag0.5Cu and
Sn3.8Ag0.7Cu solders [42]. The maximum strain energy contours
and the maximum equivalent total strain contours of the
Sn3.9Ag0.6Cu solder joint subjected to thermal cycling are
occurred at the corner solder joint.
The use of Eq. (45) for Sn(3.5-3.9)Ag(0.5-0.8)Cu, Fig. 34, has
been given in Ref. [89] and the PBGA package is the same shown
in Fig. 11. Figure 35 shows the three-dimensional (3D) finite element model that captures the construction along a diagonal strip
from the 256-pin PBGA lead-free assembly’s geometric center to
a corner. Because of the midplane symmetry, the mesh actually
models a one-half strip (with one-half of a solder joint) using the
appropriate in-plane constraints placed on one symmetry plane.
Coupled in-plane translations are applied to the other symmetry
plane to produce a state of generalized plane strain. Using exclusively hexahedral solid elements, the model can capture the precise shape of the packages’ solder joints and potential distance to
Fig. 24 Heat transfer analysis and results of the VCSEL assembly
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cycle, 20 ! 110 C, with a 15-minute ramp at hot and cold, and
20-minute dwell at hot, and 10-minute dwell at cold.
The maximum stress and creep strain at the corner solder joint
at 588 s are shown in Fig. 31 [10]. It can be seen that the maximum stress is 19.6 MPa and the maximum creep strain is 0.07.
The critical location of the stress and strain is at the upper solder
joint corners between the chip and the bulk solder. The maximum
stress (62 MPa) and strain (0.011) at the most outward microvia at
588 s are shown in Fig. 32. The critical location of the stress and
strain is near the bottom corners of the microvia.
Recently, Depiver et al. [42] used Eq. (45) for Sn3.9Ag0.6Cu
solder [36], for Sn3.8Ag0.7Cu solder [72], and for Sn3Ag0.5Cu
solder [74] in their finite element analyses (with ANSYS) of the
structure shown in Fig. 32. It is a heterogeneous integration of
four chips assembled on a PCB using those three different leadfree solder joints [42] with an underfill. Because of double symmetries, only quarter of the structure is analyzed. The chip dimensions are 3 mm 3 mm 0.35 mm and the PCB dimensions are
5 mm 5 mm 1.6 mm. The temperature profile is 40 !
150 C with 15 C/min ramp and 600 s dwell.
chip and a silicon-based actuator chip. The silica chip contains
two intersecting arrays of waveguides, with trenches etched into
each cross point. The silicon chip contains a matching pattern of
electrically addressed resistive elements. These two chips are hermetically sealed together with the Sn52In solder as shown in
Fig. 39. The creep equation of 48 wt%Sn-52 wt%In solder has
been determined experimentally in Ref. [112] by the double shear
specimens method described in Chapter 7 of Ref. [1] and is given
in Ref. [83].
At the default state, the trenches, along with the rest of the
sealed space between the silica and silicon chips, are filled with a
liquid whose refractive index matches the waveguides and properties are suitable for bubble creation and control. Optical signals
passing along any guide on the silica chip simply pass on through.
However, by activating a resistive element on the silicon chip, a
bubble can be created at that cross point, so that total internal
reflection occurs at the side wall of the corresponding trench, and
switching is achieved.
The key elements of the photonic switch consist of the silica
chip, 48 wt%Sn-52 wt%In solder sealing ring, silicon chip,
100 wt%In solder die attachment, and molybdenum substrate.
This stack of elements is bolted down onto a very large and thick
aluminum cooling plate. Because of the very large thermal expansion mismatch among the silica chip (0.5 106/ C), Sn-In solder (28 106/ C), silicon chip (2.5 106/ C), In solder (32.1
106/oC), molybdenum substrate (4.8 106/ C), and aluminum plate (23.2 106/ C), the whole structure is subjected to a
very complicate state of stresses and strains when it is under shipping/storing/handling conditions.
The objective of this investigation is to determine the displacement of the silica and silicon chips, the shear strain time-history
of the 48 wt%Sn-52 wt%In sealing ring, and the thermal-fatigue
life of the solder sealing ring of the photonic switch. The
48 wt%Sn-52 wt%In and 100 wt%In solders are assumed to obey
the Garofalo–Arrhenius creep constitutive law, Eq. (45). The finite
element model is shown in Fig. 39 and the material properties are
Fig. 25 Creep shear strain time-history of the AuSn and SnBi solder joints. Shear stress time-history of the AuSn and SnBi
solder joints.
020803-20 / Vol. 143, JUNE 2021
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neutral point (DNP) effects while retaining significant computational efficiency over full octant models. ANSYS is the code
selected for the modeling and analyses.
The temperature profile to be imposed on the PBGA assembly
is: 0 ! 100 C. The cycle time is 40 min and the ramp-up, rampdown, dwell-at-hot, and dwell-at-cold are each 10 min. Five thermal cycles are executed. The analysis is performed with the
appropriate constitutive relations, Eq. (45) by Lau et al. [36], by
Schubert et al. [72], and by Lau and Dauksher [89].
Figure 36 shows the shear stress versus creep shear strain hysteresis loops at the critical solder joint for the fifth thermal cycles.
It can be seen that: (1) the area within the loop (strain energy density per cycle) predicted by Schubert et al. [72] is larger than that
by Lau et. al. [36]; and (2) the area predicted by Eq. (45) with
material model Lau and Dauksher [89] is between those by
Schubert et al. [72] and Lau et al. [36].
Figure 37 shows a fan-out wafer-level package (13.42 mm 13.42 mm) with a very large silicon chip (10 mm 10 mm),
which is lead-free (Sn3Ag0.5Cu) solder balled on a PCB as shown
in Fig. 2 [18–22]. The finite element model is shown in Fig. 37
and the modeling technique is the same as that for the 256-pin
PBGA assembly. The constitutive equation of the solder is
Eq. (45) with material model [89]. The temperature profile is the
same as in Ref. [18].
The maximum Mises stress and accumulated creep strain occur
at the solder joints near the chip corner and the package corner as
shown in Fig. 38. Their magnitude in the die corner solder joint is
slightly larger than that in the package corner solder joint. The
failure is at the interface between the bottom of the package and
the bulk solder. Thus, any failure should occur at this location.
This correlates very well with thermal cycling test failure mode as
shown in Fig. 4. The maximum Mises stress occurs at 40 C during the thermal cycling.
Figure 39 shows the photograph of a fully assembled (fiberattached) 32 32 all-optical device developed by Agilent [83].
Basically, it consists of a silica-based planar light wave circuit
given in Ref. [83]. The temperature boundary condition is: –40 !
þ85 C, with 15 min ramp-up, 15 min hold at hot, 15 min rampdown, and 15 min hold at cold. Five full cycles are executed [83].
Figure 40(a) shows the time-history maximum (center) deflection of the silica and silicon chips. It can be seen that: (1) they are
in-phase with the applied temperature profile; (2) the maximum
deflection of the silicon chip is larger than that of the silica chip;
and (3) the gap between the silica chip and the silicon chip is not
closed since the original gap between these two chips is 5 lm.
The shear strain history at the solder sealing ring of the photonic switch is shown in Fig. 40(b). It can be seen that: (1) the
creep strain is stabilized at the third thermal cycles; and (2) the
shear creep strain range at the solder sealing ring at the third
thermal cycle is 0.042. This small magnitude of creep strain per
cycle will not create solder sealing ring reliability problem [83].
3.5 Anand Viscoplasticity. The Anand viscoplasticity model
[93] is an internal variable-based model in which the inelastic
behavior including temperature- and rate-dependent, and rateindependent plasticity effects are unified. The Anand flow equation which governs the inelastic strain e has the following form
[93]:
1=m
de
nr
Q
¼ A sinh
exp dt
s
RT
(46)
Table 5 Parameters in the Wises two-power creep constitutive equation for Sn3.5Ag and Sn4Ag0.5Cu solder alloys
e_ ¼
n1
n2
r
r
Q1
r
Q2
þ A1
exp exp þ A2
E
rn
rn
RT
RT
E (GPa)
A1 (1/s)
A2 (1/s)
rn (MPa)
n1
n2
Q1 (kJ/mol)
Q2 (kJ/mol)
R (J/mol K)
Wises, bulk (Sn3.5Ag) [59–62]
Wises, bulk (Sn4Ag0.5Cu) [59–62]
Fan, PCB (Sn4Ag0.5Cu) [56]
52.71–0.0677T (K)
7 104
2 104
1
3
11
46.8
93.1
8.314462
62.24–0.075T (K)
1 106
1 1012
1
3
12
34.6
61.1
8.314462
59.53–0.0677T (K)
4 107
1 1012
1
3
12
26.8
61.4
8.314462
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Fig. 26 Wises’ two-power creep. Wises’ two-power creep data for Sn3.5Ag bulk-specimen and for Sn4Ag0.5Cu bulkspecimen.
where de/dt is the inelastic strain rate, A is the pre-exponential factor, Q is the activation energy, R is the universal gas constant
(8.314 JK1mol1), T is the absolute temperature (Kelvin), n is
the multiplier of stress, r is the equivalent stress, m is strain rate
sensitivity. The evolution equation which defines an internal variable s of the model and its saturation value is
ds
B de
¼ h0 ðjBjÞa
(47)
dt
jBj dt
where
s
s
and
n
dep =dt
Q
s ¼ ^s
exp
A
RT
where h0 is the hardening/softening constant, a is the strain rate
sensitivity of hardening/softening. The quantity s* represents a
saturation value of deformation resistances. s^ is a coefficient, and
n is the strain rate sensitivity for the saturation value of
Fig. 27 Global/local and full models for flip chip with underfill
on package substrate and then lead-free solder joints on PCB
Fig. 28 CEEQ per cycle from global/local and full models. Mises stress from global/local and full models.
Table 6 Parameters in the Garofalo hyperbolic sine creep constitutive equation for Sn3.5Ag, Sn3.9Ag0.6Cu, Sn3.8Ag0.7Cu/
Sn3.5Ag0.5Cu/Sn3.5Ag0.75Cu, Sn4Ag0.5Cu, Sn3Ag0.5Cu, Sn(3.5-3.9)Ag(0.5-0.8)Cu, 100In, Sn52In, Au20Sn, and Sn3.8Ag0.7Cu0.03Ce solder alloys
de
C4
¼ C1 ½sinhðC2 rÞ C3 exp dt
T
Sn3.5Ag [66,67]
Sn3.9Ag0.6Cu [36]
Sn3.8Ag0.7Cu, Sn3.5Ag0.5Cu, Sn3.5Ag0.75Cu [72]
Sn4Ag0.5Cu [71]
Sn3Ag0.5Cu [74]
Sn(3.5–3.9)Ag(0.5–0.8)Cu [89]
100ln [66,67]
Sn52ln [83,112]
Au20Sn [70]
Sn3.8Ag0.7Cu0.03Ce [103]
C1
C2
C3
C4
18(553-T)/T
441000
277,984
0.17
2631
500,000
40647(593-T)/T
2.54 1011(593–T)/T
4.62 1015
284,000
1/(6386–11.55T)
0.005
0.02447
0.14
0.0453
0.01
1/(274–0.47T)
1/(5235–8.65T)
2 105
0.024
5.5
4.2
6.41
4.2
5
5
5
3.11
2.07
6.1
5802
5412
6500
6875
7096
5800
8356
9705
12268
6400
For Sn3.5Ag, 100ln, and Sn52ln, r is in psi. For all other solder alloys, r is in MPa. For all solder alloys, de=dt is in 1/s, and T is in Kelvin.
020803-22 / Vol. 143, JUNE 2021
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B¼1
deformation resistance, respectively. The evolution equation has
an extra initial condition of s(0) ¼ s0, where s0 is the initial value
of s at initial time t ¼ 0. The Anand model does not have an
explicit yield criterion or a loading-unloading criterion and viscoplastic flow occurs for any nonzero stress.
There are a total of nine constants (parameters) of the Anand
equation (model), namely A, Q, n, m, s; n, h0, a, and s0, and their
definition are tabulated in Table 7 for easy reference. These
parameters can be taken as input in ANSYS and ABAQUS and determined through fitting to the experimental data of solders. Most
researchers use the stress–strain curves (data) with various strain
rates and temperatures of solders. However, some also use the
creep curves (data) with various stresses and temperatures of
solders.
3.5.1 Anand Viscoplasticity Constitutive Equation for
Sn3.5Ag, Sn3Ag0.5Cu, and Au20Sn Solder Alloys Based on Creep
Curves Data. Based on Darveaux and Banerji’s Sn3.5Ag creep
curves data [66,67], in 2001, Wang et al. [102] determined the
nine parameters of the Anand constitutive equation, which are
shown in Table 7. For Sn3Ag0.5Cu, in 2012, Motalab et al. [97]
determined the parameters of the Anand constitutive equation
based on their creep data as shown in Table 7. In 2017, based on
his own creep curves data of Au20Sn, Jin [100] determined the
nine constants of the Anand constitutive equation, which are also
shown in Table 7.
Fig. 30 Dimensions of the microvia and solder joint
Journal of Electronic Packaging
3.5.2 Examples on Using Anand Viscoplasticity Constitutive
Equation for Sn3.5Ag Based on Creep Curves Data. By using the
Anand viscoplasticity constitutive equation for Sn3.5Ag developed by Wang et al. [102] and Hamdani et al. [101] performed the
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Fig. 29 WLCSP on PCB with microvias. Temperature condition for simulation.
finite element analysis of a 256-pin PQFP package with 0.5 mm
pitch gull-wing leads. Figure 41 shows their global model and
submodel with ANSYS. Young’s modulus (GPa), Poisson’s ratio,
and thermal expansion coefficient (ppm/K) of the Sn3.5Ag, PCB,
epoxy and Cu-lead, are, respectively, 51.3, 0.3, and 20; 17, 0.3,
and 18; 17, 0.2, and 22; and 115, 0.31, and 17. The temperature
boundary condition is also shown in Fig. 41. The inelastic normal
strain contours are shown in Fig. 41. It can be seen that the maximum location occurs near the intersection of the bended (corner)
gull-wing lead and the tip of the solder fillet. Thus, any failure
should occur at this location.
Figure 42 shows a high-power lateral insulated-gate bipolar
transistor for light-emitting diode (LED) applications proposed by
Bailey et al. [113]. It can be seen that for the vertical device, the
low-voltage terminals are placed on the front side of the die while
the high voltage terminal (800 V) is placed on the opposite side of
the die. The lateral device with the same power level: all terminals
are placed on the front side of the die. The layout of the insulatedgate bipolar transistor (IGBT) package in side view is shown in
the top of Fig. 43 and the layer structures of the device is shown
in the bottom of Fig. 43. It can be seen that the length and width
of the device are 818 lm and 672 lm, respectively. The 3D lateral
insulated-gate bipolar transistor device is with Sn3.5Ag solder
balls (diameter ¼ 150 lm), which is shown in the bottom of
Fig. 42 and the top of Fig. 43. Underfill is used to prolong the
solder joint thermal fatigue life. The temperature boundary
conditions are ramp time ¼ 3 min and dwell time ¼ 15 min, and
25 ! 125 C. The SOLID185 of ANSYS has been used [113]. The
constitutive equation of the Sn3.5Ag solder is given by Wang
et al. [102], Table 7.
020803-24 / Vol. 143, JUNE 2021
Fig. 32 Heterogeneous integration of four chips on a PCB
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Fig. 31 Stress and strain contours at the corner solder joint and microvia
The accumulated inelastic strain contours at the third cycle in
the solder joints are shown in Fig. 43 [113]. It can be seen that the
maximum magnitude occurs at the corner solder joint with the
largest DNP.
3.5.3 Anand Viscoplasticity Constitutive Equation for Sn3.5Ag
With Temperature and Strain Rate-Dependent Parameters Based on
Stress–Strain Curves. By means of the stress–strain curves with
different temperatures and strain rates such as those shown in
Fig. 34 Stress versus creep strain rate curves (at 225 C,
50 C, and 125 C)
Journal of Electronic Packaging
Fig. 35 3D finite element modeling of the 256-pin PBGA PCB
assembly
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Fig. 33 Creep strain time-history for SAC305, SAC387, and SAC396 solder joints. Creep strain
energy time-history for SAC305, SAC387, and SAC396 solder joints.
Fig. 38 (a) Maximum Mises stress in the solder joints. (b) Maximum accumulated creep strain in the solder joints.
s0 ¼ 0:0673T þ 28:6
(48)
2
Fig. 44(a) (various temperatures and strain rate ¼ 0.02/s) and
Fig. 44(b) (various strain rates and temperature ¼ 398 K), Chen
et al. [51] obtained the nine parameters of the Anand constitutive
equation for the Sn3.5Ag solder and are shown in Table 8. It is
noted that the s0 is temperature dependent and the h0 is temperature and strain rate dependent
h0 ¼ 90940 þ 961T 0:956T 2 3260582_e þ 24976816ðe_ Þ
(49)
where T is in Kelvin and e_ is strain rate (1/s).
3.5.4 Examples on Using Anand Viscoplasticity Constitutive
Equation for Sn3.5Ag Based on Stress–Strain Curves. Deshpande
et al. [94] used some of the parameters in the Anand model for
Fig. 37 Finite element model of the fan-out package (of a 10 mm 3 10 mm chip) PCB assembly
020803-26 / Vol. 143, JUNE 2021
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Fig. 36 The fifth shear stress—creep shear strain hysteresis
loop of the critical solder joint. Creep strain energy density versus time curves.
Sn3.5Ag solder developed by Chen et al. [51] to analysis a PBGA
PCB assembly. The parameters given by Deshpande et al. [94] are
also shown in Table 8. It can be seen that the s0 and h0 are different from Chen et al.’s [51]. Deshpande used s0 ¼ 9.53, which is
for T ¼ 313oK in Eq. (48), and h0 ¼ 27782.
The global structure (top) and the meshed model with octant
symmetry (bottom) are shown in Fig. 45 [94]. The temperature
boundary conditions are 25 ! 125 C at 10 C/min. The maximum equivalent inelastic strain contours and the equivalent stress
contours occur at the corner solder joint and are shown in Fig. 45.
It can be seen that at the corner solder joint, the critical location is
at the interface between the PBGA substrate and the bulk solder.
Thus, any failure should occur at this location. The second critical
location is at the interface between the bulk solder and PCB. This
could be the secondary failure candidate.
Ramachandran et al. [68] used some of the parameters in the
Anand model for Sn3.5Ag solder developed by Chen et al. [51] to
analysis a WLCSP as shown in Fig. 46. The parameters given by
Ramchandran et al. [68] are also shown in Table 8. It can be seen
that the h0 is different from Chen et al.’s [51]. Instead of temperature and strain rate dependent, Ramachandran used h0 ¼ 27782.
Figure 46 shows the two-dimensional (2D) finite element model
of the WLCSP (14 mm 14 mm) PCB assembly with Sn3.5Ag solder joints [68]. The temperature boundary conditions are JEDEC
standard G with ramping rates of 11 C, 16.5 C, and 33 C per
minute and a dwell time of 10 min. The maximum accumulated
inelastic strain occurs at the corner solder joint (the maximum DNP).
The critical location is near the interface between the WLCSP and
the bulk solder as shown in Fig. 46. This failure mode and location
agree very well with thermal cycling results as shown in Fig. 46.
Journal of Electronic Packaging
Fig. 40 (a) Displacement of the SiO2 and Si chips versus time.
(b) Shear strain time-history at the Sn52In sealing ring.
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Fig. 39 Full assembled (fiber-attached) 32 3 32 all-optical device developed by Agilent. The silica-based planar light wave circuit chip and the silicon-based actuator chip are connected with a Sn52In sealing ring.
Table 7 Parameters in Anand viscoplasticity constitutive equation for Sn3.5Ag, Sn3Ag0.5Cu, and Au20An solder alloys based on
creep curves with various stresses and temperatures
"
!#
!
de
fr 1=m
Q
¼ A sin h
exp dt
s
RT
B¼1
Parameters
Definition in Anand’s model
Pre-exponential factor
Activation energy/universal gas constant
Stress multiplier
Strain rate sensitivity of stress
Coefficient for deformation resistance saturation value
Strain rate sensitivity of saturation value
Hardening constant
Strain rate sensitivity of hardening/softening
Initial value deformation resistance
3.5.5 Anand Viscoplasticity Constitutive Equation for
Sn3.8Ag0.7Cu, Sn3.8Ag0.7Cu0.03Ce, and Sn3.8Ag0.7Cu0.1Al
Solder Alloys Based on Stress–Strain Curves Data. For
Sn3.8Ag0.7Cu and Sn3.8Ag0.7Cu0.03Ce solders, the nine parameters of the Anand viscoplasticity constitutive equations have been
obtained by Zhang et al. [103] by fitting the stress–strain curves at
different temperatures and strain rates of these solders. Figure 47(a)
shows the stress–strain curves at 55 C, 25 C, 25 C, 75 C, and
Sn 3Ag [102]
4
2.23 10
8900
6
0.181
73.81
0.018
3321.15
1.82
39.09
Sn 3Ag 0.5 Cu [97]
Au20Sn [100]
3484
9096
4
0.2
26.4
0.01
144,000
1.9
18.07
69.53
5240
0.4
0.2598
27.11
0.0917
27,595
1.017
14.75
125 C, and at a strain rate ¼ 0.01/s for the Sn3.8Ag0.7Cu solder,
while Fig. 47(b) is for the 3.8Ag0.7Cu0.1Ce solder. The Anand
parameters for both solders are shown in Table 8.
For Sn3.8Ag0.7Cu-nano-Al solder, the nine parameters of the
Anand viscoplasticity constitutive equations have been obtained
by Zhang et al. [104]. They performed a series of uni-axial tensile
tests of the SnAgCu0.1Al solder with a number of different
strain rates (from 1.0 104 to 1.0 102 1/s) and temperature
Fig. 41 Global and local finite element models of a 256-pin PQFP with Sn3.5Ag solder joints. Strain contours at the lead-free
solder joint.
020803-28 / Vol. 143, JUNE 2021
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A (1/s)
Q/R ( K)
n
m
s^ ðMPaÞ
n
ho (MPa)
a
s0 (MPa)
s
s
(
)
ds
B de
¼ h0 ðjBjÞa
dt
jBj dt
2
!3n
dep =dt
Q
exp
s ¼ s^4
5
A
RT
conditions (55, 25, 25, 75, and 125 C). The results are shown
in Table 8.
3.5.6 Example on Using Anand Viscoplasticity Constitutive
Equation for Sn3.8Ag0.7Cu and Sn3.8Ag0.7Cu0.03Ce Solder
Alloys Based on Stress–Strain Curves Data. Figure 48 shows the
finite element model of one quarter of a PQFP PCB assembly with
lead-free (Sn3.8Ag0.7Cu or Sn3.8Ag0.7Cu0.03Ce) solder joins
[103]. The model is subjected to a temperature condition
according to MIL-STD-883 (55 ! 125 C), one-hour cycle with
ramp-up, ramp-down, dwell-at-hot, and dwell-at-cold ¼ 15 min.
The maximum equivalent (Mises) stress (MPa) time-history
and the equivalent inelastic strain occur at the corner solder
(SnAgCu and SnAgCuCe) joint and are shown in Figs. 49(a) and
49(b), respectively. It can be seen from Fig. 49(a) that the equivalent stress range with the SnAgCuCe solder is smaller than that
with the SnAgCu solder. Also, it can be seen from Fig. 49(b) that
the equivalent inelastic strain with the SnAgCuCe solder is
slightly smaller than that with the SnAgCu solder [103].
Fig. 43 Side view of IGBT and the layers of the device. Accumulated inelastic strain contours in the solder
joints.
Journal of Electronic Packaging
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Fig. 42 IGBT for LED applications
3.5.7 Anand Viscoplasticity Constitutive Equation for
Sn1Ag0.5Cu, Sn2Ag0.5Cu, Sn3Ag0.5Cu, and Sn4Ag0.5Cu Solders
After Extreme Aging. For SAC105, SAC205, SAC305, and
SAC405 solders, the nine parameters of the Anand viscoplasticity
constitutive equations have been determined by Basit et al. [96]
for four different cooling profiles. These included water quenched
(WQ), reflowed (RF), RF þ 6 months of aging at 100 C, and
RF þ 12 months of aging at 100 C. For each condition, a set of
stress–strain tests performed at three different strain rates (103,
104, and 105 1/s) and five different temperatures (25, 50, 75,
100, and 125 C). The results for SAC305 are shown in Table 9.
For SAC105, SAC205, and SAC405, please read [96].
For WQ cooling, all the solders considered in Ref. [96], the
Anand parameters (s0, h0, and s^Þ are at the “upper bound” of what
is possible as far as stiffness and strength. For long (extreme)
aging such as RF þ 12 months, the Anand parameters (s0, h0,
and s^Þ are at the “lower bound” of what is possible for all the
solders.
3.6 Thermal-Fatigue Life Prediction. There are many
thermal-fatigue life prediction models of solder joints in the literature, e.g., [83,85,88,114–156]. A couple of very simple models
are shown below:
Table 8 Parameters in Anand viscoplasticity constitutive equation for Sn3.5Ag, Sn3.8Ag0.7Cu, Sn3.8Ag0.7Cu0.03Ce, and
Sn3.8Ag0.7Cu0.1Al solder alloys based on stress–strain curves with various strain rates and temperatures
Material constant
A (1/s)
Q/R ( K)
n
m
s^ ðMPaÞ
n
ho (MPa)
a
so (MPa)
Sn3.5 Ag [51]
Sn3.5Ag [94]
Sn3.5Ag [68]
Sn3.8Ag0.7Cu [103]
Sn3.8Ag0.7Cu0.03Ce [103]
Sn3.8Ag0.7Cu0.1Al [104]
177,016
10,279
7
0.207
52.4
0.0177
b
1.6
X
177,016
10,279
7
0.207
52.4
0.0177
27782
1.6
9.53
177,016
10,279
7
0.207
52.4
0.0177
27782
1.6
u
24,300
8710
5.8
0.183
65.3
0.019
3541.2
1.9
39.5
21,200
8026
5
0.130
57.6
0.0175
4352.6
2.3
28.5
22,100
8015
4.1
0.150
59.0
0.0154
4132
2.0
27.0
b ¼ 90940 þ 961 T – 0.956T2 – 3260582_e þ 24976816ð_e Þ2 .
X ¼ 0.0673 T þ 28.6.
u ¼ 0.0673 T þ 28.6.
T is in Kelvin and e_ is the strain rate (1/s).
020803-30 / Vol. 143, JUNE 2021
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Fig. 44 (a) Stress–strain curves with various temperatures and strain rate 5 0.02/s of Sn3.5Ag. (b) Stress–strain curves with
various strain rates and temperature 5 398 K of Sn3.5Ag.
Nf ¼
X
aj ½DW
bj
(50)
j
and
Nf ¼
X
"P
aj
DWi
iP
j
i
x Vi
Vi
#bj
(51)
4
Summary and Recommendations
Some important results and recommendations are summarized
in the follows:
Fig. 45 (a) PBGA with Sn3.5Ag solder joints on PCB. (b) Maximum equivalent stress contours at corner solder joint. (c) Maximum equivalent inelastic strain contours at corner solder joint.
Journal of Electronic Packaging
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where Nf is the thermal fatigue life, and aj and bj are constants to
be determined by experiments (usually isothermal fatigues) for a
specific component/package and solder joint. DWi is the creep (or
inelastic) strain energy density (or accumulated equivalent creep
strain) per cycle in the ith element determined from finite element
simulations with the above constitutive equations. Vi is the volume of that ith element.
The value of DWi depends on the accuracy of material properties of the structure. These include the solder joint, package, chip,
PCB, etc.
The value of DWi also depends on the construction of the finite
element model. This includes finer mesh to capture the
stress–strain concentration areas.
In the literature, many authors called Nf the reliability (number
of thermal cycle) of solder joint. Actually, it should be emphasized that the reliability (Nf ) obtained from DFR and Eqs. (50) or
(51) is not the same as the reliability (probability) obtained from
reliability tests. For example, the life (number of cycles-to-failure)
of the solder joints from reliability tests depends on the percent
failed (or survived). Statistically, there are an infinite number of
possible lives, e.g., the characteristic life is corresponding 63.2%
failed (or 32.8% survived). On the other hand, the best one can do
from DFR is to predict a (one) life of the solder joint for a given
material and geometry of the structure, and given boundary condition, and from a thermal-fatigue life prediction model.
Many authors compare the reliability, Nf (number of thermal
cycle) to the cycle-to-failure at 1% failure from the reliability test.
If they find the value of Nf is too big, then they compare to the
cycle-to-failure at 50% or 63.2% failures from the reliability test.
Actually, Nf and the reliability from test are two different things
and cannot be compared.
One more thing, many authors use finite element simulation to
determine the maximum value of DW and then substitute into
Eq. (50) and calculate the Nf . It should be emphasized that the calculated maximum value is acting only at one point in an element
(usually near the corner) of the solder joint. The way what they do
is (unknowingly) presuming that DW is uniformly distributed
through the whole volume of the solder joint. There is another
thing, even some authors do not assume the uniformity of the DW,
i.e., use Eq. (51), they still have to assume a crack propagation
path of the solder joint to calculate the Nf.
Finally, it should be pointed out that all the low-cycle thermalfatigue life prediction models for lead-free solder joints in the literatures have not been experimentally (satisfactorily) verified.
More works should be done in this area.
Reliability engineering consists of three major tasks, namely
DFR (design for reliability), reliability testing and data analysis, and failure analysis.
Reliability of an interconnect (e.g., solder joint) of a particular package in an electronic product is defined as the probability that the interconnect will perform its intended function
for a specified period of time under a given operating condition without failure.
Fig. 47 (a) Stress–strain curves at various temperatures
(strain rate 5 0.01/s) for Sn3.8Ag0.7Cu solder. (b) Stress–strain
curves at various temperatures (strain rate 5 0.01/s) for
Sn3.8Ag0.7Cu0.03Ce solder.
020803-32 / Vol. 143, JUNE 2021
Fig. 48 Finite element model of a (quarter) PQFP package PCB
assembly
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Fig. 46 WLCSP on a PCB with Sn3.5Ag solder joints. 2D finite element model of the WLCSP PCB assembly. Maximum
stress–strain occurs at the solder between the WLCSP and the bulk solder. The failure mode from the thermal cycling test.
Interconnect (e.g., solder joint) reliability should be determined by reliability tests. The objective of reliability tests is
to obtain failures (the more, the better) and to best fit the failure data to estimate the parameters of a chosen probability
distribution, F(x). Once F(x) is estimated, the reliability,
failure rate, cumulative failure rate, average failure rate,
mean-time-to-failure, etc. of the interconnect are readily
determined.
The life distribution, F(x), is package/component dependent.
Actually, it is also affected by the chip size, solder alloy,
type of pastes, PCB thickness, PCB material, number of copper layer in PCB, reflow condition, solder joint volume,
voids in solder joint, test condition, continuity measurement,
number of measurement during each cycle, data acquisition
system, failure criterions, data analysis method, etc.
Examples on using the Weibull and Lognormal life distributions for lead-free solder joints under thermal-cycling and
drop tests have been provided.
True Weibull slope, true characteristic life, and true mean
life have been briefly mentioned.
All the papers in the literature are dealing with liner acceleration, i.e., xo ¼ axT , or No ¼ aNT , where a is the linear acceleration factor. Other accelerations and factors have to be
investigated.
Table 9 Parameters in Anand viscoplasticity constitutive equation for Sn3.8Ag0.7Cu after extreme aging
Acknowledgment
Sn3Ag0.5Cu (SAC305) [68]
No aging
Anand parameters
A (1/s)
Q/R ( K)
n
m
s^ (MPa)
n
ho (MPa)
a
so (MPa)
WQ
6 months aging 12 months aging
RF
2800
3501
9320
9320
4
4
0.29
0.25
44.67
30.2
0.012
0.01
186,000 180,000
1.72
1.78
32.2
21.0
Journal of Electronic Packaging
RF
RF
4110
9320
4
0.18
21.9
0.0016
77,540
2.05
5.8
4210
9320
4
0.18
21.4
0.001
73,708
2.06
5.4
The author would like to thank his coauthors for the materials
presented in this paper.
References
[1] Lau, J. H., (Ed.), 1991, Solder Joint Reliability: Theory and Applications, Van
Nostrand Reinhold, New York.
[2] Lau, J. H., 1990, Design for Reliability, Reliability Testing and Data Analysis,
and Failure Analysis of Solder Joints, NEPCON West Workshops, Anaheim,
CA.
[3] Lau, J. H., Gratalo, K., Schneider, E., Marcotte, T., and Baker, T., 1996,
“Solder Joint Reliability of Large Plastic Ball Grid Array Assemblies,” J. Inst.
Interconnect. Technol., 22(1), pp. 27–32.
[4] Lau, J. H., Schneider, E., and Baker, T., 1996, “Shock and Vibration of Solder
Bumped Flip Chip on Organic Coated Copper Boards,” ASME J. Electron.
Packag., 118(2), pp. 101–104.
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Fig. 49 (a) Maximum equivalent (Mises) stress (MPa) timehistory at the corner solder joint. (b) Maximum equivalent
inelastic strain time-history at the corner solder joint.
Linear acceleration factors for various lead-free solder alloys
based on: (a) frequency and maximum temperature, (b) dwell
time and maximum temperature, and (c) frequency and mean
temperature have been systemically presented.
The advantages of DFR are to: (a) eliminate trial-and-error
of reliability tests, (b) provide insight into the physical,
chemical, electrical, mechanical, and thermal behaviors of
the solder joints, e.g., failure location and failure mode, and
(c) provide comparison between material properties and
structural geometries of package, PCB, and solder joints.
The most important property of DFR of solder joints is the
constitutive equation of the solder alloy.
Norton power creep constitutive equations and examples for
Au20Sn, Sn58Bi, Sn3.8Ag0.7Cu, and Sn3.8Ag0.7Cu0.03Ce
have been provided.
Wises two power creep constitutive equations and examples
for Sn3.5Ag and Sn4Ag0.5Cu have been provided.
Garofalo hyperbolic sine creep constitutive equations and
examples for Sn3.5Ag, Sn3Ag0.5Cu, Sn3.9Ag0.6Cu,
Sn3.8Ag0.7Cu,
Sn3.5Ag0.5Cu,
Sn3.5Ag0.75Cu,
Sn4Ag0.5Cu, Sn(3.5–3.9)Ag(0.5–0.8)Cu, 100In, Sn52In,
Sn3.8Ag0.7Cu0.03Ce, and Au20Sn have been provided.
Anand viscoplasticity constitutive equations and examples
for Sn3.5Ag, Sn3Ag0.5Cu, Sn3.8Ag0.7Cu, Sn3.8Ag0.7CuCe, Sn3.8Ag0.7CuAl, Au20Sn, Sn3.5Ag with temperature
and strain rate-dependent parameters, and Sn1Ag0.5Cu,
Sn2Ag0.5Cu, Sn3Ag0.5Cu, and Sn4Ag0.5Cu after extreme
aging have been provided.
The above four types of constitutive equations can be input
into the commercial computer simulation codes such as
ANSYS and ABAQUS.
The constants ai and bi in Eqs. (50) and (51) have to be
experimentally determined for a specific component/package
and solder alloy. One method is by isothermal fatigue test.
However, how to relate/correlate the isothermal fatigue to
the low-cycle thermal fatigue is a key question need to be
answered. More research works need to be done in this area.
The calculated value of DWi depends on the accuracy of
material properties of the structures. These include the solder
joint, package, PCB, etc.
The accuracy of the calculated DWi also depends on the construction of the finite element model. This includes the finer
meshes for the stress–strain concentration areas of the solder
joints.
The reliability, Nf (number of thermal cycle) obtained from
DFR, e.g., Eqs. (50) or (51), is not the same as the reliability
(probability) obtained from reliability tests. They cannot be
compared.
In this study, there is not any intention to present/propose
thermal-fatigue life prediction models for the determination
of Nf (reliability) of lead-free solder joints through the DFR.
More new models and experimental works should be done in
this area.
020803-34 / Vol. 143, JUNE 2021
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