Trellis-type Sigma Delta Modulators
for Super Audio CD applications
P.J.A. Harpe
January 29, 2003
Contents
1 Introduction
5
2 Trellis architecture
7
1
2
3
Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
1.1
Standard Sigma Delta Modulator . . . . . . . . . . . . . . . .
7
1.2
Trellis Sigma Delta Modulator . . . . . . . . . . . . . . . . .
8
1.3
Viterbi algorithm . . . . . . . . . . . . . . . . . . . . . . . . .
9
1.4
Initialization of the Trellis structure . . . . . . . . . . . . . .
11
1.5
Required resources . . . . . . . . . . . . . . . . . . . . . . . .
12
Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
2.1
StandardSDM function . . . . . . . . . . . . . . . . . . . . . .
13
2.2
TrellisSDM function . . . . . . . . . . . . . . . . . . . . . . .
14
2.3
CalculateTotalCosts function . . . . . . . . . . . . . . . . .
16
2.4
Path convergence problem . . . . . . . . . . . . . . . . . . . .
17
Simulation results
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
3.1
Signal to noise ratio . . . . . . . . . . . . . . . . . . . . . . .
18
3.2
Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
3.3
Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
3.4
Filter frequency . . . . . . . . . . . . . . . . . . . . . . . . . .
23
3.5
Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
CONTENTS
3
3 Efficient Trellis architecture
1
2
3
29
Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
1.1
Efficient Trellis Sigma Delta Modulator . . . . . . . . . . . .
29
1.2
Required resources . . . . . . . . . . . . . . . . . . . . . . . .
31
Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
2.1
EfficientTrellisSDM function . . . . . . . . . . . . . . . . .
32
2.2
Path convergence solution . . . . . . . . . . . . . . . . . . . .
34
Simulation results
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
3.1
Trellis versus efficient Trellis converter . . . . . . . . . . . . .
35
3.2
Signal to noise ratio and linearity . . . . . . . . . . . . . . . .
36
3.3
Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40
3.4
Filter frequency . . . . . . . . . . . . . . . . . . . . . . . . . .
40
4 Model for output noise spectral density
43
1
Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
2
Simulation results
45
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Future work
47
1
Invalid candidate removal . . . . . . . . . . . . . . . . . . . . . . . .
47
2
Noise shaping cost function . . . . . . . . . . . . . . . . . . . . . . .
49
6 Summary
53
7 Conclusions
55
Bibliography
57
Appendices
59
A dB SACD definition
61
B Path convergence example
63
C AES paper
65
4
CONTENTS
Chapter 1
Introduction
Since the introduction of Super Audio CD (SACD), 1-bit digital audio formats
attract a lot of attention. In case of SACD, the 1-bit digital information is sampled
at 2822400 Hz (64 times higher than on a normal CD), resulting in a very high
signal to noise ratio (typical well above 100 dB) and superior behaviour for input
signals with high-frequency components.
In a typical recording process for SACD, the music is converted to a multi-bit
digital representation first. Then, signal processing can be applied to edit the music
in the desired way. After that, the sample frequency is converted to the SACD
standard (2822400 Hz). The next step is to convert the multi-bit digital data to
the 1-bit format. The most often used technique for this conversion is Sigma Delta
Modulation (SDM).
Our main interest in the recording chain is the SDM. Although standard SDM
provides a good solution, recently several new SDM techniques have been published
like Trellis Noise-Shaping Conversion [1], time quantized frequency modulation [2]
and pre-correction [3]. One of their main purposes is to provide better linearity
compared to standard SDM. This paper investigates the possibilities and problems
of the Trellis technique when applied in the recording phase of a SACD.
In chapter two, an introduction to normal Sigma Delta Modulation and to the Trellis
architecture and its performance is given. A new, more efficient implementation, is
introduced in the third chapter. In the fourth chapter, a model for the noise power
spectrum at the output of Trellis converters is presented and verified.
1. INTRODUCTION
5
6
1. INTRODUCTION
Chapter 2
Trellis architecture
The Trellis architecture for the generation of 1-bit digital audio was introduced by
Kato [1]. The first paragraph gives a short introduction to this architecture, in accordance to Kato’s paper. The second paragraph covers the software implementation
for the Trellis architecture. In the last paragraph several simulation results are discussed.
1
1.1
Model
Standard Sigma Delta Modulator
x(t)
+
d(t)
-
H(z)
c(t)
Q
y(t)
z -1
Figure 2.1: A general model for a SDM.
Figure 2.1 shows a typical model for a 1-bit SDM. The digital multi-bit input signal
x(t) is converted to a single-bit output signal y(t). Signal d(t) is the error signal,
including noise and harmonic distortion. c(t) is the frequency weighted error signal.
The lowpass transfer function H(z) is responsible for the noise-shaping effect. The
2. TRELLIS ARCHITECTURE
7
Q-block is the decision-making unit for the output sequence. In case of a conventional SDM, Q is a 1-bit quantizer with the following definition:
(
y(t) =
+1 if c(t) ≥ 0
−1 if c(t) < 0
(2.1)
According to this implementation, a loop delay z −1 is necessary, otherwise the quantizer has to know the value of y(t) before y(t) is actually determined. As a result
of this definition, the SDM calculates the output as a function of previous input
and output values only. The new output is chosen such that the instantaneous error
(c(t)) is as small as possible. However, minimizing the error at each time independently is not necessarily the best solution. This is obvious when a SDM starts to
oscillate. Although the error is minimized at every point in time, the total weighted
noise power in the output signal is far from minimized.
1.2
Trellis Sigma Delta Modulator
Instead of using a simple quantizer, another decision-making unit can be implemented. Figure 2.2 shows the general relation between the signals in a Noise Shaping Device (NSD), without showing the decision-making unit. The ideal NSD is
defined to be:
Definition (Ideal NSD) The bitstream generator that creates output stream y(t)
such that the power in the frequency-weighted error signal c(t) is minimal.
In other words, the ideal NSD has to minimize PE , defined below in equation 2.2,
by choosing the correct symbols y(t).
θ
X
1
PE = lim
[c(t)]2
θ→∞ 2θ + 1
t=−θ
x(t)
+
d(t)
-
H(z)
(2.2)
c(t)
y(t)
Figure 2.2: A general model for a NSD.
8
2. TRELLIS ARCHITECTURE
However, to minimize this function, we have to evaluate it for the innumerable possible output sequences. Besides, the function is defined over an infinite time domain.
A solution is provided by the Trellis architecture, which is only an approximation of
the ideal NSD, but solves the two inherent problems (infinite time domain and innumerable possible sequences). The infinite time domain is reduced to the time span
between 0 (starting time) and t (current time). The new measure, approximating
the original power function (equation 2.2), is the cost function, defined as:
Definition (Cost function)
CωN (t) =
t
X
[c(τ )]2
(2.3)
τ =0
The second problem of the ideal NSD, calculating an infinite number of output
sequences, is solved by considering a certain amount of candidate output sequences
only. The actual amount of candidates is determined by an independent parameter
N , the Trellis order. A candidate output sequence is a sequence of output symbols
∈ {−1, 1} defined for time τ with 0 ≤ τ ≤ t and t the current time. The last
N symbols are different for all candidates. Consequently, there are exactly 2N
candidates. For all of these, the cost function (formula 2.3) is evaluated, where ωN
is the sequence of the last N bits. A smaller value of the cost function indicates a
better approximation to the input signal x(t). Thus, minimizing the cost function
for t → ∞ coincides with finding the optimal output-stream.
1.3
Viterbi algorithm
The Viterbi algorithm [4] is a method of finding the optimum output sequence, using
dynamic programming, and will be discussed here.
Suppose that the information about all (2N ) candidates at time t − 1 is known.
The information for each candidate consists of the history of the output sequence,
the current state inside the loop-filter and the value for the cost function. Based
on this situation, the Viterbi algorithm is carried out to minimize the costs for the
candidates at time t. Figure 2.3 (left) shows the state diagram for Trellis order
N = 2. There are 2N = 4 candidates, indicated by the last two output symbols.
The origination of the new candidates from the old candidates is dependent on the
new output symbol, as indicated by the paths between the states. The right side
of the picture shows how the new candidates at time t are chosen from the old
2. TRELLIS ARCHITECTURE
9
candidates at time t − 1. The following definitions were used:
σ or ς
∈ {−1, 1}, single output bit
ωN −1
sequence of N − 1 output bits
cςωN −1 σ (t) filter output after processing of σ when
candidate ςωN −1 at t − 1 is used.
t-1
00
01
10
11
t
00
0
1
0
1
0
1
0
01
t-1
0ωN-1
10
1ω N-1
σ
σ
t
ω N-1σ
11
1
Figure 2.3: Origination of new candidates (time t) from old candidates (time t − 1).
Complete state diagram for 2N = 4 candidates (left), and the general case (right).
For clarity, the signal level -1 is represented by the symbol “0” inside all figures.
Out of the two possible paths for every new candidate, the path with the smallest
total costs is chosen:
Cpath1 = C0ωN −1 (t − 1) + [c0ωN −1 σ (t)]2
Cpath2 = C1ωN −1 (t − 1) + [c1ωN −1 σ (t)]2
(
CωN −1 σ (t) =
Cpath1 if Cpath1 ≤ Cpath2
Cpath2 if Cpath1 > Cpath2
(2.4)
(2.5)
After the determination of the cheapest path for each candidate, the new value for
the cost function, the new filter state and the new output symbol are known, again
for each candidate. The total output sequence for a new candidate is given by the
output sequence of the previous state followed by σ. The definition of the Trellis
structure is that the output sequences for all 2N candidates terminate with different
symbols, thus there are 2N different output sequences as well. Fortunately, though
the sequences diverge at time t, the output sequences tend to converge to a single
solution for t → −∞. This is demonstrated in figure 2.4: the bold red lines show the
paths chosen by the Viterbi algorithm. Between time t−1 and t, the four candidates
have a different path, but before t − 3 the paths are equal for all candidates.
10
2. TRELLIS ARCHITECTURE
t-4
t-3
t-2
t-1
t
00
00
00
00
00
01
01
01
01
01
10
10
10
10
10
11
11
11
11
11
Figure 2.4: Convergence of paths: the bold red lines show the origination of the
four candidates. The different candidates terminate with different output symbols,
but in history (t → −∞) the output sequences converge to a single solution.
After some time, the paths between t − 1 and t will converge to a unique solution
as well. An easy example explains how this is possible: suppose that the value of
the cost function for the first candidate (“00”) is much lower than for the other
candidates. In that case, it is likely that the future paths start from candidate “00”.
Figure 2.5 shows the result two sample periods later.
t-2
t-1
t
t+1
t+2
00
00
00
00
00
01
01
01
01
01
10
10
10
10
10
11
11
11
11
11
Figure 2.5: Convergence of paths: example when candidate “00” at time t is cheap
compared to the other candidates at time t. Two sample periods later, all paths
converged up to time t.
Assuming that all paths converge in the past, output symbol y(t − tlat ) can be
determined at time t unambiguously when the value of tlat , also indicated with
Latency, is large enough. However, the minimum Latency has to be determined
experimentally. The influence of choosing Latency too small will be discussed during
the simulations at the end of this chapter.
1.4
Initialization of the Trellis structure
The Viterbi algorithm stores three important data structures into memory for all
candidates. These data structures are: The filter state, the path history and the
2. TRELLIS ARCHITECTURE
11
current value of the cost function. When the Viterbi algorithm is carried out to
progress from time t − 1 to time t, the new data structures are calculated based
on the data from the previous time stamp. However, when the algorithm is started
for the very first time (say t = 1), there is no data available for the previous time
stamp. That is why the data for time t = 0 has to be initialized to certain values
by the software before the actual algorithm is initiated.
The initialization of the filter state has influence on the produced output stream:
different initializations can lead to different output streams. However, there is no
reason to choose a certain initialization. For simplicity, the filter is initialized to
zero. The path history has no influence at all for the future decisions made by
the Viterbi algorithm, we are free to choose any initialization. However, the first
tlat output symbols of the SDM become equal to the sequence that was used to
initialize the path history. Therefore, it is set to an alternating sequence of “0”
and “1” symbols, representing DC level zero. Setting the cost function to zero for
all candidates means that we have no preference for a certain candidate to begin
with. This is exactly the case, as it has no influence at all on the produced output
stream. The output symbols (after the alternating sequence of length tlat ) are fully
determined by the paths selected by the Viterbi algorithm, and not by the initial
states. Table 2.1 shows the initialization for the data structures. For all candidates,
the same initialization is used.
Filter state
Path history
Cost function
0 (all integrators)
“01010101...” (zero DC level)
0
Table 2.1: Initialization of data structures.
1.5
Required resources
Although the Trellis architecture offers some benefits compared to a standard SDM,
as will be shown in the last paragraph of this chapter, this comes at the expense of
computational power and memory usage. Table 2.2 gives an overview of the needed
resources in case of a classical SDM and in case of a Trellis SDM with order N . It
appears that both the amount of work and the memory usage increase exponentially
in N .
12
2. TRELLIS ARCHITECTURE
Computational
power for each
sample moment
Memory usage
Standard SDM
Trellis SDM
1 quantizer decision
2N +1 path calculations
1 filter state
2N filter states
2N cost function values
2N · Latency output symbols
Table 2.2: Needed system resources for a standard SDM and for a Trellis SDM.
2
Implementation
To add the Trellis algorithm to the already available simulation environment for
standard Sigma Delta converters, it is implemented as a C-function. For readability,
this paragraph contains pseudo-code only. As an introduction, the implementation
of a standard SDM is discussed first.
2.1
StandardSDM function
In the simulation software, all Sigma Delta converters are implemented as a Cfunction, represented by the black box in figure 2.6. This function is called once for
every new sample period. The routine is supplied with the new input value X at
that time, and returns a new output symbol Y to the calling function.
x
y
Figure 2.6: SDM function implemented in C: a new sample X is supplied, the SDM
produces a new output symbol Y.
For the standard SDM (in figure 2.1) the routine inside the black box can be described with the following pseudo-code. First, the input to the noise-shaping filter
is calculated. Then the new filter output is calculated as a function of the current
filter state and the new filter input. Finally this value is quantized and returned by
the function.
2. TRELLIS ARCHITECTURE
13
Y := StandardSDM (X)
X ← INPUT
FilterInput := X - PreviousY
FilterOutput := Filter (FilterInput)
Y := Quantize (FilterOutput)
Y → OUTPUT
2.2
TrellisSDM function
In case of a Trellis converter, the software implementation is not so straightforward.
However, the state diagrams as presented in paragraph 1.3 are a good starting point
to explain the algorithm. Figure 2.7 shows an example of a state diagram for Trellis
order N = 2. The routine in the black box has to calculate the state of the new
candidates at time t based on the new input signal X and based upon the state of
the candidates at time t − 1.
t-1
00
01
10
11
t
0
1
0
1
0
1
0
1
00
01
10
11
Figure 2.7: Origination of new candidates (time t) from old candidates (time t − 1).
The algorithm calculates for every new candidate the total costs for the two possible
paths. The cheapest path is selected. For the new candidate, the total costs, the
state inside the noise-shaping filter and the new path are stored. Finally, the function
has to return some output symbol Y. In the previous paragraph, it was stated that
in history the paths for the different candidates converge to a single path. Thus,
the function returns the symbol according to the value of the path tlat time-stamps
back. If tlat is chosen large enough, all paths converged, and the determination of
Y is unambiguous. The path history of any candidate can be used to determine the
output symbol. If tlat is not large enough, not all paths converged, and it is possible
that the wrong output symbol is returned by the function. The influence of this
problem is investigated in the last paragraph of this chapter.
14
2. TRELLIS ARCHITECTURE
Y := TrellisSDM (X)
X ← INPUT
For (All NewCandidates)
C1 := CalculateTotalCosts (Path1 , X)
C2 := CalculateTotalCosts (Path2 , X)
if (C1 < C2 )
Select (Path1 )
else
Select (Path2 )
Save (NewCosts, NewFilterState, NewPath)
For (All NewCandidates)
TotalCosts := TotalCosts - MinimumCosts
Y := PathValue (tcurrent - tlat )
Y → OUTPUT
An aspect that was not yet considered is that the cost function is defined as:
CωN (t) =
t
X
[c(τ )]2
τ =0
The value of this function is non-decreasing and will go to infinity when t → ∞,
resulting in overflow in the software implementation. However, the algorithm is
not based on the absolute value of the cost function. The cost function is used
only to compare paths, and to select the cheapest alternative. For that reason, it
is allowed to subtract a constant value from the cost function, if it is done for all
candidates. The software implementation determines MinimumCosts, the value of
the cost function for the cheapest alternative, and subtracts it from all cost functions.
This guarantees that the value of the cost function for the cheapest alternative is
zero, and the value for the most expensive alternative is minimized. The calculation
of MinimumCosts is mathematically represented by the relation:
³
´
³
´
∀ωN : MinimumCosts ≤ CωN (t) ∧ ∃ωN : MinimumCosts = CωN (t)
2. TRELLIS ARCHITECTURE
(2.6)
15
2.3
CalculateTotalCosts function
The function of the CalculateTotalCosts-routine in the TrellisSDM-routine is to
calculate the total costs for a certain path in the trellis diagram. Figure 2.8 gives
an example of a path.
t-1
X
t
00
1
01
Figure 2.8: Path example: Old candidate “00” will lead to new candidate “01” when
the new output symbol Y is “1”.
The input symbol X is known (due to the definition of the black box in figure 2.6).
The output symbol Y is fixed for a certain path. To calculate the total costs for the
new candidate, the noise-shaping filter is first loaded with the state belonging to
the old candidate. Then, the error signal X - Y is processed by the filter. Finally
the value of the cost function for the new candidate, using this path, is calculated
according to:
NewCosts =
t
X
[c(τ )]2 =
τ =0
t−1
X
[c(τ )]2 + [c(t)]2 = OldCosts + (FilterOutput)2
τ =0
The CalculateTotalCosts-routine corresponds with the following pseudo-code:
NewCosts :=
CalculateTotalCosts (X, Y, OldCandidate)
X, Y, OldCandidate ← INPUT
RestoreFilterState (OldCandidate)
FilterInput := X - Y
FilterOutput := Filter (FilterInput)
OldCosts = CostFunction (OldCandidate)
NewCosts = OldCosts + (FilterOutput)2
NewCosts → OUTPUT
16
2. TRELLIS ARCHITECTURE
2.4
Path convergence problem
Despite the fact that in theory all paths inside the Trellis structure will converge, and
any candidate can be used to determine the output symbol, there is a convergence
problem when no input signal is applied. When the input signal remains x(t) = 0,
and at t = 0 we start with all states inside the noise-shaping filter equal to zero, the
SDM has to produce an output stream with an average value equal to zero. The
actual produced stream is dependent on the used noise-shaping filter and the Trellis
order. However, suppose the following stream is produced repeatedly:
01010101
Then, the inverted stream
10101010
has exactly the same value for the cost function. These two different paths remain
equally expensive, and will not converge to one solution. Figure 2.9 shows the
behavior in case of a second order Trellis structure.
t-4
00
t-3
00
t-2
00
t-1
00
t
00
01
01
01
01
01
10
10
10
10
10
11
11
11
11
11
Figure 2.9: Two equally expensive paths (010101 and 101010) will never converge
(bold red lines). When a fixed candidate is used to determine the output symbol,
then alternately path 010101 and path 101010 are used as path history. This results
in 000000 or 111111 as final output stream.
The implementation discussed in this chapter always uses the path history of candidate “00” to determine the output symbol. Looking at figure 2.9, this means that
the converters output-stream will become
00000000 or 11111111 ,
dependent on the used Latency. Although the converter is stable, and finds a correct path, the output stream is not correct. If, instead of candidate “00”, another
2. TRELLIS ARCHITECTURE
17
candidate is used to determine the output-stream, the same problem occurs. Increasing the Trellis order or increasing the Latency does not help at all: the two
paths will never converge. As the problem occurs for zero input-signals only, it is
considered of little interest at this moment. Especially because the optimized Trellis
structure, introduced in the next chapter, does not suffer from this problem.
3
Simulation results
A variety of simulations was carried out to determine parameters like signal to
noise ratio (SNR), harmonic distortion and stability as a function of the Trellis
order N . The problem of choosing the value tlat (latency before a new output symbol
is produced) is also discussed.
3.1
Signal to noise ratio
For the first simulation, the noise-shaping function is designed to be a 5th order
Butterworth filter (f0 = 100 kHz with two additional zero’s at 11 kHz and 16 kHz).
The input signal is fixed to a 0 dB SACD1 sine with frequency 1 kHz.
0
-55
Without Trellis
-20
-60
-40
-80
Power (dB)
Power (dB)
With Trellis
-65
-60
-100
-120
-70
-75
With Trellis
-140
-80
-160
Without Trellis
-85
-180
-200
100
1000
10000
Frequency (Hz)
-90
100000
log
100000
Frequency (Hz)
log
Figure 2.10: Output power spectrum for converter without Trellis (red) and with
Trellis (N = 2) (green), 512 power averages were used. The right picture shows the
difference around the corner frequency.
Figure 2.10 shows the output power spectrum for two different configurations: a
normal SDM without Trellis structure, and a SDM with a Trellis structure (N = 2).
1
18
Information about the definition of “dB SACD” can be found in appendix A.
2. TRELLIS ARCHITECTURE
Although the same loop filter is used for both converters, the noise power spectrum
is slightly different. This becomes most evident around the corner frequency of
the filter. As a result, the noise level in the base band increases when Trellis is
applied, and the SNR becomes worse. In chapter 4, a noise model especially for
Trellis converters is presented which gives a good estimation for the actual power
spectrum. Independent of the order N , Trellis structures show the same level of
noise in the base band as the 2nd order Trellis in the previous example. This is
visible in figure 2.11, where the SNR in the base band (below 20 kHz) is plotted
as function of the Trellis order. In all cases the SNR of the Trellis architecture is
several dB worse compared to a standard SDM. However, in paragraph 3.4, it will
be shown that Trellis architectures can handle more aggressive noise-shaping filters
than classical Sigma Delta Modulators. In this way, Trellis converters achieve higher
SNR values than standard converters.
119
118
117
SNR (dB)
116
115
114
113
112
111
No Trellis 0
2
4
Trellis order
6
8
10
Figure 2.11: SNR as a function of the used Trellis order N . On the left side, the
value for the converter without Trellis is placed, indicated with a ‘2’-mark. All
values are obtained after 32 power averages.
One could think about the question why the noise power spectrum for Trellis converters is different from the spectrum of a standard SDM. An important difference
is that in classical systems, there is always a sample-period delay in the loop: the
quantizer makes a decision first, and after that, the decision is processed by the
filter H(z). Trellis converters do not have this delay as they calculate the result
after processing by H(z) first, and choose the best alternative afterwards. It looks
2. TRELLIS ARCHITECTURE
19
reasonable to add a loop delay (z −1 ) artificially to the Trellis structure, and compare
that system again with a standard SDM. Figure 2.12 shows three different systems
that were tested with a Trellis algorithm. The picture on the left shows the system
that was used so far. The two other pictures show two different implementations of
a loop delay: in the feedback or in the forward path.
x(t)
+
d(t)
-
y(t)
H(z)
c(t)
x(t)
+
d(t)
-
y(t-1)
H(z)
z -1
c(t)
x(t)
y(t)
+
d(t)
-
z -1
H(z)
c(t)
y(t)
Figure 2.12: Three noise shaper implementations: Without loop delay (left), with
loop delay in the feedback path (middle) and with loop delay in the forward path
(right).
Suppose, the system with the delay in the feedback path is used, and a Trellis system
with order N = 0 is used. The Trellis calculates c(t) for y(t) = ‘0’ (c(t)|y(t)=‘0’ ) and
for y(t) = ‘1’ (c(t)|y(t)=‘1’ ). However, due to the loop delay, the filter output c(t)
at time t is independent from the last output symbol y(t), it is only dependent on
previous output symbols. Thus, c(t)|y(t)=‘0’ is always equal to c(t)|y(t)=‘1’ and the
Trellis algorithm is not able to make a correct decision for the output symbol. At
least a Trellis order equal to 1 is necessary to overlook the loop delay, and make
correct decisions. But this first order Trellis structure with loop delay performs
exactly the same as the zero-order Trellis structure without loop delay. Simulations
showed that Trellis converters with loop delay and Trellis order N +1 produce exactly
the same output sequence as Trellis converters without loop delay with Trellis order
N . The ‘+1’-increase of the Trellis order exactly compensates for the added delay.
For the second system with loop delay (the rightmost picture in figure 2.12), the same
argumentation is valid. A ‘+1’-increase of Trellis order is necessary to compensate
for the inserted delay, but after that, the output sequence is equal to the sequence
produced by a Trellis system without delay.
As in both cases, the output sequence remains equal to the sequence of a converter
with a delay-free loop, the shape of the noise power spectrum is also unchanged,
and is still different from the spectrum of a standard SDM. From another point of
view, it can also be explained why the addition of a loop delay does not change the
noise power spectrum. In chapter 4, it will be shown that the relation between noise
transfer function (NTF) and loop filter H(z) is given by the equation:
|N T F (z)| =
20
1
|H(z)|
(2.7)
2. TRELLIS ARCHITECTURE
Adding a loop delay means that H(z) is replaced by z −1 H(z), thus the new noise
transfer function becomes:
|N T F (z)| =
1
|z −1 H(z)|
=
1
|z −1 ||H(z)|
=
1
|H(z)|
(2.8)
The new NTF is exactly the same as the original one, showing that the noise power
spectrum will have the same shape as before. The only way to create a Trellis
architecture with a NTF comparable to the NTF of a standard SDM, is to redesign
the loop filter H(z). Based on the NTF from the standard SDM, and the model from
chapter 4, the loop filter H(z) for a Trellis structure can be designed. Nonetheless,
for all comparisons between standard SDM and Trellis SDM in this report, the same
filter H(z) will be used for both systems.
3.2
Linearity
The non-linearity of a SDM becomes visible as harmonic distortion in the power
spectrum. To investigate the linearity as function of the Trellis order, again a
converter with a 5th order Butterworth filter was used (f0 = 100 kHz with two
additional zero’s at 11 kHz and 16 kHz). The input signal is fixed to a 0 dB SACD
1 kHz sine. The most important harmonic distortion components are the 3rd , 5th ,
7th and 9th component. Figure 2.13 plots the power (relative to the 0 dB SACD
signal power) in each of these components as a function of the Trellis order N .
The linearity of any system is determined by the total power in the distortion components together. For low Trellis orders (0 ≤ N ≤ 2), the linearity of the Trellis
converter is worse than the linearity of a standard SDM. This is not strange, as
in general, the distortion components follow the noise shaping curve. As already
discussed in paragraph 3.1, for Trellis architectures the noise shaping function in
the base band is around 6 dB above the curve of a standard SDM when the same
loop filter H(z) is used. This makes an increase of harmonic distortion for Trellis architectures with the same amount (roughly 6 dB) plausible. Nevertheless, for
N ≥ 1, the total power in the distortion components is decreasing as a function
of N . For N ≥ 3, the linearity of the Trellis converter exceeds the linearity of a
standard SDM. The reason for the increasing linearity is that harmonic distortion is
“expensive”. Harmonic distortion components are coherent frequency components,
present in the output signal y(t), but not in the input signal x(t). Thus, the error
signal d(t) = x(t) − y(t) contains all harmonic distortion signals. All components,
present in the signal base band, are weighted heavily by the loop filter H(z), and
2. TRELLIS ARCHITECTURE
21
-120
No Trellis
N=0
N=1
N=2
N=3
N=4
N=5
N=6
-125
-130
-135
Power (dB)
-140
-145
-150
-155
-160
-165
-170
-175
3rd
5th
7th
9th
Harmonic distortion component
Figure 2.13: Power in the 3rd , 5th , 7th and 9th harmonic distortion component as a
function of the Trellis order. The power is measured relative to the signal power,
which is 0 dB SACD or -9 dBFS.
count heavily in c(t) and the cost function. As the Viterbi algorithm searches for
the cheapest path inside the Trellis structure, paths with better linearity will be
preferred above paths with worse linearity. The trend is that Trellis converters with
increasing N succeed in finding even cheaper solutions, having better linearity as
well.
3.3
Stability
Another interesting parameter is the input range for which the system remains stable. When the input amplitude exceeds a certain value, the SDM starts to oscillate.
The maximum input for which the system is stable is plotted as a function of the
Trellis order in figure 2.14. Amplitude ‘1’ corresponds with a full scale input signal. As in the previous simulations, the designed noise-shaping filter is a 5th order
Butterworth filter with f0 = 100 kHz and two additional zero’s at 11 kHz and 16
kHz. The figure makes clear that the Trellis structure can prevent oscillation: the
straightforward decision-making unit (a quantizer) will start to oscillate when input amplitudes larger than 0.65 are used. The Trellis converter chooses it’s output
bit-pattern such that overload inside the noise-shaping filter is prevented, while still
22
2. TRELLIS ARCHITECTURE
maintaining the high SINAD2 value as in the case of a normal SDM. For a 10th
order Trellis, the input range is already extended with 17% of the full scale input.
0.9
120
115
0.8
SINAD (dB)
Maximum input amplitude
0.85
0.75
110
0.7
105
0.65
0.6
No Trellis 0
2
4
Trellis order
6
8
10
100
No Trellis 0
2
4
Trellis order
6
8
10
Figure 2.14: Maximum input amplitude for which the system is stable, plotted as
function of the used Trellis order (left) and the SINAD for this maximum amplitude
(right). A ‘2’-mark indicates the SDM without Trellis structure.
3.4
Filter frequency
The simulations in section 3.1 (figure 2.11) showed that the SNR for a fixed inputsignal decreases when the Trellis algorithm is applied. However, from the simulation
in the previous paragraph it follows that the maximum SINAD, reached at the
maximum input level, is more or less constant, independent on the used Trellis
order. Nevertheless, it is also possible to apply Trellis to increase the SNR (and
SINAD) for a fixed input level. This can be done by increasing the filter frequency
(f0 ). A higher frequency results in a lower noise level in the base-band. However,
when the frequency is too high, the system will become instable. Simulations show
that higher filter frequencies are possible when the Trellis order increases. For this
simulation, the loop-filter is a 5th order Butterworth filter, but without additional
zero’s. Because there are no additional zero’s, the noise level in the base band is
determined by the filter frequency (f0 ) only. f0 is increased until the SDM is nearly
instable for a 0 dB SACD 1 kHz input signal. The maximum possible filter frequency
and the SINAD (for a -6 dB SACD input signal) are plotted in figure 2.15. The
SNR is not plotted as it shows exactly the same trend as the SINAD plot.
The increase of SINAD as a function of N , shows the same trend as the increase
2
SINAD is the ratio (in dB) between signal power and power in distortion components together
with noise power.
2. TRELLIS ARCHITECTURE
23
350
120
115
250
SINAD (dB)
Maximum filter frequency (kHz)
300
200
110
105
150
100
100
50
No Trellis
0
1
2
3
4
Trellis order
5
6
7
8
95
No Trellis
0
1
2
3
4
Trellis order
5
6
7
8
Figure 2.15: Higher filter frequencies are possible with higher Trellis orders (left),
while maintaining stability. This leads to better SINAD values as well (right). A
‘2’-mark indicates the SDM without Trellis structure.
of the filter frequency. At first sight, one could expect that every doubling of the
filter frequency f0 results in an increase of the SINAD of 6 · n = 30 dB (where n
is the filter order). Nevertheless, the relation between filter frequency and SINAD
is no so straightforward: the more aggressive filtering will decrease the amount of
coherent power in the frequency range around 12 fs . As the total output power of a
SDM is constant, the amount of noise power will increase in the complete frequency
range (0 up to 12 fs ), but the higher filter frequency will redistribute the noise power
according to a new noise-shaping function. The actual SINAD value is the result of
all these effects together, and an estimation of the SINAD value is not simple.
All simulations are performed using 100000 data-samples. When more samples are
used, the systems from figure 2.15 become instable. The filter frequencies have
to be lowered again until stability is achieved. However, simulations with 800000
samples showed the same trend as the presented result, except that the maximum
frequencies are a bit lower (4 to 6%). Because the maximum frequency for a system
without Trellis also decreases 4%, the trend is comparable to the example as shown
in figure 2.15. In general, the higher filter frequency can be used to increase the
SNR and SINAD of the system. The reduction of input range due to the higher
filter frequency can be compensated for by using a higher Trellis order.
3.5
Latency
Finally, the influence of the chosen Latency is discussed. In the first section of this
chapter, it was stated that a certain delay is necessary before the output symbol is
24
2. TRELLIS ARCHITECTURE
determined: tlat or Latency. When Latency is chosen large enough, the determination of the output symbol is unambiguous, otherwise, there is a chance of producing
the wrong output symbol.
Figure 2.4 is used as an example. If tlat = 3, the output symbol for t−3 is determined
at time t. For all candidates at time t, the path value at time t−3 is equal to ‘0’, thus
the output symbol can be determined unambiguously. When tlat = 2 is used, the
path value at time t − 2 is different for the different candidates. Thus, dependent on
the candidate that is used to determine the output symbol, a different output symbol
can be produced. If candidate ‘00’ or ‘10’ is used at time t to choose the output
symbol for time t−2, a ‘0’ will be produced. When candidate ‘01’ or ‘11’ is used, the
output symbol will become ‘1’. The influence of the possible misjudgement is visible
in figure 2.16. It shows the output power spectrum of a 5th order Butterworth filter
with 0 db SACD input signal in combination with a 5th order Trellis. The spectrum
is given for four different values of Latency: 70, 80, 85 and 90 samples delay. In case
of Latency ≥ 90, the delay is long enough to produce the correct (unique) output.
When Latency < 90 is used, a flat spectrum in the base band appears. This is the
effect of choosing an output symbol when the paths for the different candidates did
not yet converge to the final solution. This signal component is usually described
with the term truncation noise.
0
-50
Power (dB)
70
-100
80
85
-150
90
-200
-250
100
1000
10000
Frequency (Hz)
100000
log
Figure 2.16: Output power spectrum for different values of Latency (70, 80, 85, 90).
The power spectral density of the truncation noise in the base band is almost frequency independent. Consequently, it can be described with one value: P SDT N .
2. TRELLIS ARCHITECTURE
25
Small values of Latency result in an increasing P SDT N . Figure 2.17 shows P SDT N
as a function of Latency. It affirms that the power density of the truncation noise
is relatively stable for 50 ≤ Latency ≤ 85, but when Latency increases from 85 to
90, the noise suddenly disappears.
Truncation noise power spectral density (dB / Hz )
-60
-80
-100
-120
-140
-160
-180
-200
-220
-240
-260
50
55
60
65
70
75
Latency (Samples)
80
85
90
Figure 2.17: Power spectral density of the truncation noise in the output signal due
to too small value of Latency.
The source behind truncation noise is path truncation (or simply truncation): it
arises, because the output symbol is determined when not all paths converged to
the final solution. The output symbol is determined using one of the different paths
that still exist after the Latency delay. Sometimes, the output symbol determination switches to another path. This jump to another path (or truncation of the
previously used path) gives an instantaneous error, resulting in truncation noise.
This instantaneous error should be visible as short clicks in the time domain, and
is verified with the following simulation.
To investigate the influence of the truncation noise in the time domain, a 1 kHz
sine wave was synthesized in a normal audio file (16 bits quantization, fs = 44.1
kHz). This file was upsampled to 64fs , the sample frequency of SACD. The data
after upsampling is still multi-bit, in our case 32 bit. Then, this data is processed
through a Trellis SDM (of which the Latency is chosen too small on purpose), and
downsampled to the original audio format (16 bit, 44.1 kHz). Figure 2.18 plots a
part of the audio file. Besides the original 1 kHz signal, three short peaks are visible
in this picture, due to truncation.
26
2. TRELLIS ARCHITECTURE
Amplitude (Normalized to 1)
0.5
0.25
0
-0.25
-0.5
0
50
100
150
200
250
Time (Samples)
300
350
400
Figure 2.18: Time domain signal after downsampling to 44.1 kHz. The short peaks
are the effect of truncation noise.
The time and frequency domain simulations are in accordance with each other, as
the fourier transform of an impulse signal in the time domain, is a flat power density
spectrum in the frequency domain. When Latency is increasing, the peaks in the
time domain will occur less frequent, reducing the noise level in the power spectrum.
All peaks (even the small ones) are very audible, and should be avoided definitely.
In practice, we would like to choose Latency such that there is no problem in the
determination of output symbols. Simulations are necessary to choose the minimum
needed value for Latency. With the output power spectrum, it is very easy to check
whether a certain Latency is sufficient. Some problems are displayed in figure 2.19.
The uppermost picture shows that the minimum value for Latency is not only
dependent on the Trellis order, but also on the used input signal. The lower figure
shows that for very small input signals, the Latency increases significantly.
2. TRELLIS ARCHITECTURE
27
300
A = 10E-06
Minimum Latency (Samples)
250
200
A = 0.5
150
A = 0.25
100
50
0
1
2
3
4
5
Trellis order
6
7
8
260
240
Minimum Latency (Samples)
220
200
180
160
140
120
100
80
60
1e-12
1e-10
1e-08
1e-06
0.0001
Input amplitude
0.01
1
log
Figure 2.19: Minimum needed value for Latency for unambiguous determination
of the output stream: as a function of the used Trellis order N for three different
values of the input amplitude A (top), and as a function of the input amplitude for
Trellis order N = 5 (bottom).
28
2. TRELLIS ARCHITECTURE
Chapter 3
Efficient Trellis architecture
A disadvantage of the Trellis architecture is that for all candidates we have to store
the output sequence, the filter state and the value of the cost function. Furthermore,
the Viterbi Algorithm has to calculate two possible paths for each candidate at every
sample moment. Both the number of computations and the amount of memory
increase exponentially with N . This limits the Trellis order to relative low values.
In this chapter a more efficient implementation is introduced.
1
1.1
Model
Efficient Trellis Sigma Delta Modulator
One way to increase the efficiency of a Trellis structure, is to calculate only a fraction
of all 2N candidates. After all, our only interest is to find the single candidate with
minimum global costs. The candidates most likely to lead to the optimum final
solution are taken into account, the other candidates are not used. The following
heuristics are used:
- Cheap candidates have high probability to converge to the optimum sequence.
- Expensive candidates have low probability to converge to the optimum sequence.
3. EFFICIENT TRELLIS ARCHITECTURE
29
To verify this hypothesis, a 10th order Trellis in combination with a 5th order Butterworth filter was simulated with input signal 0.5 sin(2π1000t). The candidate output
sequences (in this case 1024) are sorted on increasing cost function (formula 2.3).
After that, the candidates are numbered with a cost index i; the M cheapest alternatives are the candidates with 1 ≤ i ≤ M . When t → ∞, the final output sequence
is determined, and ∀t the corresponding candidate with it’s index i is traced back.
Figure 3.1 shows the chance for a candidate with a certain cost index to become the
optimum solution. It is clear that the optimum solution is mainly determined by a
small amount of all candidates (< 10 out of 1024).
0.7
0.6
P final sequence
0.5
0.4
0.3
0.2
0.1
0
1
10
100
1000
Cost index (log)
Figure 3.1: The chance for a candidate with a certain cost index to become the
optimum solution. The cost index ranks the candidates on increasing cost function.
To take advantage of this knowledge, the Trellis algorithm is adapted in the following
way: based on the cost index, M ≤ 2N candidates are selected and used for further
processing, instead of using all 2N candidates. In brief, the new algorithm can be
described as follows:
Algorithm Given the M cheapest candidates at time t−1, calculate the M cheapest
candidates at time t.
In detail, the algorithm starts with the M cheapest candidates at time t − 1. Every
candidate at t − 1 leads to two new alternatives at time t, see figure 3.2. Because
of this, the number of new alternatives is equal to 2M . But, it is possible that two
different candidates at time t − 1 lead to the same new candidate at time t (see
30
3. EFFICIENT TRELLIS ARCHITECTURE
figure 3.3). To maintain the Trellis structure (last N symbols are different for all
candidates), only one of the two alternatives (the cheapest) is used. In the most
extreme case, the 2M new alternatives consist of M different candidates only. After
elimination of double candidates, the number L of new candidates is bounded by
M ≤ L ≤ 2M . Then, the L candidates are sorted on cost function, and the cheapest
M out of L are selected. In pseudo-code, the algorithm looks like:
1. Calculate 2M new alternatives at time t.
2. Sort on increasing cost function.
3. When a candidate occurs twice, remove most expensive candidate.
4. Store first M candidates at time t only.
t
t
t-1
0
1010
1
1011
0101
t-1
σωN-1
0
ωN-10
1
ωN-11
Figure 3.2: Path dependency for the new structure: every old candidate at time
t − 1 leads to two new candidates at time t. An example (left) and the general case
(right).
t-1
0011
1
1011
1
t
0111
t-1
0ωN-1
1ω N-1
σ
σ
t
ω N-1σ
Figure 3.3: Problem with the new structure: two old candidates at time t − 1 lead
to the same new candidate at time t. To maintain the Trellis structure, it is not
allowed to use both paths. An example (left) and the general case (right).
1.2
Required resources
An advantage of this new architecture is that we are free to chose M within the
range 1 ≤ M ≤ 2N . A smaller M provides a more efficient solution, while a larger
M gives a better approximation to the original Trellis converter. Table 3.1 compares
3. EFFICIENT TRELLIS ARCHITECTURE
31
the required resources for both architectures. The amount of work increases linearly
in M instead of exponentially in N . Increasing N while M is constant has little
effect on the required computational power. The memory usage is also linear in
M , except for the memory needed to store the output symbol history: Latency is
increasing as a function of N . However, the gain is still significant.
Trellis SDM
Efficient Trellis SDM
Computational
power for each
sample moment
2N +1 path calculations
2M path calculations
Memory usage
2N filter states
2N cost function values
2N · Latency output symbols
M filter states
M cost function values
M · Latency output symbols
Table 3.1: Needed system resources for a ‘normal’ Trellis SDM and for an efficient
Trellis SDM.
2
2.1
Implementation
EfficientTrellisSDM function
The actual software implementation is a little bit different from the algorithm as
described in the previous section. The model calculates all 2M alternatives first
and orders them on increasing cost function. Then, the M correct candidates are
selected. On the other hand, the software function starts sorting immediately. First
of all, a new (empty) sorted list is created. Then, the 2M new alternatives are
calculated one by one. The new alternatives are inserted into the list such that the
list remains correctly ordered on increasing cost function. The pseudo-code for the
new Trellis converter is given below.
32
3. EFFICIENT TRELLIS ARCHITECTURE
Y := EfficientTrellisSDM (X)
X ← INPUT
StartNewlist
For (All OldCandidates)
C1 := CalculateTotalCosts (Path1 , X)
C2 := CalculateTotalCosts (Path2 , X)
AddToList (Path1 , C1 )
AddToList (Path2 , C2 )
For (All NewCandidates)
TotalCosts := TotalCosts - MinimumCosts
Y := PathValue (tcurrent - tlat )
Y → OUTPUT
Although not visible in this code, there are some special situations while adding
items to the list:
- When the number of items in the list equals M , and the alternative to be added
is more expensive than the most expensive item in the list, this alternative is
not added to the list.
- When the number of items in the list equals M + 1, the most expensive item
is removed.
- When there is a candidate in the list of which the last N symbols equal the
last N symbols of the alternative to be added, the cheapest of them is inserted
in the list, the most expensive is removed from the list.
The first two rules guarantee that the number of items after all candidates are
processed, equals M . The third rule makes sure that the Trellis structure (last N
symbols different for all candidates) is maintained.
The CalculateTotalCosts-routine has exactly the same function as in the original
Trellis architecture. The subtraction of MinimumCosts to prevent overflow is also
implemented in the same way as before. The determination of the output-symbol Y
after some delay tlat is a little bit different from the original case. The full Trellis
architecture always uses the same candidate to determine Y, but the new architecture
uses the cheapest candidate instead. This is not only the easiest solution (because
3. EFFICIENT TRELLIS ARCHITECTURE
33
the cheapest candidate is the first item in the sorted list), but also solves the pathconvergence problem that was discussed in the previous chapter, this will be shown
in the next paragraph.
2.2
Path convergence solution
In paragraph 2.2.4 on page 17, it was shown that when the input signal is equal to
zero, the paths for the different candidates will not converge to a single solution.
When a fixed candidate is used to determine the output stream, the produced output
sequence might be invalid. The efficient algorithm presented in this chapter uses
a variable candidate (the cheapest), and does not suffer from this problem. When
there are several candidates with the same minimum costs, the candidate evolving
from the candidate that was used the previous time is selected to produce the output
symbol. This means that we automatically follow a certain path, except when a
cheaper path will emerge. In figure 3.4 the effect is made visible.
t-4
00
t-3
00
t-2
00
t-1
00
t
00
01
01
01
01
01
10
10
10
10
10
11
11
11
11
11
Figure 3.4: Two equally expensive paths (010101 and 101010) will never converge
(bold red lines). The candidate, used to determine the output symbol, is made
variable and follows the path that was used at the previous sample moment. The
used candidates are indicated with square boxes. In this case, the output stream is
correct (010101) for a zero input-signal.
In appendix B a realistic example shows the different behavior for a zero input-signal
for a standard SDM, a Trellis converter implemented with a fixed candidate, and a
Trellis converter implemented with a variable candidate.
34
3. EFFICIENT TRELLIS ARCHITECTURE
3
Simulation results
The simulations in this paragraph investigate the same properties as in the previous
chapter (signal to noise ratio, linearity, stability, etc.), but show that the efficient
architecture achieves the same, or even better performance compared to the ‘original’
Trellis architecture, with a significant reduction in the amount of work.
In accordance to previous definitions, N and M are used to indicate the following
parameters:
N Trellis order, the system has 2N candidates.
M Number of candidates that is actually processed.
The original Trellis structure (where M equals 2N ) will be referred to as the full
Trellis architecture.
In general the following simulations will show the change in performance as a function of N and M . It is important to realize that the needed computational power is
mainly determined by M , and hardly by N . The memory usage to store the filter
state and the cost function is only determined by M , but the memory usage to store
the path history is a function of both M and N . It is not a problem any more to
use very high Trellis orders, as long as M is small.
Before going into details, a short comparison between the full Trellis structure,
the efficient converter and a standard SDM is made in the first paragraph. After
that, parameters like signal to noise ratio, linearity, stability and maximum filter
frequency will be discussed more thoroughly.
3.1
Trellis versus efficient Trellis converter
As a short introduction to the efficient architecture, figure 3.5 compares an efficient
converter (N = 8, M = 4) to a converter without Trellis structure (left), and to
a full Trellis converter (N = 8) (right). In all three systems, the noise shaping
filter is a 5th order Butterworth filter (f0 = 100 kHz and two additional zero’s at 11
kHz and 16 kHz). The input signal is a 0 dB SACD 1 kHz sine wave. The Trellis
order of both Trellis architectures is equal, but the efficient solution reduces both
the computational power and the memory usage by a factor of 64. The picture on
the left side shows that the suppression of the 3rd and 5th harmonic for the efficient
3. EFFICIENT TRELLIS ARCHITECTURE
35
solution, compared to a standard SDM, is significant. As was the case with full
Trellis structures as well, the noise level in the base band for an efficient Trellis
SDM is higher than the noise level of a standard SDM. The picture on the right
side shows that the noise spectrum for the full system and the efficient solution are
equal, resulting in the same SNR. In the depicted spectrum, the linearity of the
efficient converter shows no visible deterioration compared to the linearity of the
full Trellis.
0
0
without Trellis
efficient Trellis, N = 8, M = 4
-20
-40
-40
-60
-60
-80
Power (dB)
-80
Power (dB)
full Trellis, N = 8
efficient Trellis, N = 8, M = 4
-20
-100
-120
-100
-120
-140
-140
-160
-160
-180
-180
-200
-200
-220
-220
1000
10000
Frequency (Hz)
1000
100000
log
10000
Frequency (Hz)
100000
log
Figure 3.5: Output power spectra after 8 power averages and 8 coherent averages.
Standard SDM compared to efficient Trellis SDM (N = 8, M = 4) (left), and full
Trellis SDM (N = 8) compared to efficient Trellis SDM (N = 8, M = 4) (right).
3.2
Signal to noise ratio and linearity
For a more detailed investigation of the SNR and linearity of efficient Trellis architectures, a new simulation was performed. The noise-shaping function is a 5th
order high-pass Butterworth filter with f0 = 100 kHz and two additional zero’s (11
kHz and 16 kHz). The input signal is a 1 kHz, 0 dB SACD sine. Figure 3.6 shows
the output power spectrum for two different configurations: a normal SDM without
Trellis structure, and a SDM with Trellis structure. The parameters for the Trellis
structure are N = 10 and M = 4, thus only 4 out of 1024 candidates are taken into
account.
Two effects are visible in the power spectrum: First, the linearity of the Trellis SDM
is better than the linearity of the normal SDM. Especially the improved suppression
of the 3rd order harmonic is significant. The second conclusion from figure 3.6 is
that using the Trellis algorithm, the SNR becomes worse compared to standard
SDM. This is exactly the same result as before with the full Trellis architecture
36
3. EFFICIENT TRELLIS ARCHITECTURE
0
-20
-40
Power (dB)
-60
-80
-100
-120
with Trellis N = 10, M = 4
-140
-160
without Trellis
-180
-200
1000
10000
Frequency (Hz)
100000
log
Figure 3.6: Output power spectra after 512 power averages for two converters with
the same loop-filter. The input signal is a 1 kHz sine. The configuration without
Trellis is a SDM with a normal quantizer, the other system has a 10th order Trellis
of which 4 candidates are processed.
(see figure 2.10): independent of the order N and the value of M , Trellis structures
show the same level of noise in the base band as the 10th order Trellis in this
example, this is demonstrated in figure 3.7. The ‘+’-marks show the performance
of full Trellis architectures. In all cases (both for full and for efficient systems) the
SNR of the Trellis architecture is several dB worse compared to a standard SDM
(indicated with a ‘2’-mark).
An interesting question is whether it is advantageous to use a Trellis configuration
with N = 10 and M = 4 instead of a structure with N = 2, M = 4. For comparison,
figure 3.8 plots the power spectra for these systems. It appears (as expected) that
both converters have about the same SNR, but it is clear that with respect to
linearity, the 10th order converter is superior, even though the amount of work to
be done every sample period is equal for both systems.
The linearity of a Trellis SDM is more thoroughly examined in the next simulation.
The noise-shaping filter is a 3rd order Butterworth filter with f0 = 200kHz. The
input signal is a +3dB SACD sine wave with f = 1kHz. The high level input
signal and low filter order are chosen such, to make the harmonic distortion better
measurable. This system is tested with Trellis orders increasing from 1 to 16, using
M = 2, 4 or 8 candidates. All simulations were coherently averaged, to make
3. EFFICIENT TRELLIS ARCHITECTURE
37
119
Full Trellis
Standard SDM
118
117
SNR (dB)
116
M=4
115
114
M=8
113
112
M=2
111
110
0
5
10
Trellis order
15
20
Figure 3.7: SNR as a function of the used Trellis order N and the number of
candidates processed (M is 2, 4 or 8). The red ‘+’-marks are the simulation results
for a full Trellis. The ‘2’-mark on the left side is in case of a converter without
Trellis. All values are obtained after 32 power averages.
0
-20
-40
Power (dB)
-60
-80
-100
-120
Trellis N = 2, M = 4
-140
-160
Trelllis N = 10, M = 4
-180
-200
1000
10000
Frequency (Hz)
100000
log
Figure 3.8: Output power spectra after 512 power averages for a Trellis converter
with N = 2 and M = 4 (all possible candidates are processed), and a converter with
N = 10 and M = 4.
38
3. EFFICIENT TRELLIS ARCHITECTURE
the first four odd harmonics visible in the power spectrum. Figure 3.9 displays the
relative power in these harmonics as function of the Trellis order N and the efficiency
parameter M . As a reference, the ‘+’-marks indicate the harmonic distortion for full
Trellis converters, and the ‘2’-marks indicate converters without Trellis architecture,
but with a normal quantizer.
5th order harmonic distortion component (dB)
-135
-140
-145
-150
-155
M=2
-160
M=4
-165
M=8
-170
-175
2
4
6
8
Trellis order
10
-115
7th order harmonic distortion component (dB)
-115
Full Trellis
Standard SDM
-130
12
14
16
Full Trellis
Standard SDM
-125
M=2
-130
-135
M=8
-140
-145
-155
M=4
2
4
6
8
Trellis order
10
12
14
-125
M=2
-130
-135
-140
M=8
-145
-150
-155
M=4
2
4
6
8
Trellis order
10
12
14
16
-115
-120
-150
Full Trellis
Standard SDM
-120
-160
9th order harmonic distortion component (dB)
3rd order harmonic distortion component (dB)
-125
16
M=2
-120
-125
M=4
-130
-135
M=8
-140
-145
Full Trellis
Standard SDM
-150
2
4
6
8
Trellis order
10
12
14
16
Figure 3.9: Relative power in the 3rd , 5th , 7th and 9th order harmonic distortion
component as a function of the Trellis order N , for M equal to 2, 4 and 8. ‘+’marks indicate full Trellis systems, ‘2’-marks indicate standard converters.
The third harmonic is suppressed much better after application of the Trellis unit.
Even for M = 2, the gain is over 30 dB compared to the standard SDM. Looking
at the 5th and 7th harmonic, M = 2 performs better than the standard SDM, but
much worse compared to the systems with M ≥ 4. For the 9th order distortion
component, the Trellis architecture performs sometimes better, sometimes worse
than the classical SDM. The expectation is that for higher order distortion (like
11th or 13th harmonic), the standard SDM gives a better suppression than the Trellis
converter. The increase in power of high order distortion components, especially in
3. EFFICIENT TRELLIS ARCHITECTURE
39
case of small M , can be a disadvantage for the application of the efficient Trellis
architecture.
It was difficult to measure the harmonic distortion of full Trellis converters, because
full Trellis converters require a lot of computational power, and the number of
coherent averages necessary to make the distortion visible increases as well. Hence,
we can not compare full Trellis converters to efficient Trellis converters with the same
order N . Nonetheless, the results in figure 3.9 still show that the efficient converter
is preferred above the full Trellis, for a given amount of available computational
power. For example, the suppression of all harmonic components in case of an
efficient Trellis converter with N = 8, M = 8 is at least 20 dB more than the
suppression of the full Trellis with N = 3, although the required computational
power is equal for both systems.
3.3
Stability
One of the advantages of the Trellis architecture is the increased input range for
which the system remains stable. To investigate the stability, again a 5th order
Butterworth filter was used (f0 = 100 kHz and two additional zero’s at 11 kHz and
16 kHz). The input signal is a sine wave of 1 kHz, with amplitude A. The amplitude
is increased slowly, until the SDM becomes instable. This maximum input amplitude
for which the system is stable after 100000 sample periods is plotted in figure 3.10
as a function of the Trellis order. The ‘+’-marks indicate systems with a complete
Trellis structure (with M = 2N ), the other lines represent systems where the number
of candidates is restricted to 2, 4 or 32.
Even in case of M = 2, the input range increases with 11% compared to normal
SDM. For N ≤ 10, the Trellis with M = 32 is as good as the full Trellis. The lower
picture in figure 3.10 shows that the SINAD value at the maximum amplitude is
more or less constant: choosing a very small value for M , does not have a negative
influence on the SINAD value, thus both SNR and linearity are preserved when the
efficient architecture is used.
3.4
Filter frequency
As stated in the previous chapter, with Trellis converters it is possible to use more
aggressive noise-shaping filters, resulting in improved SNR values. To compare the
full Trellis architecture with the efficient converter, the simulation is repeated with
40
3. EFFICIENT TRELLIS ARCHITECTURE
0.90
Full Trellis
Standard SDM
M = 32
Maximum input amplitude
0.85
M=4
0.80
0.75
M=2
0.70
0.65
0.60
0
5
10
Trellis order
120
15
Full Trellis
Standard SDM
115
SINAD (dB)
20
M=2
M=4
110
M = 32
105
100
0
5
10
Trellis order
15
20
Figure 3.10: Maximum input amplitude (normalized to 1) for which the SDM is
stable as a function of N . Red ‘+’-marks indicate systems with all candidates
processed, other lines are for efficient implementations with M equal to 2, 4 or 32.
The ‘2’-mark indicates a SDM without Trellis algorithm. The lower picture shows
the SINAD that is achieved at the maximum input amplitude.
the same parameters: the noise shaper is a 5th order Butterworth filter with filter
frequency f0 . The maximum frequency f0 for which the converter remains stable
after processing of 100000 input samples, is plotted in figure 3.11. It is clear that a
3. EFFICIENT TRELLIS ARCHITECTURE
41
higher Trellis order makes it possible to use a higher filter frequency. For example,
the maximum frequency for a SDM without Trellis structure is 125 kHz, resulting
in 104.6 dB SNR, while the 3th order full Trellis (M = 8) achieves 110.0 dB SNR
at a filter frequency of 180 kHz. The new, efficient Trellis architecture with M = 8
is stable even for frequencies up to 225 kHz, giving a SNR of 116.1 dB. Increasing
the filter frequency does not only compensate for the worse SNR figures of Trellis
converters, it makes the SNR of Trellis converters even superior to standard SDM.
Full Trellis
Standard SDM
300
Maximum filter frequency (kHz)
M = 32
250
M=8
200
M=2
150
100
0
2
4
6
8
Trellis order
10
12
14
16
Figure 3.11: Maximum noise-shaping filter frequency for which the converter is
stable as a function of N . Red ‘+’-marks indicate systems with all candidates
processed, other lines are for efficient implementations with M equal to 2, 8 or 32.
The ‘2’-mark indicates a SDM without Trellis algorithm.
42
3. EFFICIENT TRELLIS ARCHITECTURE
Chapter 4
Model for output noise spectral
density
In this section, a linear model for the noise in the output power spectrum is presented
and compared to simulation results. Although the model is rather simple, it gives a
good approximation for the power spectrum of Trellis converters.
1
Model
Figure 4.1 shows the relation between the different signals and power spectra in case
of a Trellis structure.
x(t)
+
d(t)
-
H(z)
c(t)
y(t)
Figure 4.1: Trellis SDM: relation between input x(t), output y(t), error signal d(t)
and frequency weighted error signal c(t).
This model is developed for sine-wave input signals:
x(t) = A sin(2πf0 t)
4. MODEL FOR OUTPUT NOISE SPECTRAL DENSITY
(4.1)
43
The output signal y(t) is the final sequence created by the Trellis algorithm. Except
for the latency before the final output symbol is determined, there is no loop-delay
between the input signal x(t) and the output y(t), so the error signal d(t) is free of
signal components. The power spectrum of the filter output c(t) is thus assumed to
be white noise with a certain density W , leading to the spectrum of signal d(t):
Pc (f ) = W
(4.2)
W
|H(f )|2
Pd (f ) =
Z
Pd =
1
f
2 s
0
Z
= W
(4.3)
Pd (f )df
1
f
2 s
0
(4.4)
1
df
|H(f )|2
(4.5)
Now, we take into account that the output power is constant, and consists of signal,
noise and residual power at frequencies close to 21 fs . The signal power Px is known,
the residual power Pr is assumed to be constant.


Px = 12 A2

1
Pr = Const.
⇒ Pd = 1 − A2 − Pr

2

Py = 1
(4.6)
Combining equation 4.5 and 4.6 gives:
W
=
1 − 12 A2 − Pr
R 12 fs
0
⇒
Pd (f )
(4.7)
1
df
|H(f )|2
1 − 12 A2 − Pr
=
|H(f )|2
R 21 fs
0
1
df
|H(f )|2
(4.8)
The noise power spectrum in the output signal y(t) equals Pd (f ). The signal to
noise ratio (SNR) in the baseband (0 < f ≤ fb ) becomes:
SNR = 10 log
PS =
1 2
A
2
³
PN
=
³P ´
S
PN
, with
(4.10)
R fb
1
´ 0
df
1
|H(f )|2
1 − A2 − Pr R 1
f
2
1
2 s
df
0
44
(4.9)
(4.11)
|H(f )|2
4. MODEL FOR OUTPUT NOISE SPECTRAL DENSITY
With this model the noise output spectrum and the SNR can be determined when
the amplitude of the input signal and the transfer function H(z) are given. It is
also necessary to have an estimation of the amount of residual power at frequencies
close to 21 fs .
Two functions were implemented in Matlab. The first function calculates the output
power spectrum for a single input signal. The second function calculates the SNR
in the baseband as a function of the input amplitude. The source-code for both
functions is nothing more than a direct implementation of the equations above, and
does not need any additional explanation.
2
Simulation results
The noise model was tested with a 5th order Butterworth filter in combination with
a 10th order efficient Trellis structure. The input signal is a 1 kHz sine (0 dB SACD).
Figure 4.2 displays the calculated and simulated power spectrum. The actual value
for the residual power is obtained from the simulation results, and substituted in
the model. The model estimates a SNR of 111.8 dB, where the simulation resulted
in 111.9 dB.
0
Simulation
Model
-20
-40
Power (dB)
-60
-80
-100
-120
-140
-160
-180
-200
100
1000
10000
Frequency (Hz)
100000
log
Figure 4.2: Output power spectrum: simulation after 64 power averages (red) and
model (green).
4. MODEL FOR OUTPUT NOISE SPECTRAL DENSITY
45
A second simulation was performed on a 3rd order Butterworth filter, also with a
10th order efficient Trellis structure. The SNR is calculated as a function of the
input amplitude for a 1 kHz sine. The residual power is measured for a 0 dB SACD
signal, and assumed to be constant for all input amplitudes. The results in figure
4.3 (left) show that the model is only a rough estimation. When high input values
are applied, the residual power starts to decrease and the SDM is overloaded. Both
effects are ignored by the model. Nevertheless, figure 4.3 (right) shows that the
model gives a good estimation for the noise power spectrum in case of a 0 dB SACD
input signal.
80
75
0
Simulation
Model
Simulation
Model
-50
70
Power (dB)
SNR (dB)
65
60
55
-100
-150
50
45
-200
40
35
0.01
0.1
Input signal amplitude
1
log
-250
100
1000
10000
Frequency (Hz)
100000
log
Figure 4.3: SNR as a function of the input amplitude (left), and output power
spectrum for a 0 dB SACD input after 64 power averages (right).
46
4. MODEL FOR OUTPUT NOISE SPECTRAL DENSITY
Chapter 5
Future work
In this thesis, several new architectures have been introduced. Some of the problems
in these systems were not yet solved, other properties are not yet optimized. In this
chapter, two interesting items for further investigation are pointed out.
1
Invalid candidate removal
In all Trellis architectures (full, efficient and predictive), a certain Latency is necessary before the output symbol can be determined. In paragraph 2.3.5 the influence
of a too small Latency was discussed. It appeared that this situation should be
avoided at all costs, as it produces very audible distortion. The actual problem
is that, dependent on the input signal, a very long Latency is necessary. In fact,
even when Latency is extremely long, there is no guarantee that there are no input
signals which still require more Latency.
To solve this problem, it is necessary to take a ‘reasonable’ long Latency, which will
work for most input signals. This Latency is sufficient as long as the output history
for all candidates at time tpast = tcurrent − tlat is equal to either ‘0’ or ‘1’. When
not all candidates agree with each other at that time, the Latency is too short:
some candidates indicate that the new output symbol for time tpast should be ‘0’,
other candidates indicate that it should be ‘1’. Because the SDM has to produce an
output symbol for time tpast , it has to select one candidate, and produce the output
symbol according to that candidate. As soon as that is decided, all candidates with
a different output symbol become invalid, and should not be used in the future.
5. FUTURE WORK
47
Using one of the invalid candidates in the future means that the already produced
output symbol for time tpast was wrong: a bit-error is introduced. These bit-errors
can be prevented relatively simple: when a new output symbol Y is determined
by the SDM, all candidates indicating another output symbol than Y should be
removed from the internal list. This algorithm can be implemented easily in the
efficient Trellis SDM. In pseudo code, the new algorithm for the efficient converter
becomes:
Y := EfficientTrellisSDM (X)
X ← INPUT
StartNewlist
For (All OldCandidates)
C1 := CalculateTotalCosts (Path1 , X)
C2 := CalculateTotalCosts (Path2 , X)
AddToList (Path1 , C1 )
AddToList (Path2 , C2 )
For (All NewCandidates)
TotalCosts := TotalCosts - MinimumCosts
Cheap := CheapestCandidate
Y := Cheap.PathValue (tcurrent - tlat )
For (All NewCandidates A)
If (A.PathValue (tcurrent - tlat ) != Y)
RemoveFromList (A)
Y → OUTPUT
48
5. FUTURE WORK
2
Noise shaping cost function
The loop filter H(z) in the SDM is designed to be of the structure as depicted in
figure 5.1. The input signal is integrated several times ( 1−z1 −1 -blocks). The output
signals (Ii ) of the different integrators are weighted with constants ai to produce a
filter output signal. For the system in figure 5.1, the cost function becomes:
C(t) =
t
X
[c(τ )]2 =
τ =0
I0
1
1 - 1/z
a0
t ·X
2
X
τ =0
I1
1
1 - 1/z
¸2
ai Ii (τ )
(5.1)
i=0
I2
1
1 - 1/z
a1
a2
+
Figure 5.1: 3rd order example of filter H(z).
As the loop filter is placed in a feedback loop, the quantizer or the Trellis algorithm
tries to control the loop filter output to zero. A disadvantage of this filter structure,
is that the filter output can have a small value around zero, while the internal states
of the filter (Ii ) are not equal to zero. For example, in the following situation, the
filter output is zero, while the states inside the filter are far from zero:
a0 = 10 I0 = −60
a1 = 4 I1 = −100
a2 = 1 I2 = 1000
Although the filter output is controlled to zero, the internal states of the filter are
such, that the converter is likely to become instable after some time.
Instead of controlling the output of the filter to zero, it might be worthwhile to
control the weighted energy of the filter states to zero. The filter structure for
such a system is given in figure 5.2. Normally, the cost function is equal to the
cumulated second power of the output of the loop filter, now the function is equal
5. FUTURE WORK
49
to the cumulated output, as the filter performs the square-operation. The cost
function is given by the following formula:
C(t) =
t
X
[c(τ )] = b0 2
τ =0
t
X
[I0 (τ )]2 + b1 2
τ =0
I0
1
1 - 1/z
t
X
[I1 (τ )]2 + b2 2
τ =0
I1
1
1 - 1/z
t
X
[I2 (τ )]2
(5.2)
τ =0
I2
1
1 - 1/z
b0
b1
b2
|.|2
|.|2
|.|2
+
Figure 5.2: 3rd order example of weighted-energy filter.
Minimizing cost function C(t) now corresponds to minimizing the average weighted
energy of the integrator states inside the filter. The filter output is equal to zero
only if the energy in all states is equal to zero. Thus controlling the filter output to
zero results in controlling all filter states to zero, which prevents instability.
Another approximation to the system from figure 5.2 is given in figure 5.3. In
fact, there are three parallel filters. The cost function is a weighted function of the
outputs of these filters:
C(t) = α0 · C0 (t) + α1 · C1 (t) + α2 · C2 (t) , with
Ci (t) =
t
X
[Ii (τ )]2
(5.3)
(5.4)
τ =0
The cost function for this system is exactly the same as given before (equation 5.2),
where b20 , b21 and b22 are the weight constants for the three filter outputs (α0 , α1 and
α2 respectively).
To verify the behavior of the new filter system, it was tested with the settings of
a noise shaping function with a 5th order Butterworth characteristic. The filter
50
5. FUTURE WORK
1
1 - 1/z
I0
I1
1
(1 - 1/z)2
I2
1
3
(1 - 1/z)
Figure 5.3: Combination of three filters, weighted in one cost function.
parameters are: f0 = 50 kHz and two poles at 11 kHz and 16 kHz. A 1 kHz, 0 dB
SACD input signal was applied. The settings for the Trellis structure are N = 12
and M = 16. Figure 5.4 shows the (averaged) power spectrum. The signal to noise
ratio in the base band (below 20 kHz) is more than 123 dB. A second simulation was
performed to check linearity. After 256 coherent averages, no harmonic distortion
was visible. All distortion components are at least -165 dB below the signal level.
0
-20
-40
-60
Power (dB)
-80
-100
-120
-140
-160
-180
-200
-220
100
1000
10000
Frequency (Hz)
100000
1e+06
log
Figure 5.4: Output power spectrum after 32 power averages.
Although further investigation of this filter-type in combination with Trellis structures is necessary, the first impression about the signal to noise ratio and linearity
looks very promising.
5. FUTURE WORK
51
52
5. FUTURE WORK
Chapter 6
Summary
In this thesis, Trellis-type Sigma Delta Modulators are discussed. These systems
convert digital multi-bit signals to 1-bit digital output streams. The Trellis structure in these converters calculates several possible output streams, and chooses the
optimum output stream afterwards. This has a positive influence on the stability
and linearity of the converter.
Two different Trellis architectures are investigated. The first architecture is an
implementation of a full Trellis converter. A disadvantage of this type is that the
computational power and the memory usage increase exponentially in the Trellis
order N . For this reason, a new, efficient implementation of the Trellis architecture
is introduced. This converter achieves the same performance as the full Trellis
system, but with a significant reduction in the needed resources.
After the discussion of the Trellis converters, their software implementation and
simulation results, a linear model for the output power spectrum of Trellis converters
is presented.
6. SUMMARY
53
54
6. SUMMARY
Chapter 7
Conclusions
In previous work it has been shown that with increasing Trellis order N , better
specifications of a 1-bit audio stream (e.g., for application for Super Audio CD) can
be achieved. Most notably, linearity, input range, SNR and compression gain are
substantially improved compared to a classical Sigma Delta Modulator. However,
the number of states M in the Trellis structure equals 2N , causing the required
computational power to increase exponentially in N .
In practical situations, the available computational power limits the maximum value
of M and N , reducing the maximum signal improvement that can be achieved.
Therefore, a new, more efficient, Trellis architecture was introduced. In this architecture, the number of states M is made independent from N . Simulations showed
that using this new structure with constant M , but increasing N , all specifications (linearity, input range and maximum SNR) improve. Where the improvement
is nearly as good as has been shown earlier for a full Trellis structure, the computational requirements, at the same time, have dropped exponentially. A major
conclusion is that the new, efficient Trellis architecture exceeds by far the original
Trellis converter in performance, when the amount of computational power is fixed.
Also, a simplified linear model for the noise power-spectrum at the output of an
(efficient) Trellis converter was presented and verified. It was shown, that such a
linear model gives a highly accurate approximation for the actual spectrum.
7. CONCLUSIONS
55
56
7. CONCLUSIONS
Bibliography
[1] Hiroshi Kato. ‘Trellis Noise-Shaping Converters and 1-bit digital audio’, AES
112th Convention Paper 5615, 2002 May 10-13 Munich.
[2] Hawksford, M. O. J. ‘Time-quantized frequency modulation with time dispersive
codes for the generation of sigma-delta modulation’, AES 112th Convention
Paper 5618, 2002 May 10-13 Munich.
[3] Reefman, D., Janssen, E. ‘Enhanced Sigma Delta Structures for Super Audio
CD Applications’, AES 112th Convention Paper 5616, 2002 May 10-13 Munich.
[4] Viterbi, A. J. ‘Error Bounds for Convolutional Codes and an Asymptotically
Optimum Decoding Algorithm’, IEEE Transactions on information theory, vol.
IT-13, No. 2, April 1967.
BIBLIOGRAPHY
57
58
Appendices
59
Appendix A
dB SACD definition
In this thesis, the unit “dB SACD” is used as a measure of the amplitude of the
input signal of a Sigma Delta Modulator. In this appendix, a short introduction
about this unit is given, related to other units.
The digital, 1-bit output stream of converters is described with the values +1 and
−1 in this report. The (theoretically) maximum analog input range is given by the
range −1 ≤ A ≤ +1. However, nearly all Sigma Delta converters become instable
when the maximum input signal is applied. For that reason, for high quality SACD
records, all analog signals should be in the range −0.5 ≤ A ≤ +0.5. Any input
signal with a peak amplitude equal to 0.5 is called a “0 dB SACD” signal.
There are three ways to describe the magnitude of analog input signals:
- Time domain description, like x(t) = A · sin(2πf t). The value of A is limited
by −1 ≤ A ≤ +1 in theory, or to −0.5 ≤ A ≤ +0.5 for high quality SACD
recordings.
- “dBFS” value, this value expresses the power of the input signal relative to
the power of a full scale input in dB. A full scale input signal has power “1”
or 0 dBFS.
- “dB SACD” value, this value expresses the peak amplitude of the input
signal relative to the amplitude A = 0.5 in dB.
For illustration, the following table shows some signals and their magnitude expressed in “dBFS” and “dB SACD”.
A. DB SACD DEFINITION
61
Input signal
x(t) = sign(sin(2πf t))
x(t) = sin(2πf t)
x(t) = 12 sign(sin(2πf t))
x(t) = 12 sin(2πf t)
x(t) = 14 sin(2πf t)
dBFS value
0
-3
-6
-9
-15
dB SACD value
+6
+6
0
0
-6
The definition of the sign function is:
(
sign(x) =
62
+1 for x ≥ 0
−1 for x < 0
A. DB SACD DEFINITION
Appendix B
Path convergence example
In section 2.2.4 (page 17), a problem with respect to the convergence of paths inside
the Trellis structure was discussed. The implementation of the Trellis structure
from that chapter led to an invalid output sequence when a zero input-signal was
applied. A solution to that problem was also mentioned (section 3.2.2, page 34),
namely to use a variable candidate to determine the output symbol, instead of a
fixed candidate. The usage of a variable candidate was implemented in the algorithm
for efficient Trellis converters.
An example is shown in figure B.1. The three figures display the output power
spectrum when the input signal is equal to zero. The picture on top shows the
correct spectrum for a SDM without Trellis architecture. The picture in the middle
gives the output spectrum for a 5th order full Trellis, implemented with a fixed
candidate. A large DC component is visible, showing the convergence problem:
different paths in the Trellis structure exist, and will never converge to a single
solution. Although all of these paths give a good solution, the output sequence
is a mixture of the different paths, and that results in an invalid output. Finally,
in the third picture, the output spectrum for an efficient Trellis is visible. This
Trellis structure (with N = 5 and M = 32) is in fact a full Trellis as well. The
only difference is the way the output symbol is determined: instead of using a fixed
candidate, a variable candidate is used. Although the paths in the Trellis structure
will not converge in this system either, the output sequence follows one of those
paths, and a valid sequence is created.
B. PATH CONVERGENCE EXAMPLE
63
0
-50
Power (dB)
-100
-150
-200
-250
-300
100
1000
10000
Frequency (Hz)
100000
1e+06
log
0
-50
Power (dB)
-100
-150
-200
-250
-300
100
1000
10000
Frequency (Hz)
100000
1e+06
log
0
-50
Power (dB)
-100
-150
-200
-250
-300
100
1000
10000
Frequency (Hz)
100000
1e+06
log
Figure B.1: Output power spectrum for zero-input signal. A SDM without Trellis
(top), a Full 5th order Trellis (middle) and an efficient Trellis with N = 5, M = 32
(bottom).
64
B. PATH CONVERGENCE EXAMPLE
Appendix C
AES paper
A part of the work described in this thesis will be presented at the 114th convention
of the Audio Engineering Society. The paper preprint is included in this appendix.
C. AES PAPER
65