48
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 9, NO. 1, FEBRUARY 2021
Dynamic Bus Voltage Reconfiguration in a
Two-Stage Multiphase Converter
for Fast Transient
Arnab Acharya , Student Member, IEEE, V. Inder Kumar , Member, IEEE,
and Santanu Kapat , Senior Member, IEEE
Abstract— This article proposes a dynamic bus voltage
transition method in a two-stage multiphase buck converter for
48-V-to-point-of-load (PoL) applications. The proposed topology
uses a bank of precharged switching capacitors at the output of
the first-stage buck converter. This configuration helps to achieve
an immediate intermediate bus voltage transition while supplying
a (second-stage) multiphase buck converter. This can substantially speed up a large-signal transient recovery by adjusting the
bus voltage to its highest voltage level. Thereafter, near steady
state, the bus voltage is set to its (lower) optimum value for
improving the overall efficiency of the two-stage architecture.
A higher bus voltage can reduce the output capacitance for the
second-stage while retaining the (voltage) undershoot within the
desired limit, which can reduce recovery time and current overshoot during a step-reference transient. The first stage operates in
the open loop, while the second stage uses mixed-signal current
mode control using a field-programmable gate array (FPGA)
device. A hardware prototype of the proposed architecture is
made, and an improved performance is demonstrated using
simulation and experimental results.
Index
Terms— 48-V-to-point-of-load
(PoL)
converters,
efficiency, multiphase converters, intermediate bus voltage
transition, switched capacitors, two-stage architectures, ultrafast
transient.
I. I NTRODUCTION
E
FFICIENT power management is indispensable in data
centers [2], mobile processors, and a variety of portable
devices for reducing the power consumption and to achieve
high energy savings. Point-of-load (PoL) converters are used
to supply the majority of these loads with the objectives
to achieve a fast transient response and high energy efficiency. With a rapid progress in the 48-V dc bus due to
Manuscript received September 4, 2019; revised December 20, 2019 and
January 23, 2020; accepted January 23, 2020. Date of publication February 5,
2020; date of current version January 20, 2021. This work was financially supported in part by the Ministry of Human Resource Development (MHRD) and
in part by the Ministry of Electronics and Information Technology (MeitY),
Government of India. Recommended for publication by Associate Editor
Michael A. Andersen. This article was presented at the IEEE Applied
Power Electronics Conferene (APEC), March 2019. (Corresponding author:
Arnab Acharya.)
Arnab Acharya and Santanu Kapat are with the Department of Electrical Engineering, IIT Kharagpur, Kharagpur 721302, India (e-mail:
aa.physicsrkm@gmail.com; sn.kapat@gmail.com).
V. Inder Kumar is with the Department of Electrical, Computer and Energy
Engineering, University of Colorado at Boulder, Boulder, CO 80309 USA
(e-mail: indervedula@gmail.com).
Color versions of one or more of the figures in this article are available
online at https://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JESTPE.2020.2971710
its technical benefits [3], [4], numerous 48-V-to-direct-PoL
converters (both single and two stages) have been recently proposed [5], [6]. A single-stage nonisolated multiphase cascaded
buck converter [5] achieves superior transient performance.
However, phase shedding is not feasible in this architecture;
thus, the light-load efficiency is not optimized. Single-stage
transformer-based solutions [7], [8] achieve a very high conversion ratio. However, it remains a challenge to design a
transformer at high frequency, particularly at megahertz level,
when the skin effect becomes significant. This incurs more
copper losses into the system and very fine Litz wire printed
circuit board (PCB) windings need to be used. Furthermore,
a quasi-parallel architecture based on L LC resonant DCX
[8] is useful; however, it may not be effective if the (48 V)
bus voltage varies over a wide range from 36 to 60 V.
Thus, the design of high step-down single-stage architectures
remains a challenge. Single-stage solutions are efficient and
maintain a good balance between efficiency and power density
at low frequencies, while the performance degrades when the
switching frequency goes beyond a few megahertz [9].
Two-stage solutions [10], [11] are still preferred over single
stage because the overall efficiency can be optimized by optimizing individual stages. The benefits become more apparent
for switching beyond 500 kHz, which may vary for different
power switching devices [9]. The two-stage architecture by
VICOR [10] uses the factorized power architecture (FPA) with
an unregulated second stage. Two-stage architectures based
on the conventional buck, multiphase converters [11]–[14],
switched capacitors [15], and resonant switched-capacitor converters proposed in [16] and [17] are simple and useful. A
two-stage voltage regulator module (VRM) with an unregulated L LC DCX [12] is used for the first stage. This utilizes
dynamic bus voltage transition from 12 to 6 V to reduce the
core losses in the DCX and improve the light-load efficiency;
however, a small intermediate capacitor along with a rigorous
optimal control strategy is required for a fast transition from
12 to 6 V and back. Similarly, in a slightly different context, a
two-stage architecture in [11] uses the intermediate bus voltage
optimization based on the exact loss model to achieve a high
overall efficiency. It was reported in [18] that two different
choices of the intermediate bus voltage are required to achieve
high efficiency over a wide load range. Thus, there are further
scopes for performance and efficiency optimization.
This
article
proposes
a
two-stage
multiphase
converter-based architecture. This uses a bank of precharged
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ACHARYA et al.: DYNAMIC BUS VOLTAGE RECONFIGURATION IN A TWO-STAGE MULTIPHASE CONVERTER FOR FAST TRANSIENT
Fig. 1.
49
(a) Schematic and (b) control waveforms of the proposed architecture.
switching capacitors at the output of the first stage,
which provides a fast (bus) voltage transition to the highest
voltage level in order to achieve a fast step-up load transient
recovery. For a given load step size and for the same converter
design parameters, the proposed architecture can achieve a
twofold reduction in the transient settling time, significantly
reduced peak current overshoot, and a much smaller voltage
undershoot compared to a conventional two-stage multiphase
architecture. Furthermore, the efficiency of the overall
two-stage architecture is optimized by setting the bus voltage
to its lower (optimal) value.
This article is organized as follows. Section II introduces the
proposed architecture. Section III analyzes the improvement
in both load and reference transient performance along with
a simulation case study. Section IV discusses the efficiency
optimization by optimizing the bus voltage. Section V presents
the hardware implementation and experimental results to justify the merits of the proposed solution. Section VI concludes
this article.
II. P ROPOSED A RCHITECTURE
A. Operation of the Converter
Fig. 1(a) shows the schematic of the proposed architecture
consisting of an open-loop synchronous buck converter in the
first stage with a two-phase buck converter in the second stage,
which operates under peak current mode control (CMC). For
low-voltage and high-current applications, a multiphase buck
is preferred as it reduces the current stress in each phase
and also reduces the output capacitor size by virtue of ripple
cancellation. To meet the stringent transient requirements,
the second stage must offer a high slew rate for step load
and/or reference voltage transients. This can be achieved either
by increasing the bus voltage or decreasing the output inductance. The latter would increase conduction losses, which is
selected based on the power-stage design. Hence, an alternative
approach is to increase the bus voltage (v int ) instantaneously,
which cannot be achieved using a single capacitor. Therefore,
a bank of precharged switching capacitors is considered in
the intermediate bus, as shown in Fig. 1(a). Here, C1 and C2
are the capacitors connected in parallel along the respective
series switches sw1 and, sw2 , in which only one single
capacitor is connected at a time. The capacitors C1 and C2
are precharged to v c1 and v c2 , respectively, with v c1 < v c2 ,
and the intermediate bus is allowed to switch between C1 and
C2 depending upon the slew demand of the load. During a
Fig. 2.
Different modes of operation of the proposed architecture.
load step-up transient, sw2 is enabled for a short duration
as v c2 is at the highest precharged voltage, as shown
in Fig. 1(b). Thereafter, it is brought back to its nominal
operating point to v c1 for an optimal operation. Unlike [8]
and [11], the proposed topology inherently achieves a fast
load transient recovery for the second stage by dynamically
adjusting its input (intermediate bus) voltage to the highest
level. Thereafter, a lower voltage is used to optimize the
steady-state efficiency of the overall two-stage architecture.
1) Precharging and Leakage Charge Compensation: During
startup, C1 and C2 are sequentially charged using a sequence
of burst pulses using the first stage; thus, a separate precharging circuit is not needed. When sw1 is ON, C1 is connected and
the converter operates in mode−1 (in Fig. 2). Under this condition, the open-loop duty ratio for the first stage corresponds
to the voltage v c1 [see Fig. 1 (b)]. Hence, the capacitor C1 is
charged to v c1 . After few cycles, the switch sw1 is turned off
and C1 is disconnected and sw2 is turned on to connect C2
when the converter is under mode-2 of operation (in Fig. 2).
At this point, the open-loop duty ratio of the first stage is set
such that it corresponds to the voltage v c2 [see Fig. 1(b)]. In the
intermediate bus, only one capacitor is connected at a time, and
hence, any capacitor may get discharged through the leakage
path if it remains disconnected for a longer duration. The rate
of discharge depends on the time constant of each capacitor.
The time constant of an unloaded capacitor is primarily
determined by the insulation resistance of the capacitor, which
is typically in the order of M . Therefore, the time constant
of a capacitor is in the order of seconds, which means that
if any capacitor remains disconnected for more than 250 000
consecutive switching cycles ( f sw1 = 250 kHz), then the
capacitor voltage falls below a threshold limit and it requires
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50
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 9, NO. 1, FEBRUARY 2021
TABLE I
TABLE II
F IRST-S TAGE C OMPONENTS
I NTERMEDIATE -S TAGE C OMPONENTS
leakage charge compensation, which can be compensated by
activating each capacitor within its time constant. While this
will appear as a supply transient for the second stage, the use
of peak CMC makes the second-stage output voltage nearly
unaffected.
TABLE III
S ECOND -S TAGE C OMPONENTS
B. Power-Stage Design
The nominal input voltage to the power stage is 48 V and
the rated output voltage v 0 = 1 V with the rated load current
i load = 60 A. The entire design needs to be carried out by
considering the worst case scenario. The proposed one being
a two-stage architecture, each stage is considered at a time.
1) First-Stage Design: The first stage is a simple buck
converter with an input voltage of 48 V and the output (v int )
varies within two voltage levels v c1 = 5 V and v c2 = 12 V.
The component details are given in Table I. The switching
frequency ( f sw1 ) for this stage is 250 kHz. The input current
drawn by the converter is maximum when v int = v c1 . The
inductance value (L1st ) is calculated taking 20% ripple current
using the formulas
(v in − v int )D1
(1)
(L1st )min ≥
f sw1 i L1st
where D1 is the operating duty ratio. A 80-V 10-A
integrated half-bridge GaN module and driver with part number LMG5200 is used in the hardware as the power switch. The
integrated half-bridge plus driver module is used to minimize
the loop inductance.
2) Input Filter Design: The minimum value of a capacitor
required for the input filter is given by the empirical formula
(Cin )min
1.21 i tr 2 Lin
≥
v in 2
(2)
where i tr is the maximum current swing during a load step-up
transient, v in is the maximum allowable dip in the input
voltage, and Lin is the trace inductance.
3) Intermediate-Stage Design: Table II presents the component details of the intermediate state, which consists of two
capacitors C1 and C2 connected through switches sw1 and sw2
[see Fig. 1(a)] that are precharged to 5 and 12 V, respectively.
The switches sw1 and sw2 operate at very low switching
frequency and only carry the ripple capacitor current. The
voltage ripple (v int ) is taken to be 1% of the intermediate
voltage (v int ). For an optimal transient recovery, C1 and C2
can be calculated as
(Cn )min ≥
i int 2 L 1st
, where n ∈ {1, 2}.
2[v in − v int ]v cn
(3)
4) Second-Stage Multiphase Design: The second stage
is a two-phase buck converter with the component details
in Table III. The input to the second stage is the intermediate
voltage v int and output voltage is 1 V. As the maximum intermediate voltage is v c2 = 12 V, the power switch for the second
stage has to be rated accordingly. An integrated half-bridge
MOSFET module is used to minimize the loop inductance
and switch node ringing. Considering 20% inductor current
ripple for each phase (i L ), the value of the inductance can be
calculated as
(v int − v 0 )D2
(4)
(Ln )min ≥
f sw2 i L
where n ∈ {1, 2} and D2 is the operating duty ratio for
the second stage. The output capacitor (C) of the second
stage encounters the entire load current swing during a
step-up load transient. Taking 1% output voltage ripple (v 0 ),
the output capacitor for optimal transient recovery can be
formulated as
Cmin ≥
i 0 2 Ln
, where n ∈ {1, 2}.
2[v int − v 0 ]v 0
(5)
C. Practical Implementation Details
1) Positioning and Arrangement of the Intermediate
Switches: Two n-channel MOSFETs are sufficient for the
respective C1 and C2 . The switch sw2 should be connected
from source to drain to prevent any circulating current(s). If the
positions of C1 and C2 and sw1 and sw2 are interchanged,
i.e., placing the capacitors at the top and switches at the bottom
as shown in Fig. 3, then the source of this switch can be
directly connected to ground.
Hence, a simple low-side driver would be sufficient for
sw1 ; however, a high-side driver is needed for sw2 . A dedicated high-side bootstrap driver (part number LTC4440ES6)
is used. Both sw1 and sw2 carry only the ripple (capacitor) currents during steady state, thus having a negligible
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ACHARYA et al.: DYNAMIC BUS VOLTAGE RECONFIGURATION IN A TWO-STAGE MULTIPHASE CONVERTER FOR FAST TRANSIENT
Fig. 3.
driver.
Interchanging the position of C1 and sw1 allows using a low-side
Fig. 4.
51
Capacitor current waveform during a load step-up transient.
B. Reference Transient
impact on the converter steady-state efficiency. A small capacitor C L , as shown in Fig. 1(a), is used in parallel to the
capacitor bank to maintain the voltage regulation during the
dead time when v int is switching among different capacitor
terminals.
III. A NALYSIS OF T RANSIENT I MPROVEMENT AND
C ONTROLLER D ESIGN
From Fig. 6, the recovery time and peak current during a
step-up reference transient can be derived as
(TS )ref =
2LCv ref v int
(v int − v ref 1 ) · v ref1
(7)
(i pk )ref =
2Cv ref (v int − v ref 1 ) · v ref1
.
Lv int
(8)
A. Load Transient
Fig. 4 shows the waveforms of the second-stage capacitor
current and output voltage in Fig. 1(a) during a load stepup transient under time optimal control (TOC) for one phase
[19], [20]. For a load step size of i load, the total settling
time can be written as TS = t1 + t2 + t3 . Using capacitor charge balance, the optimal parameters can be obtained
as [1]
v int
v0
i load L
(TS )load =
(i pk )load = i load
1+
(v int −v 0 )
v0
v int
v 0 =
⇒ v diff×C =
i load2 L
i load2 L
; v diff =
2 (v int − v 0 ) C
2v 0 C
v diff
i load 2 L
2v 0
.
Fig. 5(d) and (e) shows the plots for variations in TS and i pk
with increasing v int , keeping the other parameters unchanged.
While i pk slightly increases with v int for a reference step
transient, this can be anticipated by decreasing C. The expression in (7) and√(8) shows that both (TS )ref and (i pk )ref are
proportional to C. Thus, TS and i pk are reduced by reducing
the value of C as shown in Fig. 5(f), and interestingly,
this can indeed be achieved using the proposed architecture,
as discussed in Section III-A.
C. Mixed-Signal Current Mode Control Architecture
(6)
It is evident from (6) that the recovery time TS , peak
capacitor current i pk , and output voltage undershoot v 0
during a load step-up transient under TOC can be reduced
using a higher v int . Fig. 5(a) and (b) shows the variation in
i pk and TS , and Fig. 5(c) shows the variation in v 0 with
varying v int under a load step-up transient for different sizes
of the load step i load . It is also clear that the effect is
more pronounced for a larger i load. The above-mentioned
expression in (6) is valid for a single-phase buck converter.
For an N-phase buck converter [21], [22], the settling time
and the peak √load current can be√formulated using [23] as
TS,mult = TS / N ; i pk,mult = i pk/ N , which further reduces
these parameters and achieves faster transient performance.
The expression in (6) shows that the product v diff × C is
constant for a given v 0 , where i load is specified by the load
[desired (v 0 )max = 100 mV]. Thus, the output capacitor can
be reduced by increasing v int , which may be helpful to speed
up the reference transient.
In the proposed architecture, the first stage is operating
under open loop, while the second stage is under peak CMC.
For the signal conditioning circuits, a differential pipeline
analog-to-digital converter (ADC) (AD9215) is used for sampling the output voltage (v 0 ). The ADC uses a differential
amplifier (AD8138) to convert the single-ended sensed output voltage into the differential form for the reduction of
common-mode noise. The sampled output voltage v 0 [n] is then
subtracted from the reference voltage v ref [n] to generate the
error signal e[n]. The digital controller G c (z) takes the error
as input and generates the digital current reference i ref [n].
A digital compensating ramp i ramp is used to ensure fast scale
stability. The final current reference i ref,final = i ref [n] − i ramp
is common for both the phases, and it is converted into an
equivalent analog voltage by using a 12-bit digital-to-analog
converter (DAC) (AD9762) followed by a differential amplifier
(AD8130). A high-speed comparator (TLV3501) is used to
compare with the sensed inductor currents. The comparator
output is then latched, and the dead-time circuit generates the
respective gate signals (see Fig. 7). A 10-m current sense
resistor is used to sense the inductor currents followed by a
current sense amplifier realized by op-amps (THS4012CD).
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IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 9, NO. 1, FEBRUARY 2021
Fig. 5.
Variation of TS and ipk with increasing v int under different load and reference transient conditions using the proposed topology.
Fig. 6.
Capacitor current waveform during a reference step-up transient.
D. Controller Design and Implementation
The closed-loop control architecture for the second stage
resembles a switching surface (σ ) in the form of
σ = k p (v ref − v 0 ) + ki
(v ref − v 0 )dτ − (i L − i load ) (9)
where i L is the effective instantaneous inductor current
under the assumption that the effective inductance during a
large-signal transient recovery becomes L/N, where N is
the number of phases. i load is the load current. Load current
feed-forward is needed to improve the transient performance
and reduce the output impedance [24], [25]. The load current
information is obtained in the case of a processor load using
the voltage identification (VID) command signal. The proportional gain k p is tuned using the large-signal tuning method
in [26]. A small integral gain ki is sufficient to minimize the
steady-state error.
E. Simulation Case Study
A simulation case study of the proposed converter is
shown here with the nominal parameters, as considered
in Table IV.
Fig. 7.
Mixed-signal CMC architecture.
Fig. 8(a) shows the load step-up transient response for
i load = 40 A. Using v int = 12 V, TS is reduced to almost
one-third and v 0 is also reduced compared to v int = 5 V.
Similarly, Fig. 8(b) shows the improvement in the reference
step-up transient for v ref = 0.5 V. However, i pk in Fig. 8(b)
increases with v int = 12 V. Reducing the capacitor value to
270 μF from 600 μF in Fig. 8(c) and using v int = 12 V, TS
is reduced, which also maintains the desired v 0 , as shown
in Fig. 8(a). Fig. 9 shows a comparison of reference transient
with a combination of v int = 5 V and C = 600 μF and v int =
12 V and C = 270 μF is shown. The proposed architecture
that can overcome conflicting can help in achieving both fast
load and reference transient performances.
IV. E FFICIENCY O PTIMIZATION AND O PTIMAL S ELECTION
OF I NTERMEDIATE B US VOLTAGE
The first-stage efficiency may be improved by increasing
v int ; however, the second-stage efficiency may degrade. This
requires an optimal choice for v int to improve the overall
efficiency, which is discussed next.
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ACHARYA et al.: DYNAMIC BUS VOLTAGE RECONFIGURATION IN A TWO-STAGE MULTIPHASE CONVERTER FOR FAST TRANSIENT
53
Fig. 8. Simulation results under (a) load transient with v int = 5 V and 12 V. (b) Reference transient with v int = 5 V and 12 V. (c) Load transient under
combination of v int = 5 V and C = 600 μF and v int = 12 V and C = 270 μF.
3) MOSFET Output Capacitance (Coss) Loss: The
MOSFET-related power loss in synchronous buck converters
is due to the FET output capacitance (Coss), which can be
formulated as
1
PCoss = Q oss v in f sw .
(15)
2
The values of different power-stage parasitic are extracted
from the respective datasheets using the method in [28] and
listed in Table V.
B. Efficiency Optimization
Fig. 9. Reference transient under combination of v int = 5 V and C = 600 μF
and v int = 12 V and C = 270 μF.
A. Types of Losses
1) Conduction and Switching/Driver Losses: The conduction loss for a buck converter can be formulated as
i L 2
Pcond. = rds,ON i out 2 +
(10)
12
where i out is the output current for the buck converter and
i L is the ripple inductor current. The switching losses can
be formulated as [27]
Q sw
Psw = v in i out f sw
(11)
ig
where f sw is the switching frequency, Q sw is the charge due
to the overlapping of voltage and current, and i g is the gate
current. Also, the gate drive loss can be written as
Pdrv = v drv f sw Q g
(12)
where v drv is the driver input voltage and Q g is the total gate
charge.
2) Dead-Time and Reverse Recovery Loss: The dead-time
loss is induced by the low-side body diode conduction during
dead times and can be calculated as
Pdead
time
= 2v ds td i out fsw
(13)
where td is the dead time. The diode reverse recovery loss is
due to the turn-off of the low-side FET body diode and the
loss associated can be written as
Prr = v in Q rr f sw
where Q rr is the reverse recovery charge.
(14)
The overall efficiency of the converter needs to be optimized
with respect to intermediate voltage. Fig. 10(a) shows the
experimental efficiency with the variation in load current with
both v int = 5 and 12 V. The maximum efficiency region is
observed to be around i load = 4 A. The experimental efficiency
of individual stages at 4-A load are plotted in Fig. 10(b). The
efficiencies of both the stages are multiplied to obtain the
overall (experimental) efficiency of the converter with respect
to v int . Using the loss expressions in (10)–(15), the overall loss
of the converter in terms of v int at a constant load of 4 A can
be analytically expressed as
d
Ptotal = a v int + b v int 4 − c v int 5 +
v int
e
f
g
h
j
−
−
+
−
+
(16)
v int 2
v int 3
v int 4
v int 6
v int 5
a = 0.0525 A; b = 3.85802 × 10−8 A/V3 ; c = −0.8036 ×
10−7 A/V4 d = 1.86657 AV2 ; e = 0.1169 AV3 ; f =
0.01426 AV4 ; g = 0.01244 AV5 ; h = 9.83655 × 10−4 AV6 ;
and j = 4.9183 × 10−4 AV7 .
Fig. 10(c) shows a comparison between the experimental
and analytical efficiencies at 4-A load. The analytical peak
efficiency is found to be 90.2 % at v int = 6 V, whereas the
experimental peak efficiency is 89.2% at v int = 5 V. From
Fig. 10(c), it is clear that the maximum overall efficiency is
obtained within 5 V ≤ v int ≤ 6 V. Hence, v int = 5 V has
been taken as the optimal intermediate bus voltage.
V. H ARDWARE I MPLEMENTATION AND P ERFORMANCE
A. Hardware Implementation
A hardware prototype of the proposed architecture is made,
which is shown in Fig. 11, and the control algorithms
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IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 9, NO. 1, FEBRUARY 2021
Fig. 10. (a) Experimental efficiency of the second stage with load current variation. (b) Experimental efficiency of the first and second stages individually
with the variation in v int at 4 A load. (c) Comparison of experimental and analytical efficiency of the overall converter with the variation in v int at 4-A load.
TABLE V
PARAMETERS FOR L OSS M ODELING
Fig. 11.
Hardware prototype of the proposed topology.
TABLE IV
PARAMETERS FOR S IMULATION C ASE S TUDY
are implemented using a Virtex-5 field-programmable gate
array (FPGA) device. The power-stage parameters for the test
setup are given in Table IV. All the test results are obtained
by implementing the closed-loop mixed-signal CMC technique
for the second-stage converter. The time period of the FPGA
controller clock is taken as tclk = 10 nS. The components used
for the power circuit are discussed in Section II-B.
B. Transient Performance
1) Load Transient Performance: Fig. 12(a) shows the
transient performance of the proposed converter with the
second-stage multiphase converter undergoing a step change
in load current from 0.5 to 25 A at v int = 5 V with
600-μF output capacitor (C). The parameters are found to
be TS = 5 μS and v 0 = 60 mV. Under the same condition,
Fig. 12(b) shows that faster recovery time (TS = 2.4 μS)
and smaller undershoot (v 0 = 40 mV) can be achieved
using a higher bus voltage v int = 12 V. While improving
the transient performance, a higher v int value results in higher
conduction loss due to larger current ripple, thereby degrading
the second-stage (steady-state) efficiency. By switching v int
using the proposed architecture in Figs. 1 and 12(c) shows both
the improved transient performance and steady-state efficiency
by switching v int from 5 to 12 V during a (large-signal)
load-step transient and bringing back to 5 V near steady state.
v int is switched from 5 to 12 V by enabling capacitor C2 ,
and v int continues to remain at v c2 for few consecutive cycles
shown in Fig. 12(c) to precharge C2 to its desired voltage of
12 V. Thereafter, v int is connected back to C1 and continues
to remain at v c1 until the arrival of the next transient.
2) Reference Transient Performance: Fig. 13(a) shows the
transient response using a single-phase second-stage operation
for a step change in reference voltage from 1 to 1.5 V using
v int = 5 V and C = 600 μF, and the parameters are found to
be TS = 14 μS and i pk = 28 A. Fig. 13(b) shows the reference
transient response using v int = 12 V for the same reference
step size and the same output capacitor, for which TS reduced
to 10 μS; however, i pk increased to 40 A. Fig. 13(c) shows the
switching of the v int from 5 to 12 V for a reference transient
and brought back to 5 V near steady state.
C. Comparative Performance Study
The zoomed areas marked as zone-1 and zone-2 in
Fig. 12(c) is shown in Fig. 14. A comparative study using
v int = 5 and 12 V is shown in Table VI which shows that
TS , v 0 , and i pk can be decreased by 52%, 33%, and 15%,
respectively, for a load step-up transient for a load step size
of 25 A using a higher v int . This is also consistent with the
expression in (6). While using the proposed topology TS for
a reference transient is also improved as shown in Table VII,
i pk increases by 42.85%, which is difficult to handle using
a single phase. The peak current (i pk ) can be drastically
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ACHARYA et al.: DYNAMIC BUS VOLTAGE RECONFIGURATION IN A TWO-STAGE MULTIPHASE CONVERTER FOR FAST TRANSIENT
55
Fig. 12. Load transient with multiphase operation and 600 μF output capacitor (C) under (a) v int = 5 V, (b) v int = 12 V, and (c) switching v int between
5 and 12 V.
Fig. 13. Reference transient with single phase and 600 μF output capacitor (C) under (a) v int = 5 V, (b) v int = 12 V, and (c) switching v int between
5 and 12 V.
TABLE VI
L OAD T RANSIENT (M ULTIPHASE )
TABLE VII
R EFERENCE T RANSIENT
excess capacitor energy can be recycled back to the source
using an additional path [29] or bypassed by introducing an
additional discharge path [30]. However, the proposed concept
of dynamic bus voltage transition can be applied along with
these arrangements to improve both the step-up and step-down
responses of the converter.
Fig. 14.
Zoomed-in view of areas. (a) zone-1 and (b) zone-2 marked
in Fig. 12(c).
reduced by reducing the output capacitor and/or using a
multiphase architecture by sharing the current among different
phases; interestingly, the proposed architecture offers both
the possibilities. The proposed architecture only improves the
voltage undershoot and does not reduces the overshoot. The
voltage overshoot during step down can only be reduced if the
D. Output Capacitance Reduction
It is discussed in Section III-A that C can be reduced using
a higher v int without violating the constraint in v 0 , which
is also shown in Fig. 8(c). Fig. 15(a) shows the reference
transient response using a two-phase converter for v ref =
0.5 V using a smaller output capacitance C = 270 μF and
v int = 12 V. Fig. 15(a) shows that using a multiphase operation
and reduced capacitance from 600 to 270 μF, the peak current
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56
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 9, NO. 1, FEBRUARY 2021
limits of the processor load. The proposed topology helps to
retain the improved steady-state efficiency by optimizing the
intermediate bus voltage. The proposed architecture would be
an attractive solution in high-current-low-voltage applications.
ACKNOWLEDGMENT
This work was carried out at the Embedded Power
Management Laboratory supported by IMPRINT (Project
Code - 7188) program.
R EFERENCES
Fig. 15. (a) Reference transient response with multiphase and reduced output
capacitor (C) of 270 μF and v int = 12 V. (b) Load transient with reduced
output capacitor (C = 270 μF) with v int switching from 5 to 12 V having
v 0 = 80 mV (within the desired range).
is drastically reduced from 40 to 13 A per phase. Also,
TS is reduced to 8 μS with 42.85% reduction compared
to that in Fig. 13(c), which is consistent with (7) and (8).
Fig. 15(b) shows the load transient response using a smaller
output capacitance (C = 270 μF), and the (output) voltage
undershoot of v 0 = 80 mV is found to be within the
acceptable range of 100 mV. Thus, the proposed bus voltage
configuration allows to significantly improve the transient
performance without affecting the steady-state efficiency in
dynamic voltage scaling (DVS) applications, which helps to
overcome conflicting power circuit design criteria in [23] by
reducing the output capacitor.
VI. C ONCLUSION
In this article, a dynamic intermediate bus voltage configuration was proposed using precharged switching capacitors
in a two-stage architecture, which could achieve fast transient
performance for both load and reference step-up transients.
The output voltage undershoot and the settling time were
found to be improved by 33% and 52%, respectively. The
proposed architecture allows further reduction in the output
capacitance, which helps to reduce the peak current for
step-reference transients in DVS applications. The benefits
of output capacitor reduction using the proposed architecture
are justified if the additional voltage overshoot resulting from
a load step-down transient is within the maximum tolerable
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Arnab Acharya (Student Member, IEEE) received
the B.Tech. degree in electrical engineering from
the West Bengal University of Technology, Kolkata,
India, in 2014. He is currently pursuing the M.S. (by
research) degree in electrical engineering from IIT
Kharagpur, Kharagpur, India.
He is currently working at Mercedes Benz
Research and Development, Bengaluru, India.
His research interests include power electronics,
48-V-to-1-V converters for datacenter and voltage
regulator module (VRM) applications, switchedcapacitor-based networks, digital control of power electronic converters,
medium voltage, and multilevel converters.
57
V. Inder Kumar (Member, IEEE) received the
B.Tech. degree in electrical engineering from the
College of Engineering, Jawaharlal Nehru Technological University, Hyderabad, India, in 2012,
and the M.Tech. and Ph.D. degrees in electrical
engineering from IIT Kharagpur, Kharagpur, India,
in 2014 and 2019, respectively. He is currently doing
his post-doctoral research at the Department of Electrical, Computer and Energy Engineering, University
of Colorado at Boulder, Boulder, CO, USA.
His research interests include analysis, modeling,
and nonlinear digital control of dc–dc power converters, and applications to
dynamic voltage scaling (DVS) and RF power amplifier.
Santanu Kapat (Senior Member, IEEE) received
the M.Tech. and Ph.D. degrees in electrical engineering from IIT Kharagpur, Kharagpur, India, in
2006 and 2010, respectively.
From August 2009 to July 2010, he was a Visiting
Scholar with the Department of Electrical and Computer Engineering, University of Illinois at UrbanaChampaign, Champaign, IL, USA. From August
2010 to July 2019, he was a Research Engineer
with GE Global Research, Bengaluru, India. From
August 2011 to July 2019, he was with the Electrical
Engineering Department (EED), IIT Kharagpur. From July to November
2019, he was with the EED, IIT Delhi (on LIEN from IIT Kharagpur),
New Delhi, India. He returned back to IIT Kharagpur in December 2019,
where he is currently an Associate Professor with EED. He developed the
Embedded Power Management Laboratory, IIT Kharagpur, in 2014. His
research interests include high-frequency power converters, high-performance
mixed-signal control, modeling, analysis, tuning, and nonlinear dynamics; and
applications to dynamic voltage scaling, 48-V-to-PoL converters, LED drivers,
audio amplifiers, data center, dc grid, chargers, and battery management
systems.
Dr. Kapat was a recipient of the INSA Young Scientist Medal and the
INAE Young Engineering Award in 2016, and the DAE Young Scientist
Research Award in 2014. He has been serving as an Associate Editor for the
IEEE T RANSACTIONS ON P OWER E LECTRONICS since 2015 and the IEEE
T RANSACTIONS ON CIRCUITS AND S YSTEMS —II: E XPRESS BRIEFS since
2018, and the Guest Associate Editor for the IEEE J OURNAL OF E MERGING
AND S ELECTED T OPICS IN P OWER E LECTRONICS since 2019.
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