Quarterly Report
a. Recipient Organization
Arizona State University
b. Reporting Period
c. Principal Investigator (PI)
Start: 10-01-2022
Vijay Vittal
End: 12-31-2022
SECTION I: EXECUTIVE SUMMARY
The executive summary (1-2 pages) should describe a high-level status on the items listed below.
The items can be discussed in further detail in their respective task sections below. This section
should be a mix of short paragraphs and bullet points. Please complete each of the following
sections and delete the yellow instructions when finished.
Technical Achievements
Impact:
State how the findings, results, or techniques developed in this project will continue to make an
impact on the specific fields of research in this project and in other disciplines, which may
include training and educational experiences; human resource development in science,
engineering, and technology; technology transfer; and societal impacts.
In the controls area ASU investigator Ayyanar regularly participated in biweekly working group
meetings for the Controls thrust. He has contributed to the ongoing development of the
Controls area document on UNIFI Universal Principles and Test Cases. Ayyanar also participates
in the UNIFI Specifications WG that works on defining interoperability guidelines and functional
requirements for GFM. In this quarter we have worked on an important aspect related to the
protection of power systems with high penetration of GFM IBRs. A dual-VOC structure for
independent control of positive and negative sequence currents through controlled negative
sequence current injection has been developed and verified in preliminary PLECS simulation.
Project Schedule Status:
Summarize the status of tasks with respect to the plan for the reporting and budget period.
Describe issues with achieving the planned activities identified in the project schedule and the
impact on the award budget-period end dates and the overall award period of performance. If
deviations from the schedule are noted, describe the impacts and mitigation alternatives that
are in place or planned. The quantitative impact to the timing of technical milestones, go/no go
decision points, and key deliverables should also be addressed.
4.3.1 Develop universal real-time GFM control architectures and algorithms:
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This subtask is on schedule. A Ph.D. student with expertise in power electronics hardware and
control development has been recruited to work on Tasks 4.3.1, 4.3.2 and 4.4.1. Progress in
this task is described briefly in Section II.
4.3.2 System-level and unit-level controller tuning methods:
This subtask is on schedule. A Ph.D. student with expertise in power electronics hardware and
control development has been recruited to work on Tasks 4.3.1, 4.3.2 and 4.4.1. Progress in
this task is described in detail with extensive simulation results in Section II.
4.4.1 Integration of GFM IBRs into Power Systems in CHIL Environment:
This subtask is on schedule. A Ph.D. student with expertise in power electronics hardware and
control development has been recruited to work on Tasks 4.3.1, 4.3.2 and 4.4.1. Progress in
this task is briefly described in Section II.
Project Budget Status:
Compare the actual project expenditures to the plan for the quarter and budget period. If any
actual cost category amount varies by more than 10% from planned amounts, describe the
variance, associated impacts, and proposed mitigation strategy. Include a history of budget
changes along with any anticipated ones. Clearly demarcate the two.
The team at ASU had one graduate student on board. The other graduate student will come on
board during Fall 2022 semester. The budge expenditure is in line with the proposed budget.
No budget changes are anticipated.
Issues:
Describe issues with completing the required project scope identified in the SOW, the impacts on
achieving project objectives and program goals, if applicable, and proposed mitigation
alternatives. The quantitative impact on achieving the technical milestones and on go/no go
decision points and key deliverables should also be addressed.
At present the tasks are on schedule and no changes or issues are anticipated.
Products and Publications:
Describe any Products or Publications
None at present.
SECTION II: TASKS AND MILESTONE PROGRESS
Provide a narrative (up to 20 pages) below of the status, progress, and results of each task for
the reporting period, with a focus on deliverables, technical milestones, quarterly progress
indicators (for labs), and go/no go decision points. Clearly identify work by task name and
number. Explicitly list associated milestones for each task and describe in detail the progress
toward achievement. If applicable, provide data measured to date associated with each metric,
and show how the assessment tool associated with the milestone has been exercised.
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Task Number and Title:
4.3.1 Develop universal real-time GFM control architectures and algorithms:
The scope for ASU under Task 4.3.1 in BP1 is to collaborate with UNIFI team to develop a
framework for a vendor-agnostic middle-layer to translate system level requirements to vendor
proprietary controllers and identify system-level protection requirements and generalized
secondary control metrics. Towards this goal, in Q4 we have focused on contributing to the
development of the Controls area document on “UNIFI Universal Principles & Test Cases” and in
developing precise definitions of terms and concepts used in the document. We have also
contributed to the ongoing development of the UNIFI Specifications document which is related
to this subtask.
We have also developed detailed models of single phase and three phase GFM inverters in the
power electronics simulation tool PLECS and have implemented several control strategies based
on a thorough literature search. In our Q4 work, a dual dispatchable architecture of VOC (dualdVOC) has been proposed and implemented using PLECS to mitigate the grid unbalanced
scenario. The conventional synchronous machine-based power system, during any unbalanced
condition, including asymmetrical faults, injects a negative sequence current which is sensed by
the sequence-based relays to ensure the requisite protection. It poses challenges regarding how
the similar behavior can be mimicked in GFM IBRs. The newly developed dual-dVOC based
control provides the flexibility to GFM inverters to inject a negative sequence current in a fully
controlled fashion.
Moreover, a discrete time simulation of the dVOC controlled GFM inverter has been developed
which will be useful for RT-box based real time HIL implementation.
4.3.2 System-level and unit-level controller tuning methods:
The scope for ASU under Task 4.3.2 in BP1 is to contribute to the development of Universal inputoutput model of GFM IBRs and generalized control parameters, and verification methods for
input-output behavior of GFM IBRs. Towards this goal, in Q4 we developed detailed PLECS
simulation models of dual-dVOC architecture using two separate loops for positive and negative
sequence components under an asymmetrical grid condition for a three-phase inverter. Fig. 1
shows the simulated three-phase inverter with the proposed control architecture.
Sequence component extraction:
An unbalanced three-phase system, without zero sequence components, is comprised of two
symmetrical constituents - positive and negative sequence components. The direction of rotation
for the negative sequence is opposite with respect to that of the positive sequence. Moreover,
with unbalancing, the abc domain signals transformed to dq domain no longer result in pure DC
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signals but contain a sinusoidal term of frequency twice the reference frequency. It can be
mathematically represented as [1],
Fig. 1 Proposed dual-dVOC-based control architecture for the protection of grid-forming
inverters under grid unbalancing
To filter out the double frequency oscillation a notch filter has been used. The transfer function
of the notch filter is given by,
𝑠 2 + 𝜔𝑛 2
𝐺(𝑠) = 2
𝑠 + 2𝜁𝜔𝑛 𝑠 + 𝜔𝑛 2
Where 𝜔𝑛 is the central frequency which is twice the line frequency (120 Hz).
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Fig. 2 shows the phasor representation of sequence component extraction method.
Fig. 2 Extraction of sequence components in the d-q frame for an unbalanced three-phase
system
The positive sequence current references are generated from the active and reactive power set
points (P*, Q*) using,
For the negative sequence loop, the current references are generated as,
−
𝑣𝑔,𝛼
𝑖𝛼∗−
[𝑖 ∗− ] = 𝑘𝑓 [𝑣 − ]
𝑔,𝛽
𝛽
Where 𝑘𝑓 is a factor which controls the negative sequence current injection.
Simulation results:
A three-phase 10 kVA inverter with 240 V (RMS) terminal voltage and LCL-filter is simulated with
the averaged model in PLECS with the proposed controller. The inverter is simulated for 5 kW
with a grid unbalancing of 5% in phase-a. Fig.3 shows the simulation arrangement and the
detailed simulation parameters are shown in Table-1.
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Fig. 3 Simulation arrangement for GFM inverter with dual-dVOC-based control under 5% grid
unbalancing in phase-a.
Simulation parameters :
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Fig.4 Programmable injection of negative sequence current using the proposed dual-dVOC
control under 5% grid unbalanced in phase-a with varying 𝑘𝑓
Fig.4 shows that with the proposed dual-dVOC based architecture, a controlled negative
sequence current injection can be done by varying the factor 𝑘𝑓 under an asymmetrical grid
condition which will suffice the requirements related to protection.
Fig. 5 Unbalanced inverter terminal voltage due to negative sequence voltage
injection using the proposed dual-dVOC control with 𝑘𝑓 = 1
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Fig.5 shows the necessary unbalance created at the inverter terminal due to the control which in
turn helps to inject the required negative sequence current. Fig. 6 shows the unbalance in the
inverter current.
Fig. 6 Unbalanced total filter current using the proposed dual-dVOC control
with 𝑘𝑓 = 1
4.4.1 Integration of GFM IBRs into Power Systems in CHIL Environment:
The scope for ASU under Task 4.4.1 in BP1 is to work on standardizing information formats and
testing framework for Controller in the loop (C-HIL) and Power hardware in the loop (P-HIL)
across the consortium and contribute to the development of evaluation protocols for GFM and
GFM aggregates utilizing hardware, P-HIL, and C-HIL at several scales but with a focus on
distribution systems. Our main effort under this task in Q4 is to develop the controller
implementation in PLECS using C-scripts and to run it in discrete time in such a way that it can be
readily used with minimal changes in the eventual C-HIL implementation using RT-box real-time
simulator and TI DSPs.
Fig. 7 Discrete time simulation arrangement using dVOC in PLECS
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The discrete time simulation arrangement for a single-phase inverter is shown in Fig. 7. The
fixed sampling step size used is 1/(60*10000) sec as shown in Fig. 8. The dispatchable VOC
(dVOC) [3,4] with complete active reactive power control have been implemented in C-script so
far as shown in Fig. 9.
Fig. 8 Fixed step simulation parameters in PLECS
Fig. 9 C-script implementation of dVOC in PLECS
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Trapezoidal integration rule:
𝑘𝑇𝑠
𝑣𝑐 [𝑘] − 𝑣𝑐 [𝑘 − 1] = ∫
𝑣𝑐̇ 𝑑𝑡 ≈
(𝑘−1)𝑇𝑠
𝑣𝑐̇ [𝑘] + 𝑣𝑐̇ [𝑘 − 1]
𝑇𝑠
2
𝑣𝑐̇ [𝑘] + 𝑣𝑐̇ [𝑘 − 1]
𝑇𝑠
2
𝑖𝐿̇ ′ [𝑘] + 𝑖𝐿̇ ′ [𝑘 − 1]
𝑖𝐿 [𝑘] = 𝑖𝐿 [𝑘 − 1] +
𝑇𝑠
2
1
𝑇𝑠 =
= 100 𝜇𝑠
𝑓𝑠𝑎𝑚
𝑣𝑐 [𝑘] = 𝑣𝑐 [𝑘 − 1] +
Where, k denotes the kth sampling instant.
𝑣𝛼 = 𝑘𝑣 𝑣𝑐
𝑣𝛽 = 𝑘𝑣 𝜀 𝑖𝐿
Discrete time simulation results:
A discrete time simulation with the aforementioned time-step has been done for a single-phase
GFM inverter as shown in Fig. 7. Below, Fig. 10 shows the synchronization performance of the
inverter with dVOC control. Fig. 11 and Fig. 12 show the active and reactive power tracking
performance respectively.
Fig. 10 Synchronization performance with discrete time simulation
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Fig. 11 Active power (P) tracking performance with discrete time simulation
Fig. 12 Reactive power (Q) tracking performance with discrete time simulation
Planned vs. Actual Activities:
Identify the status, progress, and accomplishment of planned tasks, and describe any significant
findings, conclusions, or developments. Highlight both positive and negative outcomes. Provide
sufficient technical details with figures and data to justify achievement of milestone(s) or
describe progress toward achievement.
4.2.1 Phasor domain models for GFM IBRs:
The work conducted during the fourth quarter is as scheduled, and the actual activities match
what was planned.
4.3.1 Develop universal real-time GFM control architectures and algorithms:
The work conducted during the fourth quarter is as scheduled and the actual activities match
what was planned.
4.3.2 System-level and unit-level controller tuning methods:
The work conducted during the fourth quarter is as scheduled and the actual activities match
what was planned.
4.4.1 Integration of GFM IBRs into Power Systems in CHIL Environment:
The work conducted during the fourth quarter is as scheduled and the actual activities match
what was planned.
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4.5.1 Graduate and Undergraduate Educational Material: The status on this task is as planned.
The material in the PSERC academy is a valuable resource for providing basic information
related to IBR principles and theory. Aspect of GFM capabilities will also be considered and
sources that provide such information will be included.
4.6.1 Development of Short Courses, Tutorials, and Seminars: ASU has provided two seminars
to the UNIFI series of seminars. One during Fall 2022 and the other during Spring 2022.
Explanation of Variance:
Discuss any differences between the planned activities and the actual accomplishments
described above. If applicable, explain the corrective actions that will be taken to mitigate
negative variances.
4.2.1 Phasor domain models for GFM IBRs: There was no variance in the actual
accomplishments.
4.3.1 Develop universal real-time GFM control architectures and algorithms: There was no
variance in the actual accomplishments.
4.3.2 System-level and unit-level controller tuning methods: There was no variance in the
actual accomplishments.
4.4.1 Integration of GFM IBRs into Power Systems in CHIL Environment: There was no
variance in the actual accomplishments.
4.5.1 Graduate and Undergraduate Educational Material: There was no variance in the actual
accomplishments.
4.6.1 Development of Short Courses, Tutorials, and Seminars: There was no variance in the
actual accomplishments
Plans for Next Reporting Period:
Discuss planned activities for the task over the course of the next reporting period.
4.2.1 Phasor domain models for GFM IBRs: Further model development and testing on the
GFM phasor domain model will continue. Analysis will be done to verify if any dynamic phasor
modeling is required to capture fast changes in variable in comparison to EMT simulations.
4.3.1 Develop universal real-time GFM control architectures and algorithms:
In next reporting period we will continue our analysis of dVOC based GFM control performance
in the real distribution feeder model and include a larger number of inverters. We will also
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investigate the performance of the newly proposed dual-dVOC architecture under actual
asymmetrical fault conditions.
4.3.2 System-level and unit-level controller tuning methods:
The main work in next reporting period under this subtask will be to study the performance of
dual-dVOC-based GFM under an actual asymmetrical fault. This will be done in detailed PLECS
simulations under different grid conditions and using switching model of the three-phase
inverter. Preliminary studies on the impact of different PWM methods will also be conducted
next quarter.
4.4.1 Integration of GFM IBRs into Power Systems in CHIL Environment:
In next reporting period we will develop ePHASORsim model of a basic GFM IBR to be used in
HIL experiments in future budget periods based on the PLECS models already developed.
4.5.1 Graduate and Undergraduate Educational Material: Work on identifying new material
on GFM inverters will continue during the next quarter
4.6.1 Development of Short Courses, Tutorials, and Seminars: Work will continue on
developing new seminar and tutorial material
References:
[1] B. Mahamedi, M. Eskandari, J. E. Fletcher, and J. Zhu, “Sequence based control strategy with
current limiting for the fault ride-through of inverter-interfaced distributed generators,” IEEE
Transactions on Sustainable Energy, vol. 11, no. 1, pp. 165–174, 2020.
[2] B. B. Johnson, M. Sinha, N. G. Ainsworth, F. Dörfler and S. V. Dhople, "Synthesizing Virtual
Oscillators to Control Islanded Inverters," in IEEE Transactions on Power Electronics, vol. 31, no.
8, pp. 6002-6015, Aug. 2016
[3] M. A. Awal, H. Yu, H. Tu, S. M. Lukic and I. Husain, "Hierarchical Control for Virtual Oscillator
Based Grid-Connected and Islanded Microgrids," in IEEE Transactions on Power Electronics, vol.
35, no. 1, pp. 988-1001, Jan. 2020
[4] M. Lu, S. Dutta, V. Purba, S. Dhople and B. Johnson, "A Pre-synchronization Strategy for Gridforming Virtual Oscillator Controlled Inverters," 2020 IEEE Energy Conversion Congress and
Exposition (ECCE), 2020, pp. 4308-4313
[5] M. Lu, S. Dutta, V. Purba, S. Dhople and B. Johnson, "A Grid-compatible Virtual Oscillator
Controller: Analysis and Design," 2019 IEEE Energy Conversion Congress and Exposition (ECCE),
2019, pp. 2643-2649
[6] IEEE standard for interconnection and interoperability of distributed energy re-sources with
associated electric power systems interfaces,” IEEE Std 1547-2018 (Revision of IEEE Std 15472003), pp. 1–138, 2018.
[7] M. Lu, S. Dutta and B. Johnson, "Self-Synchronizing Cascaded Inverters with Virtual Oscillator
Control," in IEEE Transactions on Power Electronics, vol. 37, no. 6, pp. 6424-6436, June 2022.
[8] M. Sondharangalla, N. Korada and R. Ayyanar, "Challenges and Solutions for Real-Time Phasor
Modeling of Large-scale Distribution Network with High PV Penetration," 2021 IEEE 48th
Photovoltaic Specialists Conference (PVSC), 2021, pp. 0630-0636,
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