VCD (Value Change Dump) Files
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The VCD (Value Change Dump) file format is specified in the IEEE
1364 standard.
The VCD file is an ASCII file containing header information, variable
definitions, and variable value changes.
VCD is commonly used in Verilog designs, and is controlled by VCD
system task calls in the Verilog source code.
The VCD files store information about value changes during
simulation for nets and registers.
Post processing tools can accept VCD file and visually display
variable hierarchy, value and strength in terms of waveform.
The value change dumping function is more efficient than
the $monitor task both in performance and in storage space.
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Verilog
VCD (Value Change Dump) Files
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The files saved in the VCD format contain several sections that
describe :
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File creation date and time
Version number
$timescale directive
Signals specification
$dumpvars task which defines which variables to dump into a file
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Verilog
Some useful System Tasks for VCD
operations with syntax
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$dumpfile(name)
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$dumpvars
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$dumpvars(level, list_of_variables_or_modules)
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$dumpoff
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$dumpon
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$dumpall
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$dumplimit
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$dumpflush
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Verilog
VCD System Tasks
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$dumpfile is used to create a VCD file
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$dumpfile; //Default file name is dump.vcd
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$dumpfile(“file name”);
$dumpvars is used to specify variables to be dumped
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$dumpvars(level, variables or modules);
level
how many level of hierarchy of modules has to be dumped to the
VCD file.
1
will dump all variables in current specified module, not modules
instantiated inside current specified module.
0
will dump all variables in current specified module and modules
instantiated inside current specified module.
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Verilog
VCD System Tasks
$dumpvars(1, TB);
//Dumps values of A and B
$dumpvars(1, TB.u3);
//Dumps values of C and D
$dumpvars(2, TB);
//Dumps values of A, B, C and D
$dumpvars(0, TB);
//Dumps values of A, B, C, D, E1 and E2
$dumpvars(1, TB.u3, A);
//Dumps values of A, C and D
$dumpvars(1, TB.u3.u1,TB.u3);
//Dumps value of C, D and E1
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Verilog
VCD System Tasks
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$dumpall is used to write current value of all selected variable
• $dumpall;
$dumpon/$dumpoff is used to resume or stop dumping
process
• $dumpoff;
//stop dumping
• $dumpon;
//resume dumping
$dumpflush is used to empty VCD buffer and ensure all data
in buffer is written to VCD file. It is used to update the dump
file while simulation is running.
• $dumpflush;
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Verilog
Keyword Inside VCD File
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$comment
$date
$timescale
$var
$scope
$end
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Verilog
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$dumpon
$dumpoff
$dumpvars
$dumpall
$version
$upscope
VCD Keywords
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$comment represents comment inside a VCD file
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$comment This is the comment $end
$comment Multi-line Comment1
Multi-line Comment2 $end
$timescale specifies time scale which was used during
simulation
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$timescale time_number time_unit $end
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Verilog
VCD Keywords
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$date specifies the date on which VCD file was
created
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$date data_in_text_format $end
$upscope indicates change of scope to next higher
level in design hierarchy.
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$upscope $end
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Verilog
VCD Keywords
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$var section specifies properties and identification
code of variable been dumped.
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$scope specifies scope of variable been dumped
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$var var_type size identifier_code var_name $end
$scope module modulename/instance_name $end
$version indicates version of VCD writer and system
task $dumpfile used to create the file
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$version version_text system_task $end
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Verilog
Design Example
module comb_logic (a, b, c, d, e);
input a, b, c, d;
output e;
wire x, y;
assign x= a & b;
assign y= c | d;
assign e= x ^ y;
endmodule
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Verilog
VCD Test Bench (1/3)
module testbench;
reg a, b, c, d;
wire e;
comb_logic u0 (a, b, c, d, e);
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VCD Test Bench (2/3)
// VCD initial block
initial
begin
$dumpfile;
$dumpvars(1, testbench, u0.x, u0.y);
#20 $dumpoff;
#30 $dumpon;
#5 $dumpall;
end
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Verilog
VCD Test Bench (3/3)
initial
begin
forever
begin
a=$random; b=$random;
c=$random; d=$random;
#3;
end
end
endmodule
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Verilog
Questasim VCD Feature
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Creating VCD file without using Verilog System Tasks
vsim –novopt testbench
//Start TB simulation
vcd file vcd_filename
//Create VCD file
vcd add var1 var2
//Add variables to be dumped
add wave *
//Add wave window
run time_value
//Run Simulation
Converting a VCD file to a waveform file
vcd2wlf vcd_filename wlf_filename.wlf
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Verilog