SILIGURI INSTITUTE OF TECHNOLOGY
DEPARTMENT OF ELECTRICAL ENGINEERING
SILIGURI -734009
Report
SAMPLING HOLD DEVICE
By
Name : Bikramaditya Roy
Roll No.: 11901621020
Course Title : Digital Control System
Course Code : PE-EE-601A
ACKNOWLEDGEMENT
I AM OVERWHELMED IN ALL HUMBLENESS AND GRATEFULNESS TO ACKNOWLEDGE
MY DEPTH TO ALL THOSE WHO HAVE HELPED ME TO PUT THESE IDEAS, WELL ABOVE
THE LEVEL OF SIMPLICITY AND INTO SOMETHING CONCRETE. I WOULD LIKE TO
EXPRESS MY SPECIAL THANKS OF GRATITUDE TO MY TEACHERS "MRS. SHRABANI
PAL" WHO GAVE ME THE GOLDEN OPPORTUNITY TO MAKE THIS WONDERFUL REPORT
ON THE TOPIC " SAMPLING HOLD DEVICES ", WHICH ALSO HELPED ME IN DOING A LOT
OF RESEARCH AND I CAME TO KNOW ABOUT SO MANY NEW THINGS. I AM REALLY
THANKFUL TO THEM FOR HELPED ME A LOT IN GATHERING DIFFERENT INFORMATION,
COLLECTING DATA AND GUIDING ME FROM TIME TO TIME IN MAKING THIS REPORT.
THANKING YOU,
Name : Bikramaditya Roy
Roll No : 11901621020
ABSTRACT
In this tutorial, we will learn about Sample and Hold Circuits. They are a
critical part of Analog to Digital Converters and help in accurate conversion
of analog signals to digital signals. We will see a simple sample and hold
circuit, its working, different types of circuit implementations and some of the
important performance parameters.
Table of Contents
I.
II.
Definition and Introduction
Basic sample and holding circuit
III.
Working of Sample and Hold Circuit
IV.
Types of Sample and Hold Circuits
V.
VI.
VII.
VIII.
IX.
X.
Analog Switch
Performance Parameters
Advantages
Applications of Sample and Hold Circuit
Conclusion
References
Definition and Introduction
Sample and hold circuit is an electronic circuit which makes the samples of input voltage signals and
holds these samples signal for some very small time duration.
Sample and hold circuit is basically is an analog to digital converter circuit. Input voltage signals to be
sampled and hold for some duration (in microseconds) using the capacitor and give the output in the
form of digital pulse. Because this works by the holds the sampled analog input signal this is called the
sample and hold circuit. Holding of the signal is done using a capacitor called holding capacitor,
capacitor has the ability to store the voltage by charging until it will discharge. This charging and
storing property of the capacitor is used here for the holding of the signal.
Sample
Some Parts consider or take the values of a given continuous input signal at each different time is called
sample.
Hold
catch the sampled signals and take hold for a time t is called hold.
Sampling time
The time during which generates the samples of input signals called sampling time. This is usually 1us
to 14 u sec.
Holding time
The time during which the circuit holds the sampled value is called the holding time. Holding time to be
set according to the required for application.
Basic sample and holding circuit
A basic sample and hold circuit consists a switch and a capacitor. A combination of a control switch and
a capacitor is called a simple sample and hold circuit. Input voltage applied at the point Vin and then a
switch connected after that a capacitor connected between the switch and output. One side of the
capacitor is connected with the ground. A JFET or a MOSFET is used as a Control switch.
Working
When the switch is closed the connected capacitor charged and when the switch is opened the capacitor
will not get discharged because there is no path for discharging and then the capacitor takes to hold the
signal.
Basic sample and holding circuit
In this circuit two voltage follower circuit, a capacitor and A MOSFET connected. Input voltage given
at The control voltage is given on the gate terminal of MOSFET, here MOSFET is used as a switch. The
reason of using the Voltage follower circuit is this circuit gives output same as the input signal and there
is a very high input impedance so no load is considered at the input and the capacitator will also not get
discharged because of very high impedance at the input of the op-amp.
The MOSFET is used here as the control switch for applying the voltage pulse. The Gate terminal of
MOSFET is connected with a controlled pulsed signal generator. Astable multivibrator can be used to
produce frequency. This astable frequency switch ON-OFF Very fast the MOSFET. By the ON-OFF,
ON-OFF of the MOSFET a pulsed form of the input voltage signal is applied to the NON-Inverting
terminal of Op-amp. The capacitor will charge as a pulse signal gets for the 1 st pulse to its max level and
this level is HOLD for a definite time by the capacitor because this capacitor will not discharge. And
now the next pulse falls and the capacitor will again charge as this pulse voltage level and this level hold
and this process is continuously proceeding as per pulse signal and the amplitude level of the pulse
signal.
So, in this whole process, the output is sampled and also hold for a time duration, these are done by the
main capacitor used in this circuit. We know that the sampled signals are the digital signals, So we can
say that the sample and hold circuit converts analog or continuous-time signal into digital signals.
Working of Sample and Hold Circuit
As you can in the circuit diagram, we have used 2N4339 N-channel JFET, an op-amp, and a capacitor. A
command input (a PWM input) is connected to the Gate terminal of the 2N4339 transistor. As you can in
the circuit diagram, we have used 2N4339 N-channel JFET, an op-amp, and a capacitor. A command
input (a PWM input) is connected to the Gate terminal of the 2N4339 transistor. A diode 1N4007 is also
connected between command input and 2N4339 N-channel JFET.
Now, the question is why the diode is connected in reverse condition? Let me give you a brief introduction
about 2N4339. 2N4339 is an N-channel JFET with low noise and high gain. 2N4339 conducts (turn ON)
only when gate-to-source voltage is in range of -0.3v to -50v (max). Now, we have set the initial voltage
of command input to -15V and pulsed voltage to 15V. So, whenever the command input voltage is
negative the diode will be forward biased which cause the transistor to turns ON and vice versa.
The Op-amp 741 is used as a voltage follower here, because voltage follower generally has a high input
impedance and a low output impedance. This is used when the input signal is of low current becuase
voltage follower can supply sufficient current to the next stage.
So, whenever the command input is HIGH the transistor works as closed switch and at this moment the
capacitor starts charging to its peak value and stores the sample of input signal for the time transistor is in
on state. Now when the command input is LOW the transistor works as open switch and the capacitor will
experience high impedance and due to this it cannot get discharged and holds the charge for a particular
period of time. This time is known as Holding Period. And, the time during which the circuit samples
the input signal is called as the Sampling Period.
Types of Sample and Hold Circuits
Let us now see a few different types of Sample and Hold circuits. Note that all the below mentioned
circuits use JFET as the switch. During the sampling period, the JFET is turned ON and the charging in
the holding capacitor rises to the level of the input analog voltage.
At the end of the sampling period, the JFET is turned OFF and the holding capacitor is isolated from the
input signal. This makes sure that the output voltage is held constant at the value of the input voltage
irrespective of minor changes in the input value. To compensate for the low drop-out voltage across the
holding capacitor, two buffers (voltage followers) are used, one at the input and one at the output.
Analog Switch
Any FET like JFET or MOSFET can be used as an Analog Switch. In this discussion, we will
concentrate on JFET. The Gate-Source voltage VGS is responsible for switching the JFET.
When VGS is equal to 0V, the JFET acts as a closed switch as it operates in its Ohmic region.
When VGS is a large negative voltage (i.e. more negative than VGS(OFF)), the JFET acts as an open
switch as it is cut-off.
The switch can be either a Shunt Switch or a Series Switch, depending on its position with respect to
input and output. The following image shows a JFET configured as both a Shunt Switch and as a Series
Switch.
Types of Sample and Hold Circuits
Let us now see a few different types of Sample and Hold circuits. Note that all the below mentioned
circuits use JFET as the switch. During the sampling period, the JFET is turned ON and the charging in
the holding capacitor rises to the level of the input analog voltage.
At the end of the sampling period, the JFET is turned OFF and the holding capacitor is isolated from the
input signal. This makes sure that the output voltage is held constant at the value of the input voltage
irrespective of minor changes in the input value. To compensate for the low drop-out voltage across the
holding capacitor, two buffers (voltage followers) are used, one at the input and one at the output.
Types of Sample and Hold Circuits
Let us now see a few different types of Sample and Hold circuits. Note that all the below mentioned
circuits use JFET as the switch. During the sampling period, the JFET is turned ON and the charging in
the holding capacitor rises to the level of the input analog voltage. At the end of the sampling period, the
JFET is turned OFF and the holding capacitor is isolated constant at the value of the input voltage
irrespective of minor changes in the input value. To compensate for the low drop-out voltage across the
holding capacitor, two buffers (voltage followers) are used, one at the input and one at the output.from
the input signal.
Keeping this in mind, let us take a look at the first S/H Circuit. The following image shows an openloop type S/H Circuit.
As there is no feedback, this circuit is relatively faster than the coming circuits (which all are in closedloop configuration). But the feedback in the closed-loop architectures provide higher accuracy figures.
The acquisition time (discussed in the next section) must be as low as possible. It is dependent on three
factors:



The RC time constant, where R is the ON Resistance of the JFET (ron) and C is the holding
capacitor CH.
Maximum output current
Slew-rate of the Op-Amp. A slightly improved circuit than the first one is presented in the next
circuit. In this configuration, the ON Resistance of the JFET is brought into the feedback loop
and hence, the acquisition time is dependent on the other two factors.
The final circuit offers additional advantages than the previous circuit. The important one is that the
position of the holding capacitor is changed and as a result, the voltage at non-inverting terminal of
A2 is equal to the voltage across the capacitor divided by the open-loop gain of A2.
This ensure a faster charging time of the holding capacitor and subsequently a shorter acquisition time.
Performance Parameters
The performance of an S/H Circuit can be characterized by parameters that are commonly used for an
amplifier like Input Offset Voltage, Gain Error, Non-linearity and so on. But there are a few
characteristics that are specific to the S/H Circuits.
These characteristics are helpful in analyzing its performance during the transition from sampling mode
to hold mode (and vice versa) and also during hold mode operations. Let us understand these
characteristics with the help of the following image.
Acquisition Time (tac)
The time required for the charge in the holding capacitor to rise up to a level that is close to the input
voltage during the sampling is called acquisition time. It is affected by three factors:



The RC Time Constant
The Slew-Rate of the Op-Amp
The maximum output current of the Op-Amp
Aperture Time (tap)
The time delay between the initiation of Vo tracking the Vi and the initiation of the hold command is
called the Aperture Time. This delay is usually due to the propagation delays through the driver and the
switch circuits.
For a precise timing operation, the hold command must be initiated in advance by an amount of aperture
time.
Aperture Uncertainty (∆ tap)
The Aperture time will not be the same for all the sample and will vary from sample to sample. This
uncertainty is called Aperture Uncertainty. This will severely affect the advancing of the hold command.
Hold Mode Settling Time (ts)
The hold mode settling time is the time taken by the output Vo to settle within the specified error band
(usually 1%, 0.1% or 0.01%) after the application of hold command.
Hold Step
During the switching from sample mode to hold mode, there might an unwanted transfer of charge
between the switch and the holding capacitor (mainly due to the parasitic capacitances). This will affect
the capacitor voltage as well as the output voltage. This change in the output voltage from the desired
voltage is called Hold Step.
Feed through
Again, the parasitic capacitances in the switch may cause AC coupling between Vo and Vi in hold mode.
As a result, the output voltage may vary with changes in the input voltage and this is referred to as
feed through.
Droop
Voltage Droop is a phenomenon where the voltage across the holding capacitor drops down due to
leakage currents.
Advantages


It provides synchronization to all the channel present in multi-channel analog to digital
converter.
The possibility of cross-talk can also be reduced.

Applications of Sample and Hold Circuit
1. It is used in analog signal processing.
2. Also finds applications in digital voltmeter.
3. In the data conversion system as well as in sampling oscilloscopes.
4. In data distribution systems and analog to digital converters.
5. In filters used for signal construction.
This is all about the sample and hold circuit, introduction, circuit representation and working with
applications.
Conclusion
A complete beginner’s tutorial on Sample and Hold Circuit. You learned the importance of a sample and
hold circuit in Analog to Digital Converters, a simple S/H Circuit using a MOSFET and a Capacitor,
different types of Sample and Hold circuits, some important parameters which determine the
performance of an S/H circuit and also the applications of S&H Circuits.
References
1. https://www.electronicshub.org/sample-and-hold-circuit/
2. https://circuitdigest.com/electronic-circuits/sample-and-hold-circuit-op-amp