DESIGN AND INVESTIGATE A
LOW-POWER LINEAR-IN-DB
SBAND POWER DETECTOR
Masters Research Proposals by Ravanne Jules Guiliary
September, 2019
Contents
Introduction .......................................................................................................................................................2
Problem Statement............................................................................................................................................3
Significance of Research ....................................................................................................................................3
Objectives ..........................................................................................................................................................4
Literature Review...............................................................................................................................................4
Power detectors with CMOS technology .......................................................................................................4
Power detectors using Schottky diodes .........................................................................................................5
Methodology .....................................................................................................................................................6
1. Low-power amplitude detector fabrication...............................................................................................6
a. Power detector unit ...................................................................................................................................6
b. Principle of Operation ...............................................................................................................................7
c. Architecture of propose standard CMOS Technology amplitude detector ..............................................8
Conclusion .........................................................................................................................................................8
References .........................................................................................................................................................9
Introduction
The rapid growth of modern technology involving radio frequency (RF) and microwave
engineering in the agriculture industry and wireless communication have raise an awareness to
develop cheaper power detectors which has a high accuracy and low power consumption. Power
detectors are mainly used to detect the power of a transmitted signal. There has already been a
substantial amount of research in developing cheaper power detectors that operates in various
frequency range.
One of the simplest power detectors in the market for many years is fabricated using the Schottky
diode. Even though Schottky diode operates well at high frequencies, its application is limited as
it has a large parasitic capacitance which decrease its frequency range. From results obtained in
(Milanovic, V, Gaitan, M, Marshall, J & Zaghloul, M 1996), it was confirmed that accuracy of the
Schottky diode for the small device was restricted. This was because the parasitic capacitances
caused by the pads and metal lines couldn't be disregarded and in reality, dominated the
measurements. Another popular power detector circuit is bipolar junction transistor. This
technology has quite promising advantages but the fact that its production cost is high makes it
unadequate for mass production. Besides both the Schottky diode and the bipolar junction
parameters deteriorates over temperature.
CMOS the current technology that is which is being extensive used to manufacture power
detectors because of its low power consumption. This makes CMOS technology cheaper thus
appropriate for mass production. In (Kiela, K, Jurgo, M & Navickas, R 2013), a linear-in-dB power
detector was designed in 65nm CMOS technology which achieved a 74-dB dynamic range while
using 24 mW from a 1.2 power supply. The highest frequency detected for the IF signal was 57
MHz. It was also suggested that the results were promising but more research need to be done
for larger bandwidth detection without deteriorating the dynamic range.
As a result, this research proposal will accentuate on developing an affordable compact
lowpower amplitude detector to perform the signals gain and phase reading in the S-band
frequency. The S-band frequency which range between 2GHz to 4GHz because it has considerable
microwave applications such as in wireless communication and recently the agricultural industry.
Other factors such as noise will be investigated so that its effect on the accuracy of the reading is
reduced.
Problem Statement
Radio frequency and microwave applications in the S-band frequency is increasing at an
exponential rate which bring about more demand for accurate power detectors to track signal
power accurately. Even though nowadays power detectors are not only being used by big
companies but also by smaller institutions yet there is still a lack of an affordable accurate power
detectors. This is mainly because Schottky diodes are unavailable in many advanced low-cost
processes and so is its alternative the bipolar junction (J. Zhang, V. Fusco, Y. Zhang 2012).
Previous research carried out recently using the cheaper power detectors showed weak readings
which are riddled with noise. Then again, any power detector which is of better quality is too
expensive. Moreover, currently for is lack of research for power detectors in the S-band
frequency although it has various applications.
In order to address these challenges a compact, economic and accurate power detector which
operates in the S-band frequency need to be designed. This power detector should have a low
power consumption to improve power measurement accuracy. Consequently, CMOS technology
stand out as the preferred options due to its low power leakage. Furthermore, CMOS technology
involves different transistors size such as 130 nm and 90 nm. Therefore, depending on the
applications, the power detector can be fabricated as compact as possible.
Significance of Research
First of all, if an accurate power detector with low power consumption is achieved, this will greatly
improve the accuracy of power measurement in the S-band frequency range. Besides its
affordability will make it within the reach of small institution especially in the agriculture industry.
Currently there is high demand for instruments monitor the quality and performance of multiple
plantation crops. The S-band frequency is suitable because most design of microwave ring
resonators for agricultural applications operates in frequency ranging between 2 GHz and 4 GHz.
The proposed power detector could also be used to manufacture cheaper VNA’s which has
multiple important applications at present time. In a word this research will bring forward a
cheap compact power detector with low consumption that will help smaller institutions to have
accurate measurement in their applications at an affordable price.
Objectives
1. To design and build a compact low-power amplitude detector capable of reading up to
4GHz.
The first objective is to come with a possible schematic for our new power detector which
fulfill all the requirements we want it to achieve. CMOS technology will be used to build
the device so that the power consumption is low. Furthermore, the device must read
frequency up to 4GHZ.
2. To analyze the characteristics and accuracy of low-power amplitude detector via CMOS
technology.
Once a prototype of the device is fabricated, all the characteristic of the power detector
such as its gain and phase will be analyzed. The ideal transfer characteristic which will
show the relationship between the magnitude ratio and the output voltage will be
investigated to show whether it display satisfactory output reading. The accuracy of the
power detector should be similar to the datasheet.
Literature Review
Power detectors with CMOS technology
The design of power detector using Complementary Metal Oxide Semiconductor (CMOS)
technology has recently emerged. The development of practical test solutions in the gigahertz
range for contemporary and future system on chip (SoC) is an open problem that demands
further research. CMOS technology uses both the N-type and P-type transistors on the same
integrated circuits (IC), and it has a low power consumption which suits our design requirements.
Currently most researchers are going for CMOS technology due to its low-cost which makes it
adequate for mass production even though bipolar technologies perform better. For instance, in
(Choi et al. 2016), a power detector was designed using 28 nm CMOS with a wide dynamic range
(DR) and temperature variation compensation technique. The DR range was more than 40dB
from 700 MHz to 4GHz and with a power consumption ranging between 5.8 to 11.8mW.
Figure 1: schematic of power detector using CMOS technology (Choi et al. 2016)
The schematic illustrates a rms type power detector with a wide dynamic range. Squaring circuits
(SQRs) and cascading gain amplifiers (GAs) produced the required frequency range with a power
level segmented detection method (Choi et al. 2016).
Figure 2: Power detector output voltage over operating frequencies (Choi et al. 2016)
Figure 2 represents the output voltage versus input power at different frequencies such as 1 and
2.7 GHz of the power detector. The results obtained were promising and it was found that the
power output voltage is indifferent to the operating frequencies.
Power detectors using Schottky diodes
A different approach to fabricate power detectors instead of CMOS technology is using the
Schottky diode. In (Milanovic et al. 1996), a Schottky power detectors was design using n-well
CMOS foundry. Figure 3 illustrate a simplified diagram of the diode detector circuit which consists
of a 75-pF surface-mount capacitor, a Schottky diode on a CMOS chip and a 51 Ω surface-mount
matching resistor which were wire bonded to the diode and connected to 3.5 mm SMA
connectors. The RF power detector measurement are shown in figure 4 indicating that the power
detector cut off frequency is 600 MHz.
Figure 3: Simplified diagram of the diode detector circuit (Milanovic et al. 1996).
Figure 4: Frequency response of detector (Milanovic et al. 1996).
From this research it was noted that due to the high parasitic capacitance of the device make it
unsuitable for high frequency measurement. Besides because the devices were quite small, its
accuracy was limited.
Methodology
1. Low-power amplitude detector fabrication
a. Power detector unit
For the power detector unit design, the square-law principles for CMOS transistors will be
used to perform power detection. Figure 5 shows the power detector unit whereby
transistor M1 and M2 are identical and biased in the same environment. Transistor M1
will received the radio frequency signal. M1 and M2 will operate in the saturation region
as the drain potential is equal to the gate.
Figure 5: Power detector unit (Yijun Zhou & Chia 2008)
b. Principle of Operation
The RMS value gives you the equivalent heating power of a DC voltage of the same
magnitude. AC signal power in dB is given by
𝑉𝑟𝑚𝑠2
𝑃𝑜𝑤𝑒𝑟(𝑑𝐵𝑚) = 10𝑙𝑜𝑔10( 50 )
1 𝑚𝑊
Since a linear-in-decibel output is preferred, a logarithmic conversion of the rms value is
necessary. The gate to source voltage for the NMOSFETS M1 and M2 is kept close to the
threshold voltage (VTH). In case the VGS is lower than the VTH, diffusion current dominates
the MOS transistor and the drain current operates in the weak inversion region. IDS and
VGS relationship changes from square law to exponential when they operate in the weak
inversion region (Yijun Zhou & Chia 2008). When the inversion region of the transistors is
chosen appropriately, the RF signal power can be detect quite easily using the square-law
characteristic and then find its linear-in-decibel by its exponential characteristic.
Figure 6: Three inversion regions of operation of MOS transistors (Yijun Zhou & Chia 2008)
c. Architecture of propose standard CMOS Technology amplitude detector
The amplitude detector build using CMOS technology will have low power consumption
since it will only require current when the switches value change from 0 to 1 or 1 to 0.
The amplitude detector will ideally be used to handle very high frequencies of up to 40
GHz but will have greater and more accurate sensitivity in lower frequencies, around 10
GHz. Figure 7 shows our proposed schematic for the low amplitude detector which uses
a pair of NMOSFETS (M1 and M2) which will be able to read RF power.
Figure 7: Schematic for low-power amplitude detector
Resistors R1 and R2 will be able to realize ultra-wide-band operation and can supply the gate bias
voltage. Ultra-wide band (UWB) uses the frequency spectrum of 3.1 to 10.6GHz and features a
high-frequency bandwidth of more than 500MHz and very short pulse signals (<1ns) which lead
to very high data rates (Nie, W & Wang, Z 2016). The capacitors C1 and C2 are used to prevent
the flow of DC current. This proposed design will be capable of reading a significant power range
and outputting the value as a readable voltage.
Conclusion
This proposal has covered the initial points of this project, where a linear-DB low-power
amplitude detector will be fabricated using CMOS technology for low-power microwave
applications ranging between 2 GHz to 4 GHz (S-band frequency). It will provide a more
economical way to use microwave technology especially in the agricultural sector. Some of the
applications where our newly design power detector would be used are AM demodulation,
communication receivers, six port network analysers and automatic gain control. Lastly the
successfully fabricated device will be very portable due to its compact size and will promote
research in the microwave aquametric measurement.
References
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