Maximizing Verification ROI and Closure for Arm-Based Designs Part 2 – Static and Formal Verification © 2018 Synopsys, Inc. 1 Challenges in Arm-based SoC Design SoC Challenges Architecture System Power Software Reuse © 2018 Synopsys, Inc. 2 Must get the architecture right, can’t compensate later for a wrong architecture Must accelerate HW-SW integration and SoC validation Customer IP Challenges Functionality Interface Must verify the IP functionality, issues found early are less costly to resolve Must validate interfaces – minimize SoC integration issues later on Optimize and Verify Power in IP subsystems and in the context of the full SoC Start firmware development earlier, in parallel with hardware design and in context of real-world IO Achieve Time-To-Market by addressing SoC and IP challenges and smooth reuse/exchange of data between IP and SoC (design, verification methodology, stimulus, power intent, etc.) Agenda – Static Verification Introduction Static Verification for RTL Signoff Clock Domain Crossing Analysis Reset Domain Crossing Analysis Summary © 2018 Synopsys, Inc. 3 IP & SoC Design Risk Reduced with RTL Signoff Traditional Design Flow New IPs New NewIPs IP New IPs New IPs IP Existing New IPs New IPsIP 3rd Party With RTL Signoff New IPs New NewIPs IP Lint IP Integration New IPs New IPs IP Existing New IPs IPs IP rd Party 3New Power CDCRTLRDC Signoff for IP Explrn. LP DFT Power CDC RDC RTL Signoff for SoC LP Explrn. DFT IP Integration Lint Implementation (Synthesis, Place & Route) Design Effort Implementation (Synthesis, Place & Route) Design Effort • Multiple iterations, divergent process • Reduced iterations, convergent process • Significant design effort & schedule risk • Reduced design effort & schedule risk © 2018 Synopsys, Inc. 4 Customers Adopting Static Verification for RTL Signoff • SpyGlass widely adopted for RTL Signoff – 300+ customers • Integrated static verification platform – Rich set of checks for Lint, CDC, Power, DFT – Unified compile and debug – Scalable for billion+ gate SoC designs • Continued innovation in SpyGlass – Reset domain crossing (RDC) – Intelligent root cause analysis (Lint Turbo) – Hierarchical abstraction flow © 2018 Synopsys, Inc. 5 Correct RTL Delivered by Early Lint Analysis • Drives correct-by-construction RTL design by finding (and fixing) problems at source – Compliance to coding guidelines, STARC, OpenMore, Morelint, etc. – Synthesizability & simulation issues – Structural, logical and connectivity issues – Electrical rule checks • Verilog, VHDL, SystemVerilog and mixed RTL support • Structured methodology and templates help tackle design issues systematically • Comprehensive waiver support • Easy debug with cross-probe to RTL in SpyGlass GUI © 2018 Synopsys, Inc. 6 Improved Lint Root Cause Analysis for Faster RTL Signoff Mobile SoC Design Use Case • Problem – Many lint violations on large designs – The violations are instance based and valid – Designers could waive true issues due to the volume of violations reported • Goal – Focus on high impact violations and fix the root cause • Results – SpyGlass Lint Turbo reduced violations by 3X on complex million gate SoCs © 2018 Synopsys, Inc. 7 Typical Clock Domain Crossing (CDC) Bugs Metastability due to Missing Synchronizer Glitches introduced at RTL Synchronizer Required! A Glitch! B B C D A D C Re-Convergence of Synced Signals 01 Reset Synchronization 10 rst_n D1 D1 F1 F2 clk_A F3 X D2 rst_n o_rst_n clk_B clk_B F2 X D2 F6 A F7 F8 Y © 2018 Synopsys, Inc. clk_B 8 F3 o_rst_n Y 01 01 11 10 10 10 clk_A clk_B clk_B Synchronous De-assert Advanced CDC Methodology for RTL Signoff RTL SDC CDC Analysis Identify clock domains Identify CDC paths Persistent Violation Database Identify Synchronizers CDC Setup Interactive Advanced CDC Checks Divergence / Re-convergence Reset Check CDC Reporting TCL Debug (Design & CDC query) © 2018 Synopsys, Inc. 9 Report GUI Debug (violation browser, Schematic) CDC Challenges and Technology Evolution Leading Customers Adopting SpyGlass CDC Unified Compile & Debug RDC 300 Functional CDC 250 Hierarchical CDC Flow 200 Protocol Independent CDC Logos FIFO & Handshake 150 Convergence Checks Basic CDC Verification 100 Clock/Reset Checks 50 2002 © 2018 Synopsys, Inc. 10 2005 2010 2015 2018 3X Better Productivity with Hierarchical SoC Verification Debug & Fix IP Blocks IP DataSheet IP Flow Lint DFT CDC IP Flow IP DashBoard Abstract Models Model Validation in SoC Context IP1 IP1 SoC Flow w/ Abstract Models Abstraction IP3 IP1 Abstraction SoC DashBoard IP2 IP2 Abstraction IPn IPn Abstraction SoC Debug & Fix SoC Flow • Address next generation SoC capacity, run time, and methodology with 3X better productivity • Support highly configurable IPs going into multiple SoCs • Differentiates SoC integration issues vs. block/unit level issues © 2018 Synopsys, Inc. 11 RTL CDC Signoff at SoC for Fast TAT and Best QoR! Hierarchical CDC Flow at SoC Level • Problem – Millions of CDC violations at flat SoC level – Large run time & memory consumption on big (>50M Gate) designs – Changes to constraints or design requires rerunning complete flow • Goal – Focus on SoC level CDC issues only • Results – SpyGlass CDC abstract model flow adopted for SoC signoff with faster runtime and less memory © 2018 Synopsys, Inc. 12 The New Challenge - Reset Domain Crossing (RDC) • RDC Challenges are Similar to CDC which create metastable outputs & design failures • Metastability (Non deterministic value) scenarios caused by Asynchronous Reset Assertion Setup + hold time window FF1 q1 D FF2 d2 D Q RSTB RSTB CLK Q QB QB rst1 q2 rst2 Metastable value RDC Verification is also a MUST for RTL Signoff © 2018 Synopsys, Inc. 13 Design Techniques to Address RDC Issues Reset Control Logic Sequence Ensures RDC Correctness Gating Logic to ensure destination is disabled when source reset is active – Block A is reset before block B – RESET1 is ASSERTED AFTER RESET2 – 2nd flop is forced into reset state to Negate D pin’s Impact Block the Clock to Second Flop Add a synchronizer © 2018 Synopsys, Inc. 14 Synchronization Flops Market Leaders Using Static Verification © 2018 Synopsys, Inc. 15 Agenda – Formal Verification Introduction Formal Verification Apps SoC Connectivity Verification Case Study Arm protocol Verification with Assertion IP Summary © 2018 Synopsys, Inc. 16 How to Improve Verification Confidence • Simulation cycles aren’t scaling – Need to look at each problem differently Emulation Simulation • Let’s break down the verification problem – Verification plan consists of individual tasks – Some well suited for simulation – Some well suited for emulation – Some well suited for static/formal verification – Use the right task for the right problem • Why consider multiple tools in the verification flow? – Not all problems can be solved by the same approach – Use the right tool for the right problem – Find bugs, saves time and $$$ © 2018 Synopsys, Inc. 17 Formal Static Next Generation Formal Verification Architecture • Consistently higher performance and capacity – More bugs found, more proofs, larger designs – Unified coverage closure with VCS • Easier debug with Verdi – Weeks saved in faster root-cause analysis with Verdi – Easier adoption of Formal for simulation users • Displacing competition – Growing adoption at mobile, graphics, and processors – Deployed in 400+ projects • Aggressive roadmap – Strong team in place, 2X growth in investment – Increasing portfolio of formal apps © 2018 Synopsys, Inc. 18 VC Formal Verification Made Easier with Formal Apps Auto Checks Formal Aware Structural Design Analysis Formal Coverage Analyzer AEP Native integration in VCS FCA Validate correctness of configuration registers against specifications Common coverage debug with Verdi Easy setup and comprehensive checks Assertion IP Register Verification FRV Validate correctness of standard protocols VC Formal AIP Highest capacity for largest SoC’s Navigator Sequential Equivalence Connectivity Checking CC Catches bugs missed by other tools SEQ Design and Property Exploration in GUI NAV APB Faster setup with auto helper discovery Up to 8x faster than competition AHB-lite AHB (full) AHB5 Property Verification High Performance and High Capacity Property Convergence Formal Testbench Analyzer Security Verification FPV Identify Security Vulnerabilities FSV Formal testbench completeness High performance fault injection & analysis FTA AXI3 AXI4 ACE-lite ACE (full) © 2018 Synopsys, Inc. 19 AIP Stairway to Formal Verification • Formal Applications (Apps) solve specific problems very well • Easy to setup & use & debug • No need to know or write SVA/assertions • No need for formal background • Users can gradually get exposed to more advanced formal concepts © 2018 Synopsys, Inc. 20 Recent Technology Advances in Formal Verification Formal Signoff Advancements • Formal Core Coverage finds verification gaps • Formal Testbench Analyzer – native integration with Certitude • Intelligent fault scheduling: 10X performance improvement Formal Security Verification (FSV) • • © 2018 Synopsys, Inc. 21 Ensures security with no leakage or integrity vulnerabilities Automatically validates illegal access through standard bus protocols (AHB, APB, AXI) Formal Machine Learning • Regression Mode: Up to 10X increase in throughput with faster convergence • Faster property solving using supervised learning Formal SmartSearch • Significant productivity improvements in tool usage • Native search system in docs w/ Natural Language Processing • Context awareness with robust search techniques Formal SoC Connectivity Verification Use Case 5X Faster Verification Closure for Mobile SoC © 2018 Synopsys, Inc. 22 Assertion IP Optimized for Arm AMBA Standard Rapid Integration and Verification of IP supporting AMBA Protocols • High Performance Assertion IP (AIP) – Architected and optimized for formal verification – Tuned for faster convergence on VC Formal engines VC Formal AIP for AMBA APB AXI3 AHB-lite AXI4 AHB (full) ACE-lite AHB5 ACE (full) • Multi-platform support – Usable in Synopsys VC Formal & VCS simulation with debug in Verdi • Robust and mature – Functionally validated against Synopsys VIP portfolio – Asserts, assumes, and covers included – Enhanced property set beyond the standard list provided with AMBA AIP AIP Debug in Verdi GUI © 2018 Synopsys, Inc. 23 Formal Verification with Assertion IP Use Case Faster Verification Closure of Leading Microcontroller Designs • Assertion IPs help checking standard interfaces • Provides reliable & well documented set of protocol compliance properties • Easy configuration supported by both templates and user interface specification • Common architecture among AIP’s reduces learning curve © 2018 Synopsys, Inc. 24 Market Leaders Using Formal Verification Solution © 2018 Synopsys, Inc. 25 Thank You
