GOVERNMENT POLYTECHNIC HISAR
APPROVED BY AICTE NEW DELHI, AFFILIATED HSBTE PANCHKULA
DEPARTMENT OF COMPUTER ENGINEERING
DIGITAL ELECTRONICS LABORATORY
LAB MANUAL
III-SEMESTER
2018-2019
Prepared by:
RAJESH KUMAR
1|P ag e
Syllabus
DIGITAL ELECTRONICS LABORATORY
SEMESTER – III (CSE)
Number of Lecture
03 Hr Tutorial (Instructions)
Hours/Week
+ 03 Hours Laboratory
Exam Marks 50
Laboratory Experiments:
1.
Verification and interpretation of truth tables for AND, OR, NOT NAND, NOR and Exclusive
OR (EXOR) and Exclusive NOR(EXNOR) gates
2.
Realisation of logic functions with the help of NAND or NOR gates
3.
- To design a half adder using XOR and NAND gates and verification of its operation
- Construction of a full adder circuit using XOR and NAND gates and verify its operation
4.
Verification of truth table for positive edge triggered, negative edge triggered, level triggered
IC flip-flops (At least one IC each of D latch , D flip-flop, JK flip-flops).
5
Verification of truth table for encoder and decoder ICs, Mux and DeMux
6.
To design a 4 bit SISO, SIPO, PISO, PIPO shift registers using JK/D flip flops and
verification of their operation.
7.
To design a 4 bit ring counter and verify its operation.
8.
Use of Asynchronous Counter ICs (7490 or 7493)
2|P ag e
LIST OF CONTENTS
S. No.
Details
Page No.
1.
Introduction
5
2.
General Instructions
5-10
2.1 General discipline in the lab
2.2 Attendance
2.3 Preparation and Performance
2.4 Lab Reports
2.5 Learning Outcomes
2.6 Technical Information
3.
Details of Experiment
3.1 Experiment No. - 1
Verification and interpretation of truth tables for AND, OR, NOT 11-18
NAND,
NOR
and
Exclusive
OR
(EXOR)
and
Exclusive
NOR(EXNOR) gates
3.2 Experiment No. – 2
Realisation of logic functions with the help of NAND or NOR gates.
3.3 Experiment No.- 3
19-21
To design a half adder using XOR & NAND gates and verification of
its operation.
- Construction of a full adder circuit Using XOR & NAND gates and 22-24
verify its operation.
3.4 Experiment No.- 4
Verification of truth table for positive edge triggered negative edge 25-30
triggered, level triggered IC flip flop (At least one IC each of D latch,
D flip flop, JK flip flops.
3.5 Experiment No.- 5
Verification of truth table for encoder and decoder ICs, Mux and De
Mux.
3|P ag e
31-34
3.6 Experiment No.- 6
To design a 4 bit SISO, SIPO, PISO, PIPO shift registers using JK/D 35-38
flip flops and verification of their operation.
3.7 Experiment No.- 7
To design a 4 bit ring counter and verify its operation.
39-40
3.8 Experiment No.- 8
Use of Asynchronous Counter ICs (7490 or 7493)
41-43
4|P ag e
1.
INTRODUCTION
That ‘learning is a continuous process ‘cannot be overemphasized. The theoretical knowledge gained
during lecture sessions need to be strengthened through practical experimentation. Thus practical
makes an integral part of a learning process.
The purpose of conducting experiments can be stated as follows:
•
To get familiarization with the basic components, devices, electronic instruments, modules,
kits etc. used for constructing instrumentation circuits.
•
Circuit drawing using standard symbols as practiced in Instrumentation Technology
•
Making proper connection in the experimental kits/ modules as per the circuit diagram and
connection of appropriate power supply for energizing the circuits
•
Conducting experiments as per the guidelines and writing of results of observation
•
Verification of theoretical results through graphs or calculations

Han1erience on the experimental setup
2.
GENERAL INSTRUCTIONS
2.1 General discipline in the lab
•
Students must turn up in time and contact concerned faculty for the experiment they are
supposed to perform
•
Students will not be allowed after ten minutes from the scheduled time
•
Attendance in the laboratory is compulsory. For any absence, students have to fill up the
application form in format available in the lab indicating sufficient reasons.
•
In case the faculty is not convinced, he may report the matter to the management
•
Students will not leave the class till the period is over
•
Students must get the connection of the experimental setup verified before switching on the
power supply
•
After the experiment is over, the experimental kits/modules. DMM and any other tools issued
for the experiments should be returned to the course instructor
•
Students should maintain silence while performing the experiments. Should any necessity
arises for discussion amongst them, they should discuss with a very low pitch without
disturbing the adjacent groups
•
Students should not unnecessarily fiddle with the instruments knob or any other pot. In the
instruments which may disturb the calibration accuracy, range or zero etc.
5|P ag e
•
Violating the above code of conduct may attract disciplinary action.
•
Damaging lab equipment or removing any component from the lab may invite penalties and
strict disciplinary action.
2.2 Attendance
•
Attendance in the lab class is compulsory. As an incentive, certain percentage of lab marks is
allotted for attendance in the internal evaluation of lab performance.
•
Each group of students must write a satisfactory report for each lab experiments in order to
pass the course
•
Attendance will be duly recorded by the concerned faculty
•
Students should complete the experiments on the day allotted for the same
•
Failure to do so or any absence on that day may result in loosing marks in the evaluation
process of lab records
•
However, on the genuine ground, alternate time slot may be given to complete the
Experiment
•
Students should not attend a different lab group/section other than the one assigned at the
beginning of the session
•
On account of illness or some family problems, if a student misses his lab classes, he may be
assigned a different group to make up the losses in consultation with the concerned faculty
member/ lab instructor
2.3
•
Preparation and Performance
Students should come to the lab thoroughly prepared on the experiments they are assigned to
perform on that day
•
Faculty may check their preparation and understanding of the experiments. If not found
satisfactory, students may be debarred from doing the experiments
•
Students should record the experimental results and observation in the lab manual
•
Any instrument damaged or tools lost during experiments may attract punishment in the form
of fine or suspension from the class.
2.4
Lab Reports
•
Each student is required to write a complete report of the experiment he has performed and
bring to lab class for evaluation in the next working lab
•
Report should be written very clearly and lab record should be maintained neatly
6|P ag e
•
The lab report must contain the following:
1.
Duly completed title page
2.
Each report should include connection diagram, graphs, equations, calculations (where
applicable) etc.
3.
Standard symbols should be used to draw the diagrams
4.
Calculations & comparisons with appropriate equations and comments
5.
Observation can be included explaining your experience in conducting the experiments.
2.5 Learning Outcomes
After undergoing the subject, student will be able to:

Explain the importance of digitization.

Verify and interpret truth tables for all logic gates.

Realize all logic functions with NAND and NOR gates

Design half adder and full adder circuit

Demonstrate and design 4-bit adder, 2's complement subtractor

Verify and interpret truth tables for all flip flops.

Verify and interpret truth tables of multiplexer, demultiplexer, encoder and decoder ICs

Design and realize different asynchronous and synchronous counters

Design 4-bit SISO, PISO, SIPO, PIPO shift registers

Explain the features and applications of different memories.

Verify performance of different A/D and D/A converters.
2.6 Technical Information
There are two types of signals in electronics, analog and digital. When we refer to a voltage or current
as being analog in nature, we mean that the voltage or current, as the case may be, varies smoothly and
continuously. A digital signal is the one which does not varies continuously or smoothly. A digital
signal on the other hand is a series of pulses of rapidly changing levels of voltage or current, in which
change in level occurs in discrete steps or increments.
Positive Logic
Most of the systems use positive logic. This implies that 0V represents binary 0 and +5V represents
binary 1 level. In practice, however, since it is difficult to achieve these voltages precisely, circuits are
so designed that voltages less than 0.8V are considered to be low and voltages exceeding +2.5V are
taken as HIGH (binary 1). The range from 0.8 to 2.5V provides noise rejection.
7|P ag e
Negative Logic
If we assign the binary 1 state to the more negative of the two voltage level as we have a system which
is using negative logic.
Logic Circuits
Logic circuits fall into two main categories:
1.
Decision-making logic circuits and
2.
Logic circuits with memory.
In the first category comes the gates, basically AND, OR and NOT gates. Gates have two or more
inputs and a single output. They accept binary inputs and, after processing the inputs, produce a binary
output, which depends on the function it is intended for, and the information supplied at the inputs.
Gates are therefore called decision-making logic circuits.
Another type of logic circuit is one which has a memory. At the heart of a circuit with memory is a
bitable flip-flop. As this circuit has two stable states, which may be designated as binary 0 and binary
1 state, it could be considered as a memory storage device. Each flip-flop can store a single binary bit.
If many flip-flops are combined to form a memory bank, many binary bits of information can be
stored in them.
Some Basic Gates
AND, OR and NOT are three basic gates and any logic equation can realized by using these gates.
Two more gates are NAND, NOR by using only one type of gates, either NAND or NOR any logical
expression can be realized. For this reason NAND and NOR gates are known universal gates.
Karnaugh Map
The K-map is a systematic way of simplifying Boolean expressions. With the help of the K-map
method, we can find the simplest POS and SOP expression, which is known as the minimum
expression. The K-map provides a cookbook for simplification.
Just like the truth table, a K-map contains all the possible values of input variables and their
corresponding output values. However, in K-map, the values are stored in cells of the array. In each
cell, a binary value of each input variable is stored.
The K-map method is used for expressions containing 2, 3, 4, and 5 variables. For a higher number of
variables, there is another method used for simplification called the Quine-McClusky method. In K8|P ag e
map, the number of cells is similar to the total number of variable input combinations. For example, if
the number of variables is three, the number of cells is 2 3=8, and if the number of variables is four, the
number of cells is 24. The K-map takes the SOP and POS forms. The K-map grid is filled using 0's and
1's. The K-map is solved by making groups. There are the following steps used to solve the
expressions using K-map:
Multiplexer
Multiplexer is a combinational circuit that has maximum of 2 n data inputs, ‘n’ selection lines and
single output line. One of these data inputs will be connected to the output based on the values of
selection lines.
Since there are ‘n’ selection lines, there will be 2n possible combinations of zeros and ones. So, each
combination will select only one data input. Multiplexer is also called as Mux.
Demultiplexer
A demultiplexer (or demux) is a device that takes a single input line and routes it to one of several
digital output lines. A demultiplexer of 2n outputs has n select lines, which are used to select which
output line to send the input. A demultiplexer is also called a data distributor.
Types of Flip Flops
1. SR Flip Flop
The SR (Set-Reset) flip-flop is one of the simplest sequential circuits and consists of two gates
connected as shown in figure. Notice that the output of each gate is connected to one of the inputs of
the other gate, giving a form of positive feedback or ‘cross-coupling’.
The circuit has two active low inputs marked S and R, ‘NOT’ being indicated by the bar above the
letter, as well as two outputs, Q and Q.
9|P ag e
2. D Flip flop
D flip – flops are also called as “Delay flip – flop” or “Data flip – flop”. They are used to store 1 – bit
binary data. They are one of the widely used flip – flops in digital electronics. Apart from being the
basic memory element in digital systems, D flips – flops are also considered as Delay line elements
and Zero – Order Hold elements.
3. J-K FLIP FLOP
A JK flip-flop is a sequential bi-state single-bit memory device named after its inventor by Jack Kil.
In general it has one clock input pin (CLK), two data input pins (J and K), and two output pins (Q and
). JK flip-flop can either be triggered upon the leading-edge of the clock or on its trailing edge and
hence can either be positive- or negative- edge-triggered, respectively.
4. T-FLIP FLOP
In a J-K flip-flop if J = K =1, the resulting flip-flop is referred to as a T-type flip-flop. An S-R flip-flop
cannot be converted to a T-type flip-flop, since S = R = 1 is prohibited. T- flip-flop is called a toggle
flip-flop. Since output toggle when T = 1
COUNTER
Counter is a sequential circuit. A digital circuit which is used for a counting pulses is known counter.
Counter is the widest application of flip-flops. It is a group of flip-flops with a clock signal applied.
Counters are of two types.

Asynchronous or ripple counters.

Synchronous counters.
.
General Components used in Laboratory
1.
All experiments in Digital Electronics lab are performed on Bread Board. (It is used for
making electronics circuit temporarily for performing experiments).
2.
Other components used are ICs, LED display and connecting wires. Power supply of +5Vis
used in all the experiments.
3.
The students use IC tester to test each IC before performing the experiment.
10 | P a g e
Experiment No.- 1
Objective:
Verification and interpretation of truth tables for AND, OR, NOT, NAND, NOR, EXOR, EXNOR gates.
Apparatus Required
1.
2.
Bread board, Connecting wires, Power supply (+5Volt), LED display board.
IC 7400, 7402, 7404, 7408, 7432, 7486, 74810
Theory
AND, OR and NOT are three basic gates and any logic expression can be realized by using these
gates. Two more gates are NAND, NOR by using only one type of gates, either NAND or NOR any
logical expression can be realized. For this reason NAND and NOR gates are known as universal
gates.
1.
AND Gate
The circuit symbol, IC pin configuration and the truth table of AND gate shown below:
The logical “AND” statement in word is if any one of the inputs is ‘0’ then output is ‘0’. If A and B
are inputs the operation “A AND B” is written as AB.
Truth Table
A
B
C
0
0
1
1
0
1
0
1
0
0
0
1
11 | P a g e
Pin Diagram
2.
OR gate
Logical OR statement in words is if any one of the inputs is 1, then the output is 1. If A and B are
input result of logical operation “A OR B” is written as A+B the logical symbol and the truth table of
the or gate is shown below:
Truth Table
A
0
1
0
1
Pin Diagram
12 | P a g e
B
C
0
0
1
1
0
1
1
1
3.
NOT Gate
Logic operation “NOT” says that if input ‘A’ is ‘0’ the output ‘NOTA’ is ‘1’ and if ‘A’ is ‘1’ the
output “NOT A” is ‘0’. The logical symbol and the truth table is as shown below:
Truth Table
A
C
0
1
1
0
Pin Diagram
4.
NAND Gate
The NOT-AND operation is known as NAND operation. The logic symbol and the truth table of the
NAND gate is shown below in figure.
13 | P a g e
Truth Table
A
0
0
1
1
C=
B
0
1
0
1
C
1
1
1
0
Pin Diagram
5.
NOR Gate
The NOT-OR operation is known as NOR operation. The logic symbol and the truth table of the NOR
is shown below in figure.
Truth Table
A
B
C
0
0
1
1
0
1
0
1
1
0
0
0
14 | P a g e
Pin Diagram
6.
EX. OR Gate
Logical EX-OR statement in words is if either of the input is 1, then the output is 1. If both inputs are
0 or 1 then out put will be 0. If A and B are input result of logical operation A EXOR B is written as A
below:
Truth Table
A
B
C
0
0
1
1
0
1
0
1
0
1
1
0
Pin Diagram
15 | P a g e
7.
EX-NOR Gate
The EX-NOR gives high o/p for both inputs high. The EX-NOR is written as
C=
This operation is implemented using EXOR and invert gates. The basic logic circuit and symbol for
the EX-NOR are shown
Truth Table
A
0
0
1
1
Pin Diagram
B
C
0
1
0
1
1
0
0
1
Procedure
1.
Insert IC on the breadboard.
2.
Apply +5V at pin no. 14 and GND at pin 7.
16 | P a g e
3.
Apply inputs A and B at the appropriate pins mentioned in each pin diagram.
4.
Connect the output at pin mentioned in pin diagram to the LED.
5.
Switch on the supply and change the combination of A and B and observe the output at LED.
6.
Confirm whether the output you observe is same as given in the truth table.
7.
Repeat above steps for different gates.
Precautions
1.
2.
3.
Insert IC carefully in the bread board without damaging the pins.
Take care while supplying the voltage to the IC.
Keep in mind input and output pin of the IC.
Questions:
Q. 1
Why are NAND, NOR gates called as universal gates?
Ans.
Q. 2
The minimum no. of NAND gates required to implement the Boolean function A+A +A C
is equal to…………..
Ans.
Q. 3
Obtain logical expression for the following circuit:-
Ans.
Q. 4
Following voltage wave forms are applied at the inputs of 2 input AND gate & OR gate. Plot
the output waveforms of these gates.
Ans.
17 | P a g e
Q. 5
Make truth table for 3 I/P OR and NAND gates.
Ans. OR
NAND
Q. 6
Fill in the blanks
1.
The number of rows in a truth table of 4 variables is------------
2.
The no. of 3 I/P NAND gates in a 14-pin IC is--------
18 | P a g e
Experiment No.- 2
Objective:
Realisation of logic functions with the help of NAND or NOR gates.
Apparatus required
Bread board, Connecting wires, Power supply ( + 5Volt), LED display board. IC 7400, 7402
Theory
The XOR gate is a digital logic gate that implements exclusive disjunction. A HIGH output (1) results
if one, and only one, of the inputs to the gate is HIGH (1). If both inputs are LOW (0) or both are
HIGH (1), a LOW output (0) results.
XOR gate is short for exclusive OR. This means that precisely one input must be 1 (true) for the
output to be 1 (true).
If we consider the expression (A.B’ + A’.B), we can construct an XOR gate directly using AND, OR
and NOT gates. However, this approach requires five gates of three different kinds.
An XOR gate can be made from four NAND or five NOR gates in the configurations shown below. In
fact, both NAND and NOR gates are so-called "universal gates," and any logical function can be
constructed from either NAND logic or NOR logic alone.
Circuit Diagram
19 | P a g e
XOR gate contrasted using only NOR gates.
Truth Table
A
B
Q
0
0
0
0
1
1
1
0
1
1
1
0
Procedure
1.
Construct the circuit as per the 1st logic diagram (using only Nand gates).
2.
Connect the power supply and ground to VCC and GND respectively.
3.
Verify the truth table for XOR gate.
4.
Construct the circuit as per the 2nd logic diagram (using only Nor gates).
5.
Connect the power supply and ground to VCC and GND respectively.
6.
Verify the truth table for XOR gate.
Precautions
1.
Insert IC carefully in the base without damaging the pins.
2.
Take care while supplying the voltages to the IC.
3.
Keep in mind input and output pins of the IC while performing the experiment.
4.
Make neat and tight connections
Questions
Q. 1
Construct AND, OR, NOT gate using NAND gates.
Ans.
Q. 2
Write self dual expression of Boolean relation,
BC+AB +A
Ans.
Q. 3
Implement the following function with NAND and NOR logic
20 | P a g e
.
F=(A+ )( +D)
Ans.
Q. 4
Minimize the Boolean function ( +y)
(y+z)
Ans.
Q. 5` Make truth table for 3 I/P XOR and XNOR gates.
Ans. XOR
21 | P a g e
XNOR
Experiment No.- 3
Objective:
- To design a half adder using XOR & NAND gates and verification of its operation.
- Construction of a full adder circuit Using XOR & NAND gates and verify its operation.
Apparatus used
Bread board, Connecting wires, Power supply (+5Volt)
IC 7408, 7432, 7486, LED display board etc.
Theory
Half-Adder: Half adder is a logic circuit that accepts two binary digits on its inputs and produces the
binary digits on its outputs i.e. a sum bit & a carry bit. Half adder adds two 1-bit numbers.
Logic Symbol
INPUT
A
0
0
1
B
0
1
1
1
1
22 | P a g e
OUTPUT
Sum
car
0
0
1
0
1
0
0
1
Full Adder
Full adder is a logic circuit that accepts three inputs and generates two outputs a sum & carry. Full
adder adds three bit two 1-bit numbers & carry inputs from previous stage.
Truth Table
INPUT
B
A
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
OUTPUT
CI
0
1
0
1
0
1
0
1
Sum
0
1
1
0
1
0
0
1
CO
0
0
0
1
0
1
1
1
Procedure
1.
2.
3.
4.
5.
Construct the circuit as given in the logic diagrams.
Insert the ICs (AND, OR, EX-OR) on the bread board.
Give VCC & GND to all ICS.
Make all the connections.
Verify the truth tables as shown.
23 | P a g e
Precautions
1.
2.
3.
Insert IC carefully in the base without damaging the pins.
Take care while supplying the voltages to the IC.
Keep in mind input and output pins of the IC while performing the experiment.
Questions
Q. 1
Draw an adder to add two 4 bit Nos.
Ans.
Q. 2
Draw circuit of half adder using only NAND gates.
Ans.
Q. 3
Draw circuit diagram of full adder using only NAND gates.
Ans.
24 | P a g e
Experiment No.- 4
Objective:
Verification of truth table for positive edge triggered negative edge triggered, level
triggered IC flip flop (At least one IC each of D latch, D flip flop, JK flip flops
.
Apparatus used
Bread board, Connecting wires, Power supply (+ 5V), IC, 7402, 7408, 7476, LED display board, etc.
Theory
SR Flip Flop
Flip-flop is a device, which can store a binary bit indefinitely (as long power is delivered to the ckt.),
until directed by input signal to switch state.
Clocked S-R flip-flop consists of basic NAND/NOR gates & two AND gates as shown in fig &, logic
symbol is shown in fig.
Circuit Diagram
As long as the clock pulse clock is 0 the output of two AND gates remain 0. Information from
S & R input reaches the basic flip-flop when CP = 1.
25 | P a g e
When S = 1, R = 0 & CP = 1, Q = 1 i.e. it is a set state.
When S = 0, R = 1 then Q = 0 i.e. clear state.
When S = 0, R = 0 & CP = 1 there is no change in the output i.e. Q maintain its earlier state.
When S = 1, R = 1, CP = 1 both outputs go to 0 state of the flip-flop is indeterminate when CP is
removed.
Characteristics Table
S
R
Qn+1
0
0
Qn (No change)
0
1
0
1
0
1
1
1
X
D Flip flop
If we use only the middle two rows of the characteristics table of the SR flip flop we obtain a D type
flip flop. It has one input refered to as D input or data input. Q output of D flip flop is equal to the
input applied. Thus, the transfer of data from the input to the output is delayed and hence the names
the delay flip flop.
Circuit Diagram
26 | P a g e
Characteristics Table
D Input
Q n +1
0
0
1
1
J-K Flip-flop is probably the most widely used and universal flip-flop. The two Indeterminate state in
SR flip-flop are defined in J-k flip-flop.
In a J-K flip-flop if J = K =1, the resulting flip-flop is referred to as a T-type flip-flop. An S-R flipflop cannot be converted to a T-type flip-flop, since S = R = 1 is prohibited. T-flip-flop is called a
toggle flip-flop. Since output toggle when T = 1
Logic symbol & truth table for J-K flip-flop is shown in fig.
Characteristics Table for J-K and T flip flop
J
K
Qn+1
0
0
Qn (No change)
0
1
0
1
0
1
1
1
Qn‾
Input
‾‾Output
Tn
Qn+1
0
Qn (no change)
27 | P a g e
1
Qn
Asynchronous inputs over ride synchronous inputs in J-K flip-flop, J is set & K is for
clear, when
J=K=1, the F/F switches to its complement state.
Application
J-K flip-flop are widely used in many digital circuits. We will use J-K flip-flop especially in counters.
Truth table for 7476 IC
28 | P a g e
Mode of
operation
Asynchronous
Synchronous
Output
PS
CLR
CLK
J
K
Q
‾
Asynchronous
Set
0
1
X
X
X
1
0
Asynchronous
Reset
1
0
X
X
X
0
1
Prohibited
0
0
X
X
X
1
1
Hold
1
1
0
0
No change
Reset
1
1
0
1
0
1
Set
1
1
1
0
1
0
Toggle
1
1
1
1
Toggle
Procedure
1.
Construct the circuit as per logic diagram.
2.
Connect power supply and ground to (Vcc, GND).
3.
Verify the truth table for all the flip-flops.
Precautions
1.
Make neat and tight connections.
2.
Switch off the power supply when not in use.
3.
The IC should be inserted carefully without damaging its pins.
Questions
Q. 1
Explain race around condition. What is the practical solution to overcome it?
Ans.
Q.2
What is the difference between Latch and F/F.
Q. 3
fill in the blanks:
1.
In an SR flip flop s= R= 1........................ permitted.
2.
Preset and clear inputs are used in a flip flop for making Q= ......... and......respectively.
3.
An active low clear input clears the flip flop when it is ....................
4.
A chatter less switch can be implemented using a ..................
29 | P a g e
5.
6.
7.
8.
9.
10.
30 | P a g e
Registers can be designed using..............................
Flip Flop is a ..................element.
No. of Flip Flops required for storing n-bit of information is.............
In a JK F/F if J=K=1, its Q o/p will be .............when a clock pulse is applied.
In T F/F , T stands for ....................
In a T F/F, the Q o/p ...................when T=0 and clock pulse is applied.
Experiment No.- 5
Objective:
Verification of truth table for encoder and decoder ICs, Mux and De Mux.
Apparatus Required
Bread board, Connecting wires, Power supply (+ 5Volt)
IC 74151, 74138, LED display board, etc.
Software used:
ORCAD-PSpice
Theory
Multiplexer:
The Multiplexer is a logic circuit that gates one out of several inputs to a single output.
The input selected is controlled by a set of select lines. Demultiplexer is a logic circuit that gates one
data input and distributes it over several outputs.
Block Diagram of 8: 1 Mux
31 | P a g e
Truth Table
SELECT LINES
MSB
S₂
0
0
0
0
1
1
1
1
Mux Operation
S₁
0
0
1
1
0
0
1
1
LSB
OUTPUT
S₀
0
1
0
1
0
1
0
1
Y
1ₒ
1₁
1₂
1₃
1₄
1₅
1₆
1₇
1.
Insert IC 74151 on the IC base of the experimental board.
2.
Give +5V to pin no 16 and GND to the pin8.
3.
Pin 7of the 74151 is chip enable pin, which is active low i.e. the IC, will function only if pin
no.7 is low.
4.
Pin 4,3,2,1,15,14,13,12 are inputs to the Multiplexer Viz. Pin no.5 is output of the multiplexer
while pin 6 is the inverted output of pin 5. Pins 11,10,9 are select lines. S₀, S₁, S₂ respectively.
5.
Give inputs to the multiplexer using binary data switches.
6.
Vary the data on the select signal on pins S₀ S₁ and S₂.
7.
Observe the output on pin 5 and note down in the truth table.
32 | P a g e
Demultiplexer A demultiplexer performs the reverse operation of a multiplexer.It accepts one input
and steers it to one of the several outputs by means of the select lines. Like MUX we have 1:2, 1:4,1:8
and 1:16 DEMUX too.
Deultiplexers are commonly called decoders e.g. 1:4 DEMUX is also called 2-line to 4-line decoder.
A 1:16 DEMUX is called a 4-line to 16-line decoder.
Demux Operation
1.
Insert IC 74138 on the IC base of the experimental board.
2.
Give +5V to pin no 16 and GND to the pin 8.
3.
IC has multiple enable pins. (4,5,6) If E₁ = high or E₂ high or E₃ = low, all outputs will be
high.
For normal operation E₁ =E₂ = low & E₃ = high.
4.
Give inputs to demux on pins 1,2,3 (A₀, A₁, A₂), depending on value of input, out of the 8
output lines one (pin 15,14,13,12,11,10,9,7) will be active low.
5.
Vary the data on select signal on pins 1,2,3.
6.
Observe the output on pins & note down in the truth table.
Block Diagram of 1:8 Demux
Pin Diagram
33 | P a g e
Truth Table
INPUT
D
D
D
D
D
D
D
D
Precaution
SELECT LINES
MSB
LSB
A₂
A₁
A₀
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
OUTPUT
‾‾ ‾‾ ‾‾ ‾‾ ‾‾ ‾‾ ‾‾ ‾‾
Oₒ O₁ O₂ O₃ O₄ O₅ O₆ O₇
0
1
1
1
1
1
1
1
1 1
0 1
1 0
1
1
1
1
1 1
1 1
1 1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1.
Insert IC carefully in the base without damaging the pins.
2.
Take care while supplying the voltages to the IC.
3.
Keep in mind input and output pins of the IC while performing the experiment.
Questions
Q. 1
Draw truth tables of multiplexer and demultiplexer.
Ans.
Q. 2
Implement the following function using 4:1 Mux F=
Ans.
Q. 3
How multiplexer can work as an encoder?
Ans.
Q. 4
How demultiplexer can work as an decoder?
Ans.
Q. 5
What do you mean by priority encoder?
Ans.
34 | P a g e
(2,3,6).
Experiment No. 6
Objective:
To design a 4 bit SISO, SIPO, PISO, PIPO shift registers using JK/D flip flops and verification of their
operation.
Apparatus used
S. No.
1.
2.
3.
4.
5.
Components
D flip flop
AND gate
OR gate
Bread board/ logic trainer board
Connecting wires/patch cord
Specificity on
IC 7474
IC7408
IC 7432
Quality
4
6
3
1
1. Serial in Serial Out (SISO):
The serial in/serial out shift register accepts data serially – that is, one bit at a time on a simple line. It
produces the stored information on its output also in serial form. All the flip flops receive a common
clock pulse which causes the shift from one stage to the next.
The Q output of a D flip flop is connected to the D input of the flip flop to the left. Each clock pulse
shifts the contents of the register one bit position to the right. The serial input determines, what goes
into the right most flip flop during the shift.
Pin diagram of IC 7474
Circuit Diagram:
35 | P a g e
Truth Table: For a serial data input of 1101
S. No.
1
2
3
4
5
6
7
8
Clock
Pulse
1
2
3
4
5
6
7
8
D₀
1
1
0
1
X
X
X
X
Inputs
D₁
D₂
X
X
1
X
1
1
0
1
1
0
X
1
X
X
X
X
D₃
X
X
X
1
1
0
1
X
Q₀
1
1
0
1
X
1
0
X
Outputs
Q₁
Q₂
X
X
1
X
1
1
0
1
1
0
X
1
X
X
X
X
Q₃
X
X
X
1
1
0
1
X
Procedure:
1. Insert two 7474 ICs in the bread board.
2. Connect pin 14 to +5V (V ) supply and pin 7 is connected to ground.
3. Apply the connections as per the circuit diagrams.
4. Apply the input as shown is the table above and verify the truth table.
2. Serial In/Parallel out(SIPO) Shift Registers:
Data bits are entered serially (right- most bit first) into this type of register in the same manner as
Serial in/ Serial out shift register. The difference is the way in which the data bits are taken out of the
register; in the parallel output register, the output of each stage is available. Once the data are stored,
each bit appears on its respective output line, and all bits are available simultaneously, rather than on a
bit-by-bit basis as with the serial output. The effect of data movement from left to right through a shift
register can be presented graphically as
36 | P a g e
Circuit Diagram :
Truth Table: For a data input of 1101
Clock
Pulse
1
2
3
4
5
S. No.
1
2
3
4
5
D₀
1
1
0
1
X
Inputs
D₁
D₂
X
X
1
X
1
1
0
1
X
X
D₃
X
X
X
1
X
Q₀
1
1
0
1
1
Outputs
Q₁
Q₂
X
X
1
X
1
1
0
1
0
1
Q₃
X
X
X
1
1
Procedure:
1.
2.
3.
4.
Insert two 7474 ICs in the bread board.
Connect pin 14 to +5V (V ) supply and pin 7 is connected to ground.
Apply the connections as per the circuit diagrams.
Apply the input as shown in the table above and verify the truth table.
3. Paralled In/Serial Out (PISO) Shift Register:
For a register with paralled data inputs, the bits are entered simultaneously into their respective stages
on parallel lines rather on a bit-by-bit basis on one line as with serial data inputs. Figure below
illustrates a four- bit parallel in- serial out register. Notice that there are four data-input lines, D₀, D₁,
D₂, and D₃. And a SHIFT/LOAD input. SHIFT/LOAD input allows four bits to be entered in parallel
into the register. When SHIFT/LOAD input is LOW. And each data bit input is applied to the D input
os its respective flip- flop.
When SHIFT/LOAD is HIGH. Allowing the data bits to shift right from one stage to the next. The OR
gates allow either the normal shifting operation or the parallel data-entery operation, depending on
which AND gates are enabled by the level on the SHIFT/LOAD.
37 | P a g e
Circuit Diagram:
Truth Table: For data input of 1101
Inputs
Outputs
Clock Shift/
S. No.
Pulse Load D₀
D₁
D₂
D₃
Q₀
Q₁
Q₂
Q₃
1
1
0
1
1
0
1
X
X
X
X
2
2
1
X
1
1
0
1
1
0
1
3
3
1
X
X
1
1
X
1
1
0
4
4
1
X
X
X
1
X
X
1
1
5
5
1
X
X
X
X
X
X
X
1
4. Parallel In/ Parallel Out (PIPO) Shift Register : Figure below shows a parallel in/
parallel out shift register.
Circuit Diagram:
S. No.
1
2
38 | P a g e
Clock
Pulse
1
2
Truth Table : For data input of 1101
Inputs
Outputs
D₀
D₁
D₂
D₃
Q₀
Q₁
Q₂
1
1
0
1
X
X
X
X
X
X
X
1
1
0
Q₃
X
1
Experiment No.- 7
Objective:
To design a 4 bit ring counter and verify its operation.
Apparatus used
Bread board, Connecting wires, Power supply (+ 5Volt), IC 74194, LED display board, etc.
Ring Counter
Four – bit ring counter sequences
Straight ring/Over beck counter
Twisted ring/ Johnson counter
State Q₀
Q₁
Q₂
Q₃
State Q₀
Q₁
Q₂
Q₃
0
1
0
0
0
0
0
0
0
0
1
0
1
0
0
1
1
0
0
0
2
0
0
1
0
2
1
1
0
0
3
0
0
0
1
3
1
1
1
0
0
1
0
0
0
4
1
1
1
1
1
0
1
0
0
5
0
1
1
1
2
0
0
1
0
6
0
0
1
1
3
0
0
0
1
7
0
0
0
1
0
1
0
0
0
0
0
0
0
0
Procedure
1.
Insert IC 74194 on the breadboard.
2.
Give VCC to pin 16 and GND to pin 8.
39 | P a g e
3.
Give different inputs as per the truth table of shift register and verify the corresponding
outputs.
4.
For Ring Counter, apply the data 1000 at A, B, C and D respectively by using mode – S1 S0 as
1 1 for parallel output.
5.
Apply the clock pulse and verify the truth table for ring counter.
6.
Repeat the procedure for Johnson counter with the initial data 0000.
Precautions
1.
Connection should be tight.
3.
Ground and Vcc should be
Questions
Q. 1.
Draw the timing waveforms of a four stage Ring counter
Ans.
40 | P a g e
Experiment No.- 8
Objective:
Use of Asynchronous Counter ICs (7490 or 7493)
Apparatus used
Bread board, Connecting wires, Power supply (+ 5Volt)
IC, 7490, IC 7447, seven segment IC 542, LED display board, etc.
Theory
A counter is one of the most useful & versatile subsystem in a digital system. A counter driven by a
clock can be used to count number of cock cycles. Since the clock pulses occur at regular intervals, the
counter can be used as an instrument for measuring time & therefore period or frequency.
Functional Description
IC 7490 is a decade counter, it is a 4- bit ripple counter triggered by a high to low transition on the
clock inputs.
Device consists of four master slave J-K – flip-flops which are internally connected as shown in the
logic diagram. A gated AND a synchronous Master Reset (MR₁, MR₂) is provided which override the
clock & reset all the flip flops.
A gated AND asynchronous master set (MS₁, MS₂) overrides the clocks and the MR inputs and sets
the output to nine (HLLH).
During operation, the CP₁ input must be externally connected to then Q₀ output CP₀ input receives the
incoming count & ABCD count sequence is produced.
Pin Diagram
41 | P a g e
Circuit Diagram
Procedure
1.
2.
3.
4.
5.
Insert the ICs 7490, 7447, seven segments IC 542 in the bread board.
Give VCC & GND to the ICs.
Clear all flip flops& apply clock at pin 14 (CP₀)’
Connect pin 1 (CP₁)’ to pin 12 ( ₀)
Connect the Q₃, Q₂, Q₁, Qₒ output pins of decade counter to D,C,B,A pins of decoder IC 7447
respectively.
Mode Selection Table
Reset/Input
Output
MR₁
MR₂
MS₁
MS₂
Q₀
Q₁
Q₂
Q₃
H
H
L
X
L
L
L
L
H
H
X
L
L
L
L
L
X
X
H
H
H
L
L
H
L
X
L
X
COUNT
X
L
X
L
COUNT
L
X
X
L
COUNT
X
L
L
X
COUNT
Precautions
42 | P a g e
1. Connection should be tight.
2. Ground & Vcc should be proper.
Questions
Q. 1
what is the difference between synchronous and asynchronous counter?
S. No.
Synchronous Counter
Asynchronous Counter
Q. 2 Fill in the blanks.
1. Race condition may exist in .........................sequential circuits.
2. The minimum no. of flip flop required for decade counter is ........................
3. The cascade of divide by 5 counter followed by divide by 2 counter is in state 0000. When a
clock pluse is applied its state will be................. Assume negative edge triggered circuits.
4. A ripple counter is ...............................sequential circuit.
5. The modulo of a 4 bit binary counter is .........................
43 | P a g e
44 | P a g e