Microelectronics Journal 53 (2016) 1–7
Contents lists available at ScienceDirect
Microelectronics Journal
journal homepage: www.elsevier.com/locate/mejo
Static and dynamic modeling of organic thin-film transistors for circuit
design
Li Jiang a,b,n, Ezz EI-Masry a, Ian G. Hill b
a
b
Department of Electrical & Computer Engineering, Dalhousie University, Canada
Department of Physics and Atmospheric Science, Dalhousie University, Canada
art ic l e i nf o
a b s t r a c t
Article history:
Received 13 December 2015
Received in revised form
14 March 2016
Accepted 13 April 2016
Available online 26 April 2016
A new static and dynamic model for organic thin-film transistors (OTFTs) is proposed. The model incorporates a gate-voltage dependent mobility, drain/source contact series resistance, threshold voltage
variation with bias and channel length, and drain induced barrier lowering effect. The model also takes
into account all the operating regions and includes static and dynamic characteristics of OTFTs. It is
developed using a physical basis where the model's parameters can easily be extracted from the experiment data. The model is suitable for computer aided design applications and has been verified by
device simulations and measurements from both p-type and n-type OTFTs.
& 2016 Elsevier Ltd. All rights reserved.
Keywords:
Organic thin-film transistors (OTFTs)
Static and dynamic model
Parameter extraction
Model validation
Circuit simulation
1. Introduction
Advances in organic semiconductor (OS) technologies have
been occurring at an accelerating pace. This technology is particularly attractive due to its low-cost, low temperature process,
implementation on flexible and light substrates, novel applications, and the potential to move to more environmentally friendly
materials and process. In addition, organic circuits can be manufactured in different shapes, e.g. printed onto curved substrates,
knitted into cloth, or even used as fibers directly in fabrics. They
can be used in large-area electronic applications such as smart
flexible displays, solar cells, flexible microelectronics and electronic skin for robots [1–3]. Organic semiconductors are inherently
sensitive to specific molecules, thus organic transistors are ideally
suited for biological and chemical sensors. The efficient design of
organic integrated circuits requires preliminary optimization and
modeling, and the availability of accurate SPICE-like analytical
models is particularly attractive.
OTFTs pass current by majority carriers, as opposed to the inversion mode of operation of typical MOSFETs. Many OTFTs
models have been proposed in the literature [4–12] to reflect
specific charge transport characteristics of particular OTFTs. An
efficient and accurate compact device model can provide the
bridge between existing OTFT technologies and more traditional
n
Corresponding author at: Department of Electrical & Computer Engineering,
Dalhousie University, Canada.
http://dx.doi.org/10.1016/j.mejo.2016.04.012
0026-2692/& 2016 Elsevier Ltd. All rights reserved.
circuit design. Electronic design automation (EDA) tools for organic integrated circuit design will be crucial for increasing the
development speed of OTFT technology, speeding its transition
from laboratory to application. However, it is difficult to find a
widely accepted SPICE-like model which includes static (DC) and
dynamic (AC) model based on second order effects of OTFTs [13–
16]. In this paper, we propose an advanced compact DC/AC model
for OTFTs based on second order effects. The present model has
three major improvements: (i) This DC/AC model is based on
second effects of OTFTs, such as channel length modulation, contact resistance. (ii) Drain induced barrier lowering (DIBL) effect is
considered in this model. (iii)The extended range of application
including p-type and n-type. The model covers all the operating
regions of OTFTs with a reasonable number of parameters. P type
OTFT with organic material Pentacene and n type OTFT with organic material PTCDI-C13 were manufactured and analyzed to investigate the validity of the model. The comparative results could
be accurately fit between the measured I–V characteristics and
simulation output with methodically extracted model parameters
from the linear region to saturation region.
2. Static model
In a traditional inorganic device, the active semiconductor layer
is generally comprised of lightly doped Si, or combination of group
III–V elements, such as GaAs. In these materials, the applied gate
2
L. Jiang et al. / Microelectronics Journal 53 (2016) 1–7
voltage causes an accumulation of minority charge carries at the
dielectric interface, such as electrons in a p-type material termed
an ‘inversion layer’. Carriers injected from the source and drain
electrodes may pass in this shallow channel where the current
flow is resulted. In an organic OTFT, the active layer is composed of
a thin film of highly conjugated small molecules or polymers, e.g.
p-channel pentacene and n-channel PTCDI-C13.Compared to inorganic materials, organics pass current by majority carriers and
an inversion regime does not exist. This fundamental difference is
related to the nature of charge transport in each of these semiconductors. In well-ordered inorganic material, the delocalization
of electrons leads to a band-type mode of transport, with charge
carriers moving through a continuum of energy levels. In less-ordered organic materials, the proposed mechanism is hoping between discrete, localized states of individual molecules.
OTFTs are three-terminal electrical devices that allow for the
control of the electrical current flowing between two electrodes
(source and drain) through the modulation of voltage (or current)
at a third electrode (the gate). In the basic OTFT design, there are
two types of device configuration: top contact and bottom contact.
The former involves building source and drain electrodes onto a
performed semiconductor layer, whereas the latter is constructed
by depositing the organic over the contacts layer. The structures
are illustrated in Fig. 1. The electrodes in the thin-film transistor
are composed of a metal. Typically, the electrodes are composed of
gold which have to do with the energy barrier, or the contact
potential of the metal–semiconductor interface.
A suitable OTFT model must be accurate enough in device simulations but also should present a high level of convergence in
integrated circuit simulations. At the same time, the model needs
to be flexible enough to take into account differences in OTFTs due
to materials and procedures used in fabrication. In order to avoid
the divergence, the model should be developed using explicit
equations. It has to be analytical, simple and easily derivable. The
model performance must be evaluated by comparing the simulation results to device measurements.
In the following discussion, the transistors are assumed to be
n-type. For the case of p-type, care must be taken to change the
polarities of the voltage applied.
Charge drift is the accepted model in the presence of tail-distributed traps (TDTs). From TFT charge drift model, the current is
given by [17]:
ID = Wμ x Q x Ex
(1)
where W is the width of the OTFT conduction channel. At given
position x in the channel ( 0 ≤ x ≤ L ), μx is mobility and Q x is the
charge density. Ex is the electric field strength.
Parameter Q x is given by (for VGS > VT ):
Q x = Cdiel (VGS − VT − Vx )
(2)
Parameter Cdiel is the gate dielectric capacitance per unit area,
VGS is the voltage between the drain and source, VT is the threshold
voltage and Vx is the voltage at position x .
In order to obtain a better fit to the measured data, a gate
voltage dependent mobility is developed [19]. In OTFTs operating
above threshold, most of the charge induced by the gate-source
voltage occupies localized traps and only a fraction of carriers play
a role in current conduction. This effect can be accounted for by
the empirical gate-voltage dependent field-effect mobility.
⎛ V − VT − Vx ⎞γ
μ x = μ 0 ⎜ GS
⎟
⎠
⎝
Vaa
(3)
where μ0 is the low-field mobility, γ is the mobility enhancement
factor, and Vaa is a fitting parameter [18]. These parameters can be
extracted from the IDS (VGS ) characteristics.
Parameter Ex can be written as:
Ex = ∂Vx/∂x
(4)
Integrating Eq. (1) along the channel gives:
∫0
L
ID dx =
∫0
VDS
⎛ V − VT − Vx ⎞γ
Wμ 0 Cdiel ⎜ GS
⎟ (VGS − VT − Vx ) dVx
⎠
⎝
Vaa
Therefore:
ID =
μ 0 Cdiel W (VGS − VT )(γ + 2) − (VGS − VT − VDS )(γ + 2)
Vaa γ L
γ+2
(5)
2.1. Channel length modulation
Eq. (5) can be modified to allow for channel length modulation:
ID =
μ 0 Cdiel W (VGS − VT )(γ + 2) − (VGS − VT − VDS )(γ + 2)
Vaa γ L − ΔL
γ+2
(6)
Introducing the channel length modulation coefficient λ ,
ΔL
= λVDS
L
⎞ λV < < 1
⎛
⎛
L
ΔL ⎞
⎟⎟ = L ⎜⎜ 1 − λVDS ⎟⎟ DS ≈
L − ΔL = L ⎜⎜ 1 −
L ⎠
( 1 + λVDS )
⎠
⎝
⎝
(7)
Therefore, Eq. (6) can be written as:
ID =
μ 0 Cdiel W
*(1 + λVDS )*
Vaa γ L
(VGS − VT )(γ + 2) − (VGS − VT − VDS )(γ + 2)
γ+2
Fig. 1. Simplified diagram of organic thin-film transistor (OTFT).
(8)
L. Jiang et al. / Microelectronics Journal 53 (2016) 1–7
3
Therefore, Eq. (11) can be written:
2.2. Variation of threshold voltage with bias and channel length
ID =
When the variation of the drain to source voltage VDS is small,
threshold voltage is relatively constant. When larger VDS is applied
to the device, the channel depletion width is no longer constant
along the length of the device, but varies from the drain to the
source [18]. If the length of OTFT is reduced and VDS is increased,
the drain accumulation region moves closer to the source accumulation region, resulting in significant field penetration from the
drain to the source. Due to this field penetration, the potential
barrier at the source is lowered, resulting in increased carrier injection at the source through the reduced channel barrier, thus
giving rise to increased drain current. The effective threshold
voltage can be expressed by [17]:
VT , eff = VT 0 − VDS *σ
(9)
where VT 0 is threshold voltage at low voltage VDS and parameter σ
is called drain induced barrier lowering effect (DIBL) parameter.
σ = ε0 εorg /πCox L
(10)
where parameter ε0 is the permittivity of free space and εorg is the
relative permittivity of the organic semiconductor. Therefore, including threshold voltage variation, Eq. (8) can be written:
ID =
μ 0 Cdiel W
*(1 + λVDS )*
Vaa γ L
(VGS − VT 0 + VDS *σ )(γ + 2) − (VGS − VT 0 − VDS + VDS *σ )(γ + 2)
γ+2
(VGS − VT 0 + VDSI *σ )(γ + 2) − (VGS − VT 0 − VDSI + VDSI *σ )(γ + 2)
γ+2
We define the effective voltage drive ( Vevd ) as:
⎡
⎛ V − VT − VDS ⎞ ⎤
Vevd = VGS − VT − VDS = VSS ln ⎢ 1 + exp ⎜ GS
⎟⎥
⎠⎦
⎝
VSS
⎣
when (VGS − VT − VDS ) < < VSS for subthreshold region
⎛ V − VT − VDS ⎞
Vevd ≈ VSS exp ⎜ GS
⎟
⎠
⎝
VSS
when (VGS − VT − VDS ) > VSS for above−threshold region
Vevd ≈ (VGS − VT − VDS )
(16)
where voltage VSS is subthreshold slope voltage [20]. The value for
parameter VSS is related to the steepness of the subthreshold
characteristics of the OTFTs.
If (VGS − VT 0 − VDSI + VDSI *σ ) < VSS , the OTFT is operating in the
subthreshold region, and Eq. (15) can be written:
μ 0 Cdiel W
*(1 + λVDSI )*
Vaa γ L
(VGS − VT 0 + VDSI *σ )(γ + 2) −
(V
SS *exp
(
VGS − VTO − VDSI + VDSI * σ
VSS
γ+2
2.3. Source/drain series resistance
μ 0 Cdiel W (VGS
(17)
ID =
μ 0 Cdiel W
*(1 + λVDSI )
Vaa γ L
(VGS − VT 0 + VDSI *σ )(γ + 2) − (VGS − VT 0 − VDSI + VDSI *σ )(γ + 2)
γ+2
(18)
When [VGS − VT 0 + VDSI *σ ] ≤ VDSI , the OTFT is in the saturation region. The current ID can be written as:
ID =
μ 0 Cdiel W (VGS − VT 0 + VDSI *σ )(γ + 2)
(1 + λVDSI )
Vaa γ L
γ+2
(19)
(12)
Assuming the drain and source resistances to be equal, and
where symbol Rs is the source/drain series resistance and Rch is
channel resistance. The total series resistance is very sensitive to
the source/drain specific contact resistance and the contact resistance dominates the total series resistance in some cases [19].
When the OTFT is operating in linear region:
R ch ≈
(γ + 2)
))
If [VGS − VT 0 − VDSI + VDSI *σ ] > VSS and [VGS − VT 0 + VDSI *σ ] > VDSI ,
the OTFT is in the linear region, and the current is given by:
The series resistance depends on the specific contact resistance
and the contact area. For larger contact resistance values, the
voltage drops due to the source/drain series resistances cannot be
neglected. From the fabrication perspective, a certain amount of
overlap between the source/drain and gate electrodes is needed in
order to reduce the series resistances between the channel and
source/drain electrodes. However, a larger overlap leads to a larger
parasitic capacitance between source/drain and gate, which is
undesirable for many applications. Therefore, this trade-off must
be considered when designing a process. The total device resistance Rtot is expressed by:
Rtot = 2Rs + R ch
(15)
2.4. Considering the sub-and above-threshold regions
ID =
(11)
μ 0 Cdiel W
*(1 + λVDSI )*
Vaa γ L
L
− VT 0 + VDS *σ )
(13)
Internal potentials of source and drain are expressed by VSI and
VDI . Therefore, internal potentials of source and drain are shown
by:
The charge per unit area which in general depends on the
position x along the length of the channel can be expressed by:
Q gx = Cdiel (VGS − VT − Vx )
(20)
In Eq. (20), parameter Vx is the voltage at any point x along the
length of the channel from the source to drain. If integrating these
charges over the area of the active gate region, the corresponding
total charge Q g can be obtained by:
Qg = W
∫0
L
Cdiel (VGS − VT − Vx ) dx
(21)
We change the variable of integration from ‘ dx ’ to ‘ dVx ’ by
making use of the following Eq. [20]:
VSI = VS + Rs *ID
VDI = VD − Rs *ID
VDI − VSI = VDSI = VD − VS − 2Rs *ID = VDS − 2Rs *ID
3. Dynamic model
(14)
where VS and VD are the source electrode voltage and drain electrode voltage, respectively.
dx =
μ0 W
μ W
Q gx dVx = 0 Cdiel (VGS − VT − Vx ) dVx
ID
ID
Substitute (22) into (21), one gets:
(22)
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L. Jiang et al. / Microelectronics Journal 53 (2016) 1–7
CGD =
∂Q g
∂VGD
=
VGS
(γ + 2)Vaa γ
(V − VTO )2
WLCdiel * GD
(1 + λVDS )
(VGS − VTO )2 + γ
4. Parameter extraction
4.1. Mobility enhancement factor
The mobility enhancement factor γ in Eq. (18) of the OTFT's
model must be extracted from experimental data. In order to extract this parameter, the function H (VGS ) is introduced. The H (VGS )
function is the integral of the drain current over the gate bias divided by the drain current at VGS. The corresponding equation of
the H (VGS ) function is derived as Eq. (29).
Fig. 2. H (VGS ) and IDS1/ (γ + 2) plotted versus gate bias for p-type.
Qg =
μ 0 W 2Cdiel2
ID
∫0
VDS
V
H (VGS ) =
(VGS − VT − Vx )2dVx
(23)
∫0 GS IDS (VGS ) dVGS
IDS (VGS )
1 (VGS − VT 0 + VDSI *σ )γ + 3 − (VGS − VT 0 − VDSI + VDSI *σ )γ + 3
=
γ + 3 (VGS − VT 0 + VDSI *σ )γ + 2 − (VGS − VT 0 − VDSI + VDSI *σ )γ + 2
(29)
For saturation region:
3.1. The linear region
H (VGS ) =
When the TFTs are operating in the linear region, using Eq. (18)
for the current ID , neglecting the threshold voltage variation with
bias and carrying out the integration of Eq. (23):
Qg =
⎡ (V − V )3 − (V − V )3 ⎤
(γ + 2)Vaa γ
GD
TO
GS
TO
⎥
WLCdiel ⎢
3 (1 + λVDS )
⎣ (VGD − VTO )2 + γ − (VGS − VTO )2 + γ ⎦
(24)
Therefore, the gate to source capacitance, neglecting overlap,
is:
CGS =
∂Q g
∂VGS
=
VGD
⎡
3 (VGS − VTO )2
Vaa γ
WLCdiel ⎢
3
⎣ (VGS − VTO )2 + γ − (VGD − VTO )2 + γ
((V − VTO )3 − (VGS − VTO )3)(VGS − VTO )2 + γ (2 + γ ) ⎤ γ + 2
⎥*
+ GD
((VGD − VTO )2 + γ − (VGS − VTO )2 + γ )2 (VGS − VTO ) ⎦ 1 + λVDS
(25)
The gate to drain capacitance can be expressed by:
CGD
+
∂Q g
=
∂VGD
VGS
VGS − VTO + VDSI *σ
γ+3
The value of mobility enhancement factor γ is obtained from
the slope of the H (VGS ) versus VGS . The H (VGS ) versus VGS plots for
p-type OTFT using pentacene as the semiconductor in Fig. 2 and
for n-type OTFT with N, N′-ditridecy1-3,4,9,10-perylenedicarboximide(PTCDI-C13) as the semiconductor, are shown in Fig. 3. The
size of p-type OTFT is W¼ 500 mm, L¼ 100 mm, Cox ¼ 3.45 F/cm2 and
was made on the silicon wafer with a thermal SiO2 gate dielectric,
treated with a phosphoric acid SAM [21]. The procedure can be
seen in Section 5.1 in this article. The size of n-type OTFT is
W¼1500 mm, L¼ 50 mm, Cox ¼1.14 F/cm2 and was also made on the
silicon wafer. A thermal SiO2 plus over layer Cytop was as gate
dielectric for the n-type OTFT [22]. After calculation, the mobility
enhancement factor γ for p-type is 0.504, and for n-type is 0.185.
4.2. Characteristic voltage for field effect mobility Vaa
⎡
3 (VGD − VTO )2
V γ
= aa WLCdiel ⎢
3
⎣ (VGD − VTO )2 + γ − (VGS − VTO )2 + γ
γ+2
((VGS − VTO )3 − (VGD − VTO )3)(VGD − VTO )2 + γ (2 + γ ) ⎤
⎥*
((VGD − VTO )2 + γ − (VGS − VTO )2 + γ )2 (VGD − VTO ) ⎦ (1 + λVDS ) (26)
Calculating the slope SVaaγ of the expression IDS1/ (γ + 2) versus
VGS − VT 0 + VDSI *σ , the value of Vaa γ from Eq. (19) is:
3.2. The saturation region
When the OTFTs are operating in saturation region, using the
Eq. (19) for the current ID , neglecting the threshold voltage variation with bias and carrying out the integration of Eq. (23):
Qg =
⎡ (V − V )3 − (V − V )3 ⎤
(γ + 2)Vaa γ
TO
GS
TO
⎥
WLCdiel ⎢ GD
3 (1 + λVDS )
(VGS − VTO )2 + γ
⎣
⎦
(27)
Therefore:
CGS =
∂Q g
∂VGS
=
VGD
(γ + 2)Vaa γ
WLCdiel *
3 (1 + λVDS )
((VGS − VTO )3 − (VGD − VTO )3)(2 + γ ) − 3 (VGS − VTO )3
(VGS − VTO )3 + γ
(30)
(28)
Fig. 3. H (VGS ) and IDS1/ (γ + 2) plotted versus gate bias for n-type.
L. Jiang et al. / Microelectronics Journal 53 (2016) 1–7
Vaa γ =
μ 0 Cdiel W (1 + λVDSI )
(γ + 2) L (SVaaγ )γ+ 2
(31)
The relation between IDS1/ (γ + 2) and VGS can be seen for p-type
OTFTs in Fig. 2. The relation between IDS1/ (γ + 2) and VGS can be seen
for n-type in Fig. 3. From Eq. (31),fitting the data results in
Vaa γ ¼3.60, Vaa ¼13 V for p-type, and Vaa γ ¼ 0.584, Vaa ¼0.055 V for
n-type.
4.3. Series resistance and channel modulation factor
Rewriting Eq. (12), the total resistance between the source and
the drain is:
Rtotal = 2Rs +
L
μ 0 Cdiel W (VGS − VT 0 + VDSI *σ )
(32)
Eq. (32) can be written as:
Rtotal = S (L − ΔL ) + 2Rs
Parameter S (= μ
(33)
1
0 Cdiel W (VGS − VT 0 + VDSI * σ )
) is the channel resistance
per unit length. Parameter ΔL is the difference between the design
and effective channel length, including channel modulation.
Rtotal = SL − SΔL + 2Rs = SL + M
(34)
Therefore,
M = 2Rs − SΔL
(35)
The value of the resistance can be calculated by Rtotal = VDS /ID
from ID -VDS curves for different VGS and different channel lengths L.
When the OTFTs are operating in the accumulation region at high
VGS voltage, the total resistance Rtotal is plotted against L . The value
S can be obtained from the slope of the curve ( Rtotal versus L ) while
the intercept yields M in Eq. (34). Repeating the previous steps for
different VGS, i generates sets of Si (VGS, i ) and Mi (VGS, i ). The intercepts
Mi are plotted against the corresponding slopes Si . Therefore, the
slope and intercept of Mi versus Si gives ΔL and series resistance
2Rs in Eq. (35). After calculation, series resistance Rs is 50 kΩ for
p-type and 10 kΩ for n-type.
5
The channel modulation factor is obtained using λ = ∂ID/∂VDS, SAT ,
in which VDS, SAT is equal to the value of the drain/source saturation
voltage. The parameter λ is the slope of the curve ID against VDS, SAT
in saturation mode. After calculation, the parameter λ is 4.5E-3 for
p-type and is 0.5E-5 for n-type.
4.4. Subthreshold slope voltage
The subthreshold current is the drain current for VGS below the
threshold voltage and varies exponentially with VGS . The reciprocal
of the slope of log10 (IDS ) versus VGS is defined as the sub-threshold
slope S . The sub-threshold slope is an important parameter that
determines how well the OTFTs operate as a switch, by determining the voltage swing required to switch the transistor between the off and on states. When the voltage VGS is equal to VT ,
the drain current IDS0 is determined. When the drain current IDS′ is
two decades lower than the current IDS0 (i.e. IDS′
= IDS0/100), the
corresponding gate voltage VGS′ is the boundary of subthreshold
operation. The reciprocal of the slope of log (IDS ) versus VGS shown
in Fig. 4 can be obtained from the subthreshold region, given by
[17] and [14]:
S = dVGS /d (log IDS ) ≈ VSS
(V /decade)
(36)
After calculating above OTFTs with pentacene semiconductor,
the parameter value VSS is 3.03 V for p type and 1.28 V for n-type
OTFTs.
4.5. Drain induced barrier lowering effect (DIBL) parameter
Eq. (9) can be written as:
VT , eff = VT 0 − VDS *σ = VT 0 + ΔVT
(37)
The parameter ΔVT is the variation of the threshold voltage
with increased voltage VDS . If ΔVT is measured, σ also can be
characterized. This can be done by sweeping the gate-source voltage VGS from VT 0 − 1V to VT 0 + 1V for different drain-source voltages VDS . The threshold voltage, VT (VDSn ), is the gate voltage,
VGS (VDSn ), at which the drain current is equal to IDS0 determined in
Section 4.4 above. Once VT (VDSn ) is determined for each voltage
Fig. 4. Log (ID) versus VGS for p-type and n-type.
6
L. Jiang et al. / Microelectronics Journal 53 (2016) 1–7
Table 1
Extracted parameters for p-type and n type OFTFs.
Model parameter of OTFT
p-type
n-type
VT0 – threshold voltage(V)
μ0 – mobility (cm2/V s)
0.88
1.20
3.45E-8
500
100
0.504
13
0.2E-4
50k
3.03
4.5E-3
1.18
0.032
1.14E-8
1500
50
0.185
0.055
0.18E-4
10k
1.28
0.5E-5
Cdiel – specific capacitance (F/cm2)
W – channel width(um)
L – length (mm)
γ – mobility enhancement factor
Vaa – characteristic voltage (V)
σ – drain induced barrier lowering
Rs – contact resistance (Ω)
VSS subthreshold slope voltage (V)
λ – channel length modulation(V 1)
Fig. 6. The characteristic of VGS IDS for p-type OTFTs.
Fig. 5. The characteristic of VDS IDS for p type OTFTs.
VDSn , then the variation of the threshold voltage
pressed by:
VT 0 − VTn = − ΔVT = VT 0 − VT (VDSn ) = σ *VDS (n)
ΔVT can be ex(38)
The slope of the built curve VT 0 − VT (VDSn ) versus VDS (n) is the
value for DIBL parameter σ .
4.6. Summary of model parameters
All model parameters are extracted from the experimental data
and are summarized in the Table 1.
5. Experiment and results
Fig. 7. The characteristic of VDS IDS for N type OTFTs.
assembled monolayer-modified oxide and polymeric gate dielectrics were successfully manufactured in our lab. The fabrication procedure in detail for p-type and n-type OTFTs are separately
shown in the Refs. [21] and [22].
5.1. Experiment
5.2. Results and discussions
We made two kinds of OTFTs including p-type and n-type to
verify the model in this article. P-type is self-assembled monolayers of phosphonate(SAMPs) fabricated on SiO2 gate dielectrics
which can benefit pentacene-based devices to get better performance, especially for these four parameters: on/off ratios, carrier
mobilities, sub-threshold performance, and threshold voltages. For
p-type, the source and drain electrodes were made by gold.
N-channel organic thin-film transistors based on N, N′
-ditridecyl-3,4,9,10-perylenedicarboximide(PTCDI-C13) using self-
The p-type and n-type FETs are based on organic semiconductors pentacene and PTCDI-C13, respectively. The measured
DC output curves for the p-type OTFTs and the simulated results
using the model presented here are shown in Fig. 5.It can be seen
from Fig. 5 that there is a good agreement in the drain current
between the simulations and measurements from the linear region to saturation region. Note that the developed model can take
symmetry into consideration, allowing the drain-source voltage
VDS can change from negative to positive. Fig. 6 is the characteristic
L. Jiang et al. / Microelectronics Journal 53 (2016) 1–7
7
References
Fig. 8. The characteristic of VGS IDS for N type OTFTs.
of VGS IDS for p-type OFET.
In Fig. 7, the measured DC curves are for the n-type OTFTs reported in [22].The simulated result using the model parameters
listed in Table 1 is also shown in Fig. 7. Consistent behavior between the simulations and measurements in the characteristics
can be seen in both the linear region and saturation regions under
normal biasing. There is some deviation between the simulations
and experiments in the linear regions. We believe this to be due to
a nonlinear, diode-like, contact resistance that has not been included in this model. This nonlinear contact resistance produces
the “hook” in the output curve near VDS ¼0 V, which is not reproduced in this model. Nonlinear contact resistance is very undesirable, can be avoided by judicious choice of source/drain
contact materials, and was therefore not included in this model.
Fig. 8 is the characteristic of VGS IDS for n-type OFETs.
6. Conclusion
A dynamic and static model for organic thin-film transistors
(OTFT) is proposed in the article. The model considers a gatevoltage dependent mobility, drain/source contact series resistances and the variation of the threshold voltage VT both with
drain bias and channel length. At the same time, the model simulates all the operating regions in DC and transient modes.
Simple methods for extracting the model parameters are presented in the article. The model equations have been verified by
experiments and the comparison of results between the simulation and experiments from p-type and n-type OTFTs show good
agreement. Therefore, the model is suitable for computer-aided
organic integrated circuit design applications.
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