Islamic University – Gaza
Engineering Faculty
Department of Computer Engineering
ECOM 3010: Computer Architecture Discussion
Chapter 6
Exercises with solutions
Eng. Eman R. Habib
December, 2013
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Computer Architecture Discussion
Exercise 1: (6.3 from book)
Exercise 2: (6.4 from book)
There is a data dependency through $3 between the first instruction and each subsequent
instruction.
There is a data dependency through $6 between the lw instruction and the last instruction.
The data dependencies between the first instruction and each subsequent instruction can be
resolved by using forwarding.
The data dependency between the load and the last add instruction cannot be resolved by
using forwarding, cause a stall.
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Computer Architecture Discussion
Exercise 3: (6.17 from book)
At the end of the fifth cycle:
instruction 1 finish WB stage,
instruction 2 finish MEM stage,
instruction 3 finish EX stage,
instruction 4 finish ID stage and
instruction 5 finish IF stage.
Registers are being read after ID stage  instruction 4, registers $6 and $1 are being read.
Registers are being written after WB stage  instruction 1, register $2 is being written.
Exercise 4: (6.18 from book)
The forwarding unit is seeing if it needs to forward. It is looking at the instructions in the fourth
and fifth stages and checking to see whether they intend to write to the register file and
whether the register written is being used as an ALU input.
Thus, it is comparing:
EX/MEM.RegisterRd = ID/EX.RegisterRs? $ 4 = $3?
EX/MEM.RegisterRd = ID/EX.RegisterRt?,  $4 = $7?
MEM/WB.RegisterRd = ID/EX.RegisterRs?,  $2 = $3?
MEM/WB.RegisterRd = ID/EX.RegisterRt?  $2 = $7?
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Computer Architecture Discussion
Exercise 5: (6.19 from book)
The hazard detection unit is checking to see whether the instruction in the ALU stage is an lw
instruction and whether the instruction in the ID stage is reading the register that the lw will be
writing. If it is, it needs to stall. If there is an lw instruction, it checks to see whether:
ID/EX.RegisterRt = IF/ID.RegisterRs?  $7 = $6?
ID/EX.RegisterRt = IF/ID.RegisterRt?  $7 = $1?
Exercise 6: (6.21 from book)
a. There will be a bubble of 1 cycle between a lw and the dependent add since the load
value is available after the MEM stage. There is no bubble between an add and the
dependent lw since the add result is available after the EX stage and it can be forwarded
to the EX stage for the dependent lw. After 2 instructions (add, lw) there is a bubble of 1
cycle, so every 2 instructions need 3 cycles. Therefore, CPI = cycle/instruction ≈ 3/2 =
1.5.
b. Without forwarding, the value being written into a register can only be read in the same
cycle. As a result, there will be a bubble of 2 cycles between an lw and the dependent
add since the load value is written to the register after the MEM stage. Similarly, there
will be a bubble of 2 cycles between an add and the dependent lw, so every instruction
needs 3 cycles. Therefore, CPI ≈ 3.
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Computer Architecture Discussion
Exercise 7: (6.22 from book)
It will take 8 cycles to execute this code, including a bubble of 1 cycle due to the dependency
between the lw and sub instructions.
5 cycles for the lw (five stages) + 1 cycle bubble + 1 cycle for sub + 1 cycle for add = 8 cycles.
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Computer Architecture Discussion
Exercise 8: (6.23 from book)
Exercise 9:
Add a Forward Unit For load immediately followed by store
if (EX/MEM.MemWrite
and (MEM/WB. RegWrite)
and (MEM/WB.RegisterRt != 0)
and (MEM/WB.RegisterRt = EX/MEM.RegisterRt))
ForwardC = 1
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Computer Architecture Discussion
Exercise 10:
Add a Forward Unit For add immediately followed by store
if (EX/MEM.MemWrite
and (MEM/WB. RegWrite)
and (MEM/WB.RegisterRd != 0)
and (MEM/WB.RegisterRd = EX/MEM.RegisterRt))
ForwardC = 1
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Computer Architecture Discussion
The Last Discussion
I hope you have benefited from me in this
course and I wish you Good luck in your final
exams and Good luck in all your life
♥I wish you all the Best my lovely students ♥
 Best Wishes 