MIPS
pipelining with hazards
pipelining without hazards
multi mips
Multi cycle -
Fetch
Decode
LW
5
SW
4
R-type
4
B-type
3
PCWrite = 0
PCSrc = 1
ADDI
4
RegWr =1
Single Cycle -
Multi - shared bus
Fetch
MDR
LD
ADD
ST
JMPZ
ADD
Single-Cycle SimpleCPU
Simple CPU - Multi Cycle
CMP
Cache
Control Hazards
Branchstall=
BranchD
AND RegWriteE AND (WriteRegE == rsD OR WriteRegE== rtD)
OR
BranchD AND MemtoRegM AND (WriteRegM == rsD OR WriteRegM == rtD)
StallF = StallD = FlushE = lwstall OR branchstall
Pipelined-based design
Combinational logic (F)
Latch (L)
Max. propagation delay in F: TM
Min. propagation delay in F: Tm
Proper latching delay: TL
Consider the 2-scenarios
Case-1:
Inputs x1 applied at the stage at time T1
Outputs of F must be valid at T1 + TM
Latching at L of the outputs must be valid until: T1 + TM +TL
Case-2:
Inputs x2 applied at the stage at time T2
Effect of the outputs can be found at least at T2 + Tm
Condition of 2-nd set of signals does not overrun the 1-st set:
T2 + Tm > T1 + TM + TL
Clock period (T): T2 – T1 > TM – Tm + TL
Max. clocking rate cannot exceed 1/T
Clock period has two parts TM-Tm & TL
TM-Tm ≈ 0
TL: ~feedback loop and stabilizing of the signal
~worst-case clock skew
Cost of non-pipelined design: G
Gate count
Cost of adding a latch: L
Cost of k-stages pipelined design (C): G + k * L
Cost of pipeline design increases linearly w.r.t depth of
pipeline
The latency in the non-pipeline design: T
Performance or throughput: 1/T
Throughput of pipelined design (P): 1/(T/k + S)
The additional delay S because of latches
P is a non-linear function of k