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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 12, DECEMBER 2002
A 10–300-MHz IF-Digitizing IC With 90–105-dB
Dynamic Range and 15–333-kHz Bandwidth
Richard Schreier, Member, IEEE, Jennifer Lloyd, Larry Singer, Member, IEEE, Donald Paterson, Member, IEEE,
Mike Timko, Member, IEEE, Michael Hensley, Greg Patterson, Associate Member, IEEE, Kevin Behel, and
James Zhou
16 analog-to-digital converter (ADC), decimation filter, and
two synthesizers implement a general-purpose back-end for a
narrow-band superheterodyne receiver. The 16 ADC is merged
Abstract—An integrated low-noise amplifier, mixer, bandpass
with the mixer and combines LC, active-RC, and switched-capacitor resonators to achieve low noise and robust operation with
low power consumption. A variable full-scale feature adds an
automatic-gain-control capability to the ADC while saving power
and minimizing noise at low signal levels.
Index Terms—Analog-to-digital converter, bandpass, continuous-time, delta–sigma, digital receiver, sigma–delta, superheterodyne receiver.
I. INTRODUCTION
I
T HAS been noted [1] that “The wonderful thing about standards is that there are so many to choose from.” This sentiment is especially pertinent in radio communications, wherein
a multitude of standards specify a variety of frequency assignments, data rates, modulation formats, and access schemes. Despite this diversity, all high-performance communication systems share the need for receivers with high dynamic range.
When the highest possible dynamic range is required, a
superheterodyne receiver is usually employed. A superheterodyne receiver, an example of which is depicted in Fig. 1, uses a
number of filter/amplify/mix operations to extract the desired
signal from the many signals picked up by the antenna. As the
receiver refines the signal bandwidth, more gain can be applied
because more of the many interfering signals have been filtered
out. This technique allows a superheterodyne receiver to cope
with many interfering signals spread over a broad spectrum.
The disadvantages of a superheterodyne receiver, relative
to an architecture such as direct-conversion, are the increased
complexity and higher power consumption associated with
an increased block count and the need to digitize a high
intermediate frequency (IF). As demonstrated in [2], a direct-conversion receiver employing a pair of continuous-time
low-pass analog-to-digital converters (ADCs) can be implemented with very little power, but the direct-conversion
architecture is vulnerable to low-frequency distortion products
which limit its dynamic range.
Manuscript received March 31, 2002; revised August 1, 2002.
R. Schreier, J. Lloyd, L. Singer, D. Paterson, and M. Timko are with Analog
Devices, Inc., Wilmington, MA 01887-3463 USA.
M. Hensley, G. Patterson, and K. Behel are with Analog Devices, Inc.,
Greensboro, NC 27409 USA.
J. Zhou is with Analog Devices, Inc., Beijing, China.
Digital Object Identifier 10.1109/JSSC.2002.804331
Fig. 1. A dual-conversion superheterodyne receiver.
In this work, a combination of a mixer and a continuous-time
ADC achieves 90 dB of dynamic range over a
bandpass
333-kHz band from 10 to 300 MHz. The 50-mW power consumption of the circuit shows that a high-performance dual-conversion superheterodyne receiver can be implemented with low
power. The integration of a low-noise amplifier (LNA), mixer,
and ADC, together with the synthesizers needed by the receiver
back-end address the issues of size, cost, and complexity—issues which are of great importance in portable systems.
In the next section, the specifications and overall architecture
of the IC are described. The main body of the paper deals with
individual blocks. The ADC is given the greatest emphasis, but
noteworthy features of other blocks are also mentioned. Measurements show that the IC is indeed able to implement a lowpower, high-performance receiver back-end.
II. SYSTEM OVERVIEW
This work is concerned with integrating the back-end of the
superheterodyne receiver shown in Fig. 1. To allow use of the
IC in a broad range of narrow-band applications, including
analog-FM, GSM/EDGE, as well as a variety of specialized
protocols, no IF-specific optimizations and no application-specific signal processing are implemented on the IC. Thus, the
primary purpose of the IC is simply to convert an IF input into
digital form, where the IF and signal bandwidth are allowed
to vary from application to application. Secondary functions
include a synthesizer for the second LO (LO ), a synthesizer
for the ADC sampling clock (CK) plus automatic-gain-control
(AGC) logic.
The input IF (IF ) range is 10–300 MHz, while the second IF
(IF ) range is 1–4 MHz. The lower limit on IF is determined
by the size of the coupling and bypass capacitors used in the
LNA, mixer, and elsewhere, while the upper limit on IF is determined by the high-frequency roll-off of these two blocks. The
0018-9200/02$17.00 © 2002 IEEE
SCHREIER et al.: IF-DIGITIZING IC WITH 90–105-dB DYNAMIC RANGE AND 15–333-kHz BANDWIDTH
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(a)
(b)
Fig. 2.
(a) Conventional and (b) improved back-end architectures.
IF range is linked to the range of
, since the ADC and dec8 center frequency. The
imation filter are designed for an
range was chosen to span the GSM-inspired
8–32-MHz
13–26-MHz range, with margin.
In addition to the above frequency-range specifications are
specifications related to signal levels, noise, and distortion.
Under large-signal conditions, the IF power can approach
20 dBm, so the IC is required to process this level without
clipping. When signals are small, the noise figure of the IC
needs to be as small as possible, and a target of 8 dB was
set. Lastly, the distortion specification is captured in the input
third-order intercept point (IIP3) specification of 5 dBm.
Returning now to the primary function of the IC, Fig. 2 contrasts two approaches for converting an IF into bits. The more
conventional topology shown in Fig. 2(a) requires several highpower blocks, namely a variable-gain amplifier (VGA), antialias filter (AAF), and ADC. This topology uses a switched-caADC in order to take advantage of
pacitor (SC) bandpass
the fact that the signal is narrow-band, but the noise/power tradeoffs in a SC ADC require the use of a VGA with a large gain
range to compensate for the ADC’s high noise figure. In [3], for
example, a gain range of 22 dB was needed, and, despite the fact
that the AAF was implemented as part of the VGA, the power
required by the VGA/AAF equaled that of the ADC.
In the improved architecture shown in Fig. 2(b), both the
ADC
VGA and AAF are eliminated by using a bandpass
containing an LC tank [4]. The AAF is not needed because the
ADC has inherent alias proteccontinuous-time bandpass
tion [5], and the VGA is not needed because the dynamic range
of the ADC is very high. How the ADC’s dynamic range can be
high even though its power consumption is low will be explored
next.
III. BANDPASS ADC
Fig. 3 shows the structure of the ADC in some detail. The
IF input is amplified by the LNA, converted to a current by
the mixer’s -to- converter, and chopped using the Gilbert
switching core. The output current from the mixer is the input to
the ADC. This input, minus the feedback from the current-mode
DAC (IDAC) is applied to the LC tank, which forms the first
Fig. 3.
ADC in detail.
resonator in a bandpass
ADC. The output of this first resonator is a voltage which couples to a second resonator implemented with active-RC circuitry. The second resonator couples to a final SC resonator whose output is quantized by a
nine-level flash and then fed back to each resonator through a
number of DAC circuits. Thus, the ADC is a sixth-order multibit
modulator constructed with a variant of the casbandpass
cade-of-resonators feedback topology containing both continuous-time and discrete-time resonators. The reasons underlying
the choice of the various resonator architectures will be presented after delving into the architecture’s dynamic range advantages.
A. ADC Front-End
The first key to the architecture’s high dynamic range is the
fact that the output of the mixer is taken in current form. In a
more conventional approach, the mixer output current is converted to a voltage via resistive loads, and this voltage is then
converted to digital form by the ADC. For example, if the ADC
ADC with an LC tank as in [6],
were a continuous-time
the ADC input voltage would have to be converted to current
form using a low-noise, highly linear (and hence high-power)
transconductance element. Taking the mixer output directly
eliminates unnecessary -to- and -to- conversion, and
thus eliminates the noise, distortion, and power associated with
these operations.
The second and most important feature of this architecture
is that the first resonator of the ADC is an LC tank. Since inductors and capacitors are (ideally) lossless, they do not add
noise. Inductors and capacitors are also very linear, and thus
the distortion of these components is negligible. Lastly, since
an LC tank does not use active components, the first resonator
needs no power. It is rare for an architecture to gain advantages
in terms noise, distortion, and power simultaneously, but this is
indeed what happens when the first resonator takes advantage
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of a physical (as opposed to synthesized) resonance. The particular arrangement of the inductors shown in Fig. 3 is also helpful
because it eliminates the dc drop caused by passing the mixer’s
bias current through resistive loads and thus gives the mixer (and
the IDAC) the greatest possible headroom.
Despite these important advantages, there are drawbacks associated with using an LC tank. The first disadvantage is that the
inductances needed are in the range of a few microhenry ( H)
and so the inductors must be external. Fortunately, suitable inductors are small (possessing a volume of about 12 mm ) and
inexpensive (less than 5¢ each). The second disadvantage of an
LC tank is that, due to the 10% tolerance of the inductors, the
resonant frequency needs to be tuned. The IC achieves tuning
to within 1% of the desired frequency by means of a 9-b array
of trimming capacitors. Approximately 200 pF is available for
tuning. During the tuning process, the LC tank is used as the resoscillator and the frequency of
onant element of a negative8. The tuning code of the
oscillation is compared against
capacitor array is then adjusted in a successive-approximation
fashion until all bits in the tuning code are determined. The drift
of the resonant frequency with temperature is dominated by the
temperature coefficient of the inductors. Low-cost inductors can
achieve a drift of less than 3% over a 100 C span, so tuning at
power-up is typically sufficient.
B. ADC Back-End
The second resonator in the ADC could also use an LC tank,
but the benefits of an LC tank are less compelling in this context. As typically occurs in a bandpass modulator, noise added
after the first resonator is noise-shaped and thus the noise/distortion/power advantages of an LC tank can be weighed against
the need for external components and associated pins. Since the
active-RC resonator shown in Fig. 3 is able to meet the noise
requirements of the second stage with only 2 mA of current, the
power penalty of a fully integrated resonator is not excessive.
As with the LC resonator, the RC resonator requires tuning.
Tuning is accomplished via programmable capacitor arrays
which make up the integrating capacitors shown in Fig. 3 and
proceeds by turning the RC resonator into an oscillator via a
small amount of positive feedback (not shown) and adjusting
the tuning code to align the frequency of oscillation with the
desired center frequency. The tuning range of the RC resonator
is what limits the 8–32-MHz clock frequency range of the
modulator.
The third resonator in the ADC could also be implemented
and drift of
with an active-RC resonator, but the uncertain
an RC resonator, coupled with a conservative design strategy,
would necessitate the use of a fourth resonator stage. To avoid
a fourth resonator, the third stage of the ADC uses an SC resonator. The 1 mA consumed by the SC resonator is justified by
its and drift advantages. Since the SC stage operates in discrete-time, the alias protection in this modulator is not as great
as that of a fully continuous-time system. Nonetheless, the alias
attenuation is more than 80 dB, or 40 dB higher than a system
in which the AAF was separate from the ADC [3].
The final component in the modulator is a nine-level flash
ADC. The number of levels is determined by a tradeoff between the power/complexity of the flash ADC and the perfor-
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 12, DECEMBER 2002
mance/robustness of the modulator as a whole. With nine levels,
the power and complexity of the flash ADC are low while quantization noise is a small contributor to the overall noise and
the modulator is stable for inputs that are within a fraction of
a decibel of full scale. Element mismatch in the DACs is addressed by the use of a bandpass variant of the element rotation
mismatch-shaping scheme [7].
C. Noise and Power
For a quantitative demonstration of the LC tank’s ability to
provide relief from noise sources within the ADC, the LNA and
mixer will be viewed as an effective transconductance
10 mA/V. The gain of the first resonator is then
, where
is the (frequency-dependent) impedance of the tank. Since
noise added after the first resonator stage is reflected to the LNA
, the in-band power of the noise can
input by dividing by
be computed via
(1)
-
is the power
where and bound the band-of-interest and
spectral density of the noise, which is assumed to be white. If the
where
effective tank impedance is defined via
is the rms of the tank admittance
over the band of
, where
interest, i.e.,
is the width of the band-of-interest, then the in-band noise power
is given by
-
(2)
The above expression shows that, for the purpose of noise analysis, the gain from the LNA input to the output of the first resand so, the higher
onator can be considered to be
is, the greater is the suppression of noise added after the tank.
tank and a bandwidth that is 7% of the
With an ideal
,
is about 7 k ; with
20 and a
center frequency
drops to about 4 k . Using the latter figure
1% error in ,
, the effective gain to the output the first resonator is thus
for
(10 mA/V)(4 k ) 40. In contrast, due to the need to
handle a 20-dBm input without clipping, the system reported
in [3] could only support a gain of about 3 from the LNA input
to the mixer output. The present architecture enjoys a 20-dB
gain advantage because the IDAC feedback current counterbalances the majority of the mixer output current and because the
mixer output can swing above and below the supply voltage.
Approximate values for the current consumption in the ADC
are: 9 mA for the LNA and mixer (including biasing and LO amplification), 2 mA for the IDAC, 3 mA for the RC resonator (including the transconductance block connected to the LC tank),
1 mA for the SC resonator, and 1 mA for the flash converter.
As these values indicate, 2/3 of the current is consumed by the
front-end blocks. To allow reduced power consumption when
signals are small, the bias currents of the LNA and mixer can
be programmed to approximately 1/4 of their nominal values.
SCHREIER et al.: IF-DIGITIZING IC WITH 90–105-dB DYNAMIC RANGE AND 15–333-kHz BANDWIDTH
Fig. 4.
Noise sources versus AGC.
When the mixer bias current is throttled back, the maximum
mixer output current is reduced and so the 2-mA full scale
of the ADC is excessive. Reducing the ADC full scale is therefore possible and can be accomplished by reducing the full scale
of IDAC. Reducing the full scale of IDAC by a factor of 4 reduces its power consumption by the same factor and brings the
full scale of the ADC in alignment with the maximum output of
the mixer. To counteract the reduction in internal signal swing
that accompanies a reduction in IDAC’s full scale, a variableblock (labeled “VGA” in Fig. 3) provides a transconductance
which is inversely proportional to IDAC’s full scale.
The variable full scale of the ADC is similar to the function of
the VGA of Fig. 2(a) in the sense that both change the effective
gain of the signal chain and so can be used to implement AGC.
However, as described above, the main reason for implementing
a variable full scale is power savings.
Reducing the full scale of the ADC has the added benefit of
reducing the input-referred noise of a number of noise sources
within the ADC. For example, noise from the RC and SC resonators is reduced when the ADC’s full scale is reduced simply
block is large
because the transconductance of the variablewhen the ADC full scale is small. However, two other noise
sources, namely IDAC thermal noise and IDAC mismatch noise,
are also reduced when the full scale is reduced. At first glance,
this is somewhat counter-intuitive because reducing the current
in the IDAC should worsen its SNR. Both statements are true:
decreasing IDAC’s full scale increases the magnitude of thermal
and mismatch noise relative to IDAC’s full scale, but, since the
absolute value of both noise sources decreases, the input-referred noise goes down.
Fig. 4 shows the magnitude of noise sources within the ADC,
60, 1% tuning
computed for an oversampling ratio (OSR)
25, as a function of the full scale at the LNA
error, and
input. As this figure indicates, the input full scale is adjustable
from 50 to 200 mV , and the input-referred noise from all
sources, except the LNA and mixer, is smaller when the full
scale is reduced. The input resistance of the LNA is 300 , so
noise sources are shown relative to the thermal noise of a 300resistor. The LNA/mixer noise is clearly dominant, with IDAC
mismatch noise (0.3% element mismatch is assumed) and noise
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from the RC resonator plus the VGA being the next two largest
contributors. At the minimum full scale, the total noise is only
1 dB above the LNA/mixer noise, while at the maximum full
scale the total system noise is about 5 dB above the LNA/mixer
noise. In radio parlance, the system noise figure is predicted to
degrade from 8 dB at minimum AGC attenuation to 12 dB at 12
dB of AGC attenuation. The resulting “graceful degradation” in
sensitivity with increased AGC is a valued feature of a high-performance receiver.
For OSR 60, the input-referred IDAC mismatch noise is
smaller than shown in Fig. 4, dropping by 9 dB for every octave increase in OSR, thanks to the mismatch-shaping provided
by the dynamic element matching circuitry. Furthermore, since
increases somewhat with OSR (the upper bound on
is a function of the tuning accuracy and the tank ), the input-referred RC resonator noise is also smaller for OSR 60. Quantization noise and SC noise are also reduced for similar reasons
at high values of OSR. As a result of these effects, the predicted
noise figure degradation with AGC is only about 2 dB if OSR
300.
IV. DECIMATION FILTER
The purpose of the decimation filter is to produce down-sampled baseband data that is free from aliased out-of-band signals
and noise. Since the final stage of channel filtering is delegated
to the DSP, the decimation filter does not need to filter the data
down to its minimum bandwidth and instead outputs data that is
2 oversampled. The decimation filter is constructed such that
are passed with minimal attenfrequencies in
uation and are minimally corrupted by aliased signals and noise,
where is the width of the band-of-interest, while frequencies
in the remainder of the output frequency range suffer attenuation and alias corruption. In order to accommodate a variety of
signal bandwidths, the decimation factor is programmable.
As shown in Fig. 5, the decimation filter consists of four
blocks. The first block, DEC1, performs the equivalent of an
8 quadrature mix and decimation by a fixed factor of 12
filter. The second block, DEC2, contains a pair
using a
filters which decimate by a factor of , where can
of
range from 1 to 16, while the third block, DEC3, is an FIR decimation filter which decimates by a factor of either 4 or 5. The
overall decimation factor is thus 48 or 60 . The final block
normalizes the full scale of the filter outputs to within 0.15 dB
across all decimation modes.
Fig. 6 shows the functional equivalent of DEC1, followed by
its evolution to its final form. Functionally, DEC1 performs a
8 followed by decimation with a
complex mix by
complex lowpass filter. As illustrated in Fig. 6(b), this operafilters, each operating
tion can be implemented with four
on data that is zero 75% of the time, followed by a linear combifactor needed
nation of the decimated output data [8]. The 1/
in the linear combiner is implemented by multiplying the A and
C data streams by 239 while multiplying the B and D streams by
169/239. These two multiplication operations
169 since 1/
require 3 and 4 CSD terms, respectively, and are implemented
with hardwired circuitry.
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 12, DECEMBER 2002
Fig. 5. Structure of the decimation filter.
(a)
(b)
(c)
Fig. 6. Evolution of the first stage of the decimator. (a) Desired signal-processing operations. (b) Intermediate decomposition into four paths operating at f . (c)
Actual filter containing four paths operating at f =4.
In order to exploit the sparsity of the data applied to the
four integrator chains, the following polyphase decomposition
is used:
(3)
where
applied to the differentiator chains, which operate at the decimated rate. The overall operational complexity of DEC1 is approximately eight additions per input sample. Custom-routed
dynamic logic is used in DEC1 to minimize both silicon area
and power consumption.
The second and third stages of the decimator are clocked
at lower rates and so are less critical in terms of power consumption. To save area, DEC2 uses nibble-serial arithmetic and
DEC3 uses a register-file/shifter/accumulator engine with hardwired control.
Fig. 7(a) shows the frequency response of the decimation
filter for decimation factors of 48 and 300, while Fig. 7(b) shows
that the aliases which fold into the passband are attenuated by
a large factor. For decimation by 60 , the decimation filter provides at least 88 dB of image attenuation, while for decimation
by 48 the minimum image attenuation is 94 dB. The passband
ripple is about 1 dB.
(4)
V. OTHER BLOCKS
(5)
A. LNA and Mixer
(6)
The input impedance of the LNA is set higher than the 50standard because it takes less power to achieve a given noise
figure when the input impedance is high. The penalty associated with a high input impedance is that larger voltage swings
result from a particular input power, and hence linearity is degraded. With a 300- input impedance and an input power of
20 dBm, the input to the LNA is approximately 0.15 V . The
LNA’s voltage gain is 15 dB (5.6 V/V), so the output of the LNA
swings 0.9 V , which is approximately the largest signal that
can be supported with a simple common-emitter amplifier powered from a 2.7-V supply.
and
(7)
The consequence of this identity is that the integrator chains in
filters can be clocked at
4, or implemented
the four
with a single four-path integrator chain clocked at and operating on multiplexed data, followed by four small FIR filters, as
depicted in Fig. 6(c). The outputs of the FIR filters only need
to be evaluated every 12 clock cycles because their outputs are
SCHREIER et al.: IF-DIGITIZING IC WITH 90–105-dB DYNAMIC RANGE AND 15–333-kHz BANDWIDTH
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where
is the absolute value of the LNA gain. As a result,
is greater than
, and so
contributes less noise than a
would.
termination to ground of value
To allow a tradeoff between linearity and power consumption, the LNA bias current can be programmed to one of four
values from 0.5 to 3 mA. Programming is accomplished via
. To maintain a
MOS switches which alter the value of
is proconstant LNA gain, the collector load resistance
.
grammed in concert with
The output of the LNA is applied to one side of a differential
– converter [9]; the bias point for the opposite
multiside is set by an operational amplifier (opamp) whose output
tracks the dc level of the LNA output. The output of the –
converter is then chopped by a Gilbert mixing core driven by
a squared-up version of the second LO, and the output of the
mixer goes to the LC tank. As with the LNA, the mixer’s bias
current is programmable to one of four values, from 0.5 to 4 mA.
The overall noise figure of the LNA and mixer is about 7 dB;
4 dB of that noise results from the folding of image noise.
(a)
B. Synthesizers
(b)
Fig. 7. Decimation filter frequency response, f
response. (b) Folded response.
= 24 MHz. (a) Full
Two synthesizers are included on-chip to facilitate the generation of the second LO and the ADC clock. Both synthesizers use a traditional integer- architecture consisting of programmable clock/LO and reference dividers, a phase/frequency
detector and a programmable charge-pump. The VCOs and loop
filters needed to make complete phase-locked loops (PLLs) are
off-chip so that these circuits can take advantage of high-quality
passives (inductors, capacitors, and varactors). On-chip amplifiers allow the use of VCOs with low output power. Dynamic
dividers are used in the LO synthesizer’s prescaler to minimize
power consumption. The current consumed by the LO synthesizer is approximately 2 mA, while the CK synthesizer consumes about 1 mA.
C. AGC Logic
Fig. 8.
Simplified LNA and mixer schematics.
As shown in Fig. 8, the LNA is a simple resistively degenerated common-emitter amplifier. (Since the IF range spans nearly
five octaves, inductor degeneration and tuned loads are impractical.) Resistor RF sets the input impedance according to
(8)
The gain of the signal path can be set manually or adjusted
automatically by on-chip AGC circuitry. AGC is activated when
the signal at the output of DEC1 exceeds a programmable target.
Once this occurs, a constant-bandwidth AGC loop [10] tracks
the signal level and the output signal level stays constant until
the 12-dB-gain range of the ADC is exhausted. Thereafter, the
signal at the output of the decimation filter grows in proportion
to the LNA input.
To minimize the spectral spreading caused by a time-varying
gain, the gain control is continuous (i.e., the full scale of the
ADC varies smoothly with time). Continuous control is implemented by inserting an RC filter between the output of the 8-b
AGC-DAC and the analog circuitry which sets the ADC’s full
scale. The AGC set point, attack time, and decay time are all
digitally programmable.
Fig. 9 shows an annotated die photo. The total area of the
0.35- m BiCMOS die is 11 mm , with the ADC (including associated bondpads) and the digital logic each occupying roughly
40% of the available area. A significant portion of the ADC area
is allocated to the capacitor array which tunes the LC tank.
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 12, DECEMBER 2002
Fig. 11. In-band spectrum. f
MHz, and OSR 48.
=
= 103.25 MHz, f = 100 MHz, f = 26
Fig. 9. Annotated die photo.
Fig. 12. In-band spectrum. f
MHz, and OSR 900.
=
Fig. 10.
NTF and STF.
VI. MEASUREMENTS
Fig. 10 shows the measured noise density and signal transfer
function, superimposed on the theoretical curves. The good
agreement between measurement and theory shows that, even
at the maximum clock rate of 32 MHz, the DAC timing and
waveshape are close to the idealized timing and rectangular
waveshape assumed in the design phase. The measured STF is
quite flat, exhibiting a slope of 0.1 dB per 100 kHz over a span
of approximately 500 kHz.
Fig. 11 shows the in-band portion of the spectrum of the deci26 MHz, OSR 48, and maximum AGC
mated data for
(2 OSR)
attenuation. [The full spectrum extends to
270 kHz since the output is 2 oversampled.] With an input
IF of 103 MHz, the SNR is 81 dB and the spurious-free dynamic
range (SFDR) is 103 dB.
Putting the mixer in its standby mode eliminates the noise
originating in the LNA and mixer, thereby making the noise
from the ADC itself visible. Doing so results in an integrated
noise floor that is 4 dB lower than when the LNA and mixer
= 73.35 MHz, f = 68.85 MHz, f = 36
are active, indicating that the ADC noise at maximum AGC is
about 2 dB lower than the noise from the LNA and mixer. This
observation suggests that the noise estimates shown in Fig. 4 are
slightly pessimistic.
Fig. 12 shows the in-band portion of the output spectrum
when the clock frequency is set to the highest value for which
36 MHz, while OSR is set
the ADC would tune, namely
to 900 and AGC attenuation is set to maximum. Here the input
IF is 73 MHz and the observed SNR and SFDR are 92 dB and
106 dB, respectively. The skirts on the input signal are thought
to be a result of phase noise from the LO and IF signal generators, since the observed phase noise of 125 dBc/Hz at 1 kHz
offset is actually lower than the phase noise specifications of the
HP 8644B sources used during testing.
Fig. 13 shows the measured SNR as a function of the LNA
32 MHz, an input IF of 273 MHz, and
input power for
OSRs of 48 and 900. A dynamic range of 90 dB is achieved at
OSR 48, while at OSR 900 the dynamic range is 105 dB.
The decimation filter, digital logic, and output drivers consume
8.5 mA in the wide-band mode and 5 mA in the narrow-band
mode, while the analog portion of the IC consumes 17 mA in
its max-power/max-performance mode. Most of the current (11
mA) is consumed by the LNA/mixer and the feedback DAC;
SCHREIER et al.: IF-DIGITIZING IC WITH 90–105-dB DYNAMIC RANGE AND 15–333-kHz BANDWIDTH
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The combination of a mixer and a continuous-time bandpass
ADC containing an LC tank allows a superheterodyne receiver to achieve its characteristically high dynamic range with
low power consumption.
ACKNOWLEDGMENT
Fig. 13. SNR versus input power, f
32 MHz.
= 273 MHz, f = 269 MHz, f =
The unflagging and cooperative spirit demonstrated by W.
Martin, J. Cutcher, D. Flondro, M. Lenzen, M. Koenig, B. Hoon,
C. Schultz, A. Galan, P. Gailus, T. Mansfield, J. Dorevitch, W.
Turney, and others throughout the design and evaluation phase
is gratefully acknowledged. The layout and design efforts of J.
DiSpirito, C. Che, P. Chen, A. Cepeda, R. Sullivan, E. Gaft,
G. Biedermann, G. Harris, K. Brown, and P. Durant were outstanding, as were the test, evaluation, and logistics support of W.
Palmer, H. Ng, Q. Luu, P. Hendriks, R. Claypool, B. McCleod,
R. Manoogian, N. Yaghini, T. Das, and M. Moran.
REFERENCES
TABLE I
PERFORMANCE DATA
[1] This comment has been attributed to several sources, including Andrew
S. Tanenbaum, Ken Olsen and Grace Hopper.
modulator with integrated
[2] L. J. Breems et al., “A 1.8 mW CMOS
mixer for A/D conversion of IF signals,” IEEE J. Solid-State Circuits,
vol. 35, pp. 468–475, Apr. 2000.
[3] R. Schreier et al., “A flexible 10–300 MHz receiver IC employing a
bandpass sigma–delta ADC,” in Proc. IEEE RFIC Symp., May 2001,
pp. 71–74.
[4] R. Schreier et al., “A 50 mW bandpass
ADC with 333 kHz
bandwidth and 90 dB DR,” in ISSCC Dig. Tech. Papers, Feb. 2002, pp.
216–217.
[5] R. Schreier and B. Zhang, “Delta–sigma modulators employing continuous-time circuitry,” IEEE Trans. Circuits Syst. I, vol. 43, pp. 324–332,
Apr. 1996.
[6] J. A. Cherry, W. M. Snelgrove, and W. Gao, “On the design of a fourthorder continuous-time LC delta–sigma modulator for UHF A/D conversion,” IEEE Trans. Circuits Syst. II, vol. 47, pp. 518–530, June 2000.
[7] T. Shui and R. Schreier, “Mismatch shaping for a current-mode multibit
delta–sigma DAC,” IEEE J. Solid-State Circuits, vol. 34, pp. 331–338,
Mar. 1999.
[8] R. Schreier and W. M. Snelgrove, “Decimation for bandpass sigma–delta
analog-to-digital conversion,” in Proc. 1990 IEEE Int. Symp. Circuits
and Systems, vol. 3, May 1990, pp. 1801–1804.
principle: A tutorial overview,” IEEE J.
[9] B. Gilbert, “The multiSolid-State Circuits, vol. 33, pp. 2–17, Jan. 1998.
[10] J. M. Khoury, “On the design of constant settling time AGC circuits,”
IEEE Trans. Circuits Syst. II, vol. 45, pp. 283–294, Mar. 1998.
61
61
tanh
these are the only blocks which need to handle the full dynamic
range of the signal.
VII. CONCLUSION
Table I summarizes key specifications of the IC. The broad
range of input frequency, clock rate, and signal bandwidth allow
the IC to be used in a variety of narrow-band applications, while
the high dynamic range yields excellent system performance
even though the power consumption is low.
This work demonstrates that using an LC tank as the first resmodulator saves power, while keeping
onator in a bandpass
noise and distortion low. Driving the tank with the current output
from an active mixer eliminates unnecessary -to- and -toconversion, and implementing a variable full scale via the first
feedback DAC saves power and helps to reduce further noise.
Richard Schreier (S’89–M’91) received the B.A.Sc., M.S., and Ph.D. degrees
from the University of Toronto, Toronto, ON, Canada, in 1983, 1985, and 1991,
respectively.
From 1985 to 1987, he worked for Bell-Northern Research, Ottawa, ON,
Canada, and from 1991 to 1997 he was an Assistant/Associate Professor at
Oregon State University, Corvallis. Since 1997, he has been working for Analog
Devices, Inc., Wilmington, MA. He is the author of the freeware Delta–Sigma
Toolbox for MATLAB and is co-editor (with S. R. Norsworthy and G. C. Temes)
of an IEEE Press book on delta–sigma modulation.
Jennifer Lloyd received the B.S., M.S., and Ph.D. degrees in electrical engineering from the Massachusetts Institute of Technology, Cambridge, in 1989,
1992, and 1997, respectively.
She joined Analog Devices, Inc., Wilmington, MA, in 1997 as a Mixed-Signal
Designer in the High Speed Converter Group. Her current interests include highspeed and high-resolution A/D and D/A converters.
1644
Larry Singer (M’88) received the B.S.E.E. and M.S.E.E. degrees from the
Massachusetts Institute of Technology, Cambridge, in 1985 and 1987, respectively.
Since 1987, he has been with Analog Devices, Inc., Wilmington, MA, designing many high-speed, high-resolution ADC and DAC products, including
subranging and pipelined architectures on BiCMOS and CMOS processes. His
current interests include pipelined ADCs, high-speed sampling and interface
circuits, and ESD protection.
Donald Paterson (M’86) received the B.Sc. degree in electronics and physics
from the University of Edinburgh, U.K., in 1987.
He then worked as a digital VLSI designer for STC Technology and Pioneer
in the U.K., with interests including custom and semicustom design and MPEG
decoding. Since joining Analog Devices, Inc., Wilmington, MA, in 1996, his
focus in the High Speed Converter Group has been on highly integrated mixedsignal chips for both imaging and communications applications.
Mike Timko (M’76) received the S.B. and S.M. degrees in electrical engineering from the Massachusetts Institute of Technology, Cambridge, in 1970.
Upon graduation, he joined start-up Nova Devices which later became the
Semiconductor Division of Analog Devices, Inc., Wilmington, MA. In 1982, he
was named an Analog Devices Division Fellow. He has been involved in many
aspects of analog and mixed signal design and development. He has designed
or contributed to the design of temperature transducers, references, digital-toanalog and analog-to-digital converters, and system-level chips. He is currently
a designer in the High Speed Converter Group.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 12, DECEMBER 2002
Michael Hensley received the B.Sc. degree from North Carolina State University in 1997.
Since then, he has spent his time employed as a mixed signal Design Engineer at Analog Devices, Inc., Greensboro, NC. His interests and previous design
work include high-speed ADCs and mixed-signal radio IC design and modeling.
Greg Patterson (S’95–A’97) received the B.S. and M.S. degrees in electrical
engineering from the University of Tennessee, Knoxville, in 1997 and 2000,
respectively.
In the summer of 1999, he worked as an engineering intern for IBM, Research
Triangle Park, NC. In 2000, he joined Analog Devices, Inc., Greensboro, NC,
as an Analog Design Engineer. He has worked in the area of wireless communications, primarily in the infrastructure market. His interests include wireless
communications and analog design.
Kevin Behel received the B.S. and the M.S. degrees in electrical engineering
from the University of Tennessee, Knoxville, in 1997 and 1999, respectively.
In 1999, he joined Analog Devices, Inc., Greensboro, NC, as a Design Engineer working on products for the wireless infrastructure market. His interests
include analog IC design for wireless communications.
James Zhou was born in Zhejiang Province, China, on October 5, 1963. He received the B.S. and M.S. degree in electronics engineering from Zhejiang University, China, in 1986 and 1989, respectively.
He is currently a Manager of the design center of Analog Devices, Inc., Beijing, China. His interests include VLSI design and digital signal processing.