01:19
01:34
02:20
00:47
the drain and the source terminal and this current can be
controlled by applying the voltage between the gate and the
source terminal so these applied voltage generate
01:02
within the device and by controlling this electric field or in a way
by controlling this voltage we can control the flow of current
through the device so basically in this field effect transistor by
controlling the electric field we can control the flow of current s
the electric field
03:05
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01:49
02:44
volt and the positive voltage is applied between this drain and the
source terminal so as soon as we apply the positive voltage and
the electrons in this N channel will get attracted towards this
positive terminal so if you
03:03
electron starts moving towards the drain terminal and in this way
the current will establish in this N channel and if we keep on
increasing the voltage between this train and the source terminal
then the current which is flowing through the channel will inc
03:19
until all the electrons in this channel will contributes in the flow
of current and then after if we increase this voltage then the
current which is flowing through the channel will become
constant so if you see the direction of
03:26
03:44
03:54
04:14
as we apply negative voltage to the gate the electrons towards the
substrate and at the same time the holes in this p-type substrate
will also get attracted towards these electrons so in short to be the
negative voltage at the gate terminal the electrons in the channel
f you see the direction of the conventional current then it will
flow from the drain terminal towards the source terminal and for
the VDS is equal
04:16
at the same time the holes in this p-type substrate will also get
attracted towards these electrons so in short to be the negative
voltage at the gate terminal the electrons in the channel will get
recombined with this holes and
04:27
terminal the electrons in the channel will get recombined with
this holes and the rate of the recombination will depend on the at
that negative voltage so as we increase this negative voltage and
the rate of recombination will
04:36
so as we increase this negative voltage and the rate of
recombination will increase and that will reduce the number of
free electrons which is available in this end channel and
effectively it produces the flow of current so as you
04:51
05:16
05:44
05:29
terminal then the electrons which are minority carriers in this ptype substrate he'll also get attracted towards this end channel and
you do that the number of free electrons in this N channel will
increase so effectively we
05:55
06:38
06:37
whenever this vgs is positive then the number of free electrons in
the channel will increase and due to that this region where the
BJS is positive is known as the enhancement region and this
region where the vgs is negative is
06:51
region where the vgs is negative is known as depletion region but
still the relationship between this current ID and the voltage vgs
can be expressed by the same expression which was used for the
jfe t that means drain current ID is
07:16
07:54
07:39
substrate is n-type and for the P channel MOSFET now the
polarity of the applied voltage will also get reversed that means
this voltage VDS will be negative and this voltage VDS will be
positive but first of all let us see how
08:19
08:04
when VDS is negative then the holes in this p-type channel will
get attracted towards the negative terminal and the flow of holes
will be established in in this fashion and in
08:14
established in in this fashion and in this case the conventional
current will also flow in the same direction now whenever we
apply the positive value of voltage vgs then the holes will be
08:25
voltage vgs then the holes will be pushed towards the n-type
substrate and at the same time the electrons in this n-type
substrate will also get attracted towards the p-type channel and
you do that this holes and the electrons will
08:37
that this holes and the electrons will get recombined and as we
keep on increasing this voltage VDS then the number of holes in
this p-type channel will reduce and
09:04
10:18
then the drain current ID will reduce and at the pinch off voltage
this drain current ID will become zero and whenever this vgs is
negative then the value of drain current ID will be even higher
than this high DSS and similarly if you
effectively the flow of current in this p-type channel will
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00:47
and the p-type substrate. But here unlike the depletion type of
MOSFET,
there is no channel between this drain and the source terminal.
So, whenever we apply the control voltage,
between this gate and the source terminal,
01:02
02:18
Now, holes are the majority carriers in this
p-type substrate. And whenever we apply the positive voltage
at this gate terminal, then the holes which are near this oxide
layer will be pushed away
from this gate terminal. And at the same time, the electrons which
are the minority carriers in this p-type substrate
02:31
And at the same time, the electrons which
are the minority carriers in this p-type substrate will also get
attracted towards this gate
terminal. But at the lower voltage of Vgs, these electrons
will get recombined with this majority charge
02:54
02:40
But at the lower voltage of Vgs, these electrons
will get recombined with this majority charge carriers. Now, as
we keep on increasing this voltage
Vgs, then the holes will be pushed more and more deeper into the
substrate.
03:05
But due to this insulating layer, they will
not be able to cross this oxide layer. And they will start
accumulating near this
oxide layer. So, eventually, the inversion layer of free
electrons will get created near this oxide
03:31
current can flow through this channel. So, the value of the gate to
source voltage
at which this inversion layer is getting created is known as the
threshold voltage. And below this threshold voltage, there will
not be any flow of current through the MOSFET.
07:12
04:43
So, when we apply the voltage Vds, then through
the channel electrons get attracted towards this positive terminal.
And in this way, the current will establish
in this circuit.
04:57
And the conventional current will flow from
the drain terminal towards the source terminal. But now if you
observe, the width of the channel
has been reduced towards the drain side. Because now, due to the
positive voltage at
the drain terminal, this PN junction will
will get more reversed biased. And due to that, the width of the
depletion
region will increase.
05:16
get more reversed biased. And due to that, the width of the
depletion
region will increase. So, because of that, the effective channel
width towards the drain terminal will reduce. And the same
phenomenon can be also explained
in another way.
05:29
So, once we apply the drain to source voltage,
then the voltage difference between this gate and the drain
terminal will reduce. So, the voltage difference between these
two
terminals will be equal to Vgs - Vds.
05:44
And as this source or the substrate terminal
is grounded, so we can say that this difference will be equal to Vg
- Vd. So, as the value of the voltage Vd will increase,
then the difference between these two voltages
05:55
will reduce. On the other end, this source terminal is
connected to the ground terminal. So, the voltage difference
between the gate
and the source terminal will remain as it
So, due to that, the gate terminal which is
towards the drain side will be less positive than the other side.
06:17
than the other side. And hence, this region will attract fewer
electrons compared to the other side. And due to this reason, the
channel width
gets narrower as we go from the source terminal 05:12
06:26
And due to this reason, the channel width
gets narrower as we go from the source terminal towards the
drain terminal. And as we keep on increasing this voltage
Vds, then at one particular voltage, the pinch-off condition will
occur.
06:40
condition will occur. So, at that particular voltage, the drain
current which is flowing through the circuit will get saturated. So,
the voltage Vds, at which this pinch-off
condition occurs is known as the saturation voltage.
06:58
Where Vt is the threshold voltage. That means the pinch-off
condition will occur
whenever the difference between the gate and the drain terminal
is just equal to the threshold
voltage.
07:39
07:02
That means the pinch-off condition will occur
whenever the difference between the gate and the drain terminal
is just equal to the threshold
voltage. the threshold at the threshold voltage, the
channel is just getting created between the
07:12
drain and the source terminal. So, for the fixed value of Vgs, if
we further
increase the value of Vds, the voltage difference between the gate
07:24
between the gate and the drain terminal will
be even lesser than this threshold voltage. And due to that, the
channel will not get
formed towards the drain terminal. So, it appears that the current
through the
channel should become zero.
08:18
08:54
09:13
09:31
09:58
10:51
11:25
11:30
11:42
12:03
12:28
13:03
03:14
layer. And now this inversion layer will act as a
channel between this drain and the source terminal. And now,
suppose if we apply the voltage between
this drain and the source terminal, then the
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01:37
02:47
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01:19
02:45
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02:46
03:36
03:44
04:06
05:00
04:45
vgs is equal to 0 or when the control input at the gate is 0 at that
time the current is flowing through the mosfet so when the
control input is zero at that time these depletion type mosfets are
in the on condition
05:00
and when the control input is greater than the pinch of voltage at
that time only they are in the off condition so because of this
characteristic they are not preferred as the switch on the other
end the e mosfets or the
05:36
05:05
on the other end the e mosfets or the enhancement type of
mosfets starts conducting when the voltage vgs is greater than the
threshold voltage so if the input is less than the threshold voltage
then it will remain in the off condition so these e-type mosfets are
normally off devices and this characteristic is more
06:24
06:15
if these are the operating voltage and the current then the ratio of
this voltage and the current will give us the rds on and as you can
see as the voltage vgs increases then this rds on will reduce so
this rds
06:34
and the value of this rds on should be as low as possible because
as i said earlier in the on condition of the mosfet the conduction
loss of the mosfet depends on this on resistance so this is the
basic circuit of the
07:02
07:17
07:02
when this control input is low then the mosfet will act as a open
circuit and in this case
07:26
12:47
the transfer characteristic of the p-type mosfet is exactly opposite
to the n-type mosfet
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01:04
01:34
02:41
ll
02:43
00:09
03:11
04:17
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01:18
02:14
03:15
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MOSFET- Channel Length Modulation Explained
00:27
00:12
modulation in the mosfet now so far for the enhancement type of
mosfet we have assumed that when the mosfet is operating in the
saturation region then the drain current id remains constant that
means for the given value of the voltage vgs
00:42
this expression but actually if you see for the given value of the
voltage vgs as we increase the value of voltage vds then the drain
current also slightly increases and this phenomenon is known as
the channel length if vds is increased then also this drain current
remains constant
00:48
as we increase the value of voltage vds then the drain current also
slightly increases and this phenomenon is known as the channel
length modulation so let us understand exactly what happens in
this phenomenon
01:16
we have seen that as we increase the drain to source voltage then
this gate terminal will become less positive with respect to the
drain terminal that means this gate terminal will
terminal will attract a lesser electrons towards the drain side
compared to the source side or in other words the electron charge
density will be lesser towards the drain side
01:31
then the length of the channel will reduce at drain side and at one
point when the voltage vds is equal to vgs minus vt or when the
gate voltage is just one threshold voltage greater than the drain
voltage then the width of the channel will
channel will almost becomes negligible at this end because at this
end the gate to substrate potential is not enough to attract the free
electrons and we call this condition as the pinch of condition
02:27
03:17
05:19
07:01
07:10
09:23
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01:59
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MOSFET- Channel Length Modulation Explained
00:27
00:12
modulation in the mosfet now so far for the enhancement type of
mosfet we have assumed that when the mosfet is operating in the
saturation region then the drain current id remains constant that
means for the given value of the voltage vgs
00:42
this expression but actually if you see for the given value of the
voltage vgs as we increase the value of voltage vds then the drain
current also slightly increases and this phenomenon is known as
the channel length if vds is increased then also this drain current
remains constant
00:48
as we increase the value of voltage vds then the drain current also
slightly increases and this phenomenon is known as the channel
length modulation so let us understand exactly what happens in
this phenomenon
01:16
we have seen that as we increase the drain to source voltage then
this gate terminal will become less positive with respect to the
drain terminal that means this gate terminal will
terminal will attract a lesser electrons towards the drain side
compared to the source side or in other words the electron charge
density will be lesser towards the drain side
01:31
then the length of the channel will reduce at drain side and at one
point when the voltage vds is equal to vgs minus vt or when the
gate voltage is just one threshold voltage greater than the drain
voltage then the width of the channel will
channel will almost becomes negligible at this end because at this
end the gate to substrate potential is not enough to attract the free
electrons and we call this condition as the pinch of condition
02:27
03:17
05:19
07:01
07:10
09:23
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MOSFET Transconductance and MOSFET Small Signal Model
Explained
01:55
gm = transconductance
03:56
04:38
05:32
06:20
08:31
09:28
09:38
09:09
the ac signal can be assumed as 0 and similarly during the ac
analysis this dc voltage can be assumed as 0. so as you can see
under this small signal approximation the change in the drain
current 09:23
the drain current is linearly proportional to the input signal vin
and in that case the mosfet can be replaced by the small signal
equivalent model so here this vgs is the input signal which is
applied between the gate and the source terminal
10:12
so when the signal ac is too less the mosfet can be replaced by a
small signal model. which is equal to
11:46
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00:11
00:51
01:29
when Id is kept fixed the gm is proportional to W/L
W/L is kept fixed the gm = Id
01:58
03:07
03:50
04:55
05:47
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MOSFET Common Source Amplifier - Small Signal A
01:15
03:58
05:15
06:09
07:16
08:45
now when a source resistor Rs is used. it provides -ve feedback
and increases the stability of the
09:17
12:17
12:51
13:51
13:53
So, as I said, the output impedance is Thevenin's
equivalent impedance which is seen through the output side.
And to find that, we will consider all the independent sources in
the circuit as zero.
That means this input signal will act as a
14:07
short circuit.
And once we consider this Vin as zero, then these two resistors
will also get short-circuited.
And because of that, this voltage vgs is also
14:25
15:17
16:09
17:12
18:07
19:16
19:46
19:50
for small signal analysis short ckt capacitors and replace all the
dc sources by 0
19:59
20:41
21:01
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00:50
00:50
the voltage gain now let's replace this circuit by the ac equivalent
circuit so for the ac analysis this dc voltage sources will act as a 0
and if you see the equivalent circuit
01:14
01:20
if you observe then the drain and the gate terminal are connected
together and the drain terminal is connected to the ground
terminal so in the equivalent circuit it can be
01:37
01:34
signal equivalent circuit of this mosfet m2 so in case of the m2
the small signal equivalent circuit will look like this so there is a
input signal between the gate and the source terminal and the
output is measured b/w drain and source terminal
01:49
overall ckt will look like this
01:57
02:01
so as i said since the mosfet m1 is a diode connected transistor so
it can be replaced by the equivalent resistance and this resistance
is the equivalent resistance which is seen from this side so to find
the equivalent
02:16
resistance let us apply a test voltage to the m1 and let's find the
test current which is flowing through this voltage source so the
ratio of this vx and ix will gives us the equivalent
02:36
03:07
03:40
03:51
04:30
05:35
06:19
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MOSFET Common Source Amplifier - Small Signal Analysis (
Drain Feedback Bias)
01:08
01:43
08:40
09:06
10:30
11:53
12:43
13:00
13:37
now small signal analysis
13:53
14:29
14:52
15:18
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MOSFET Common Source Amplifier - Small Signal Analysis (
Drain Feedback Bias)
01:08
01:43
08:40
09:06
10:30
11:53
12:43
13:00
13:37
now small signal analysis
13:53
14:29
14:52
15:18
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04:27
05:33
05:18
optimal gain for this common source amplifier but we can obtain
this gain if the current source is the ideal current source but if we
see the actual current source then the current source has the finite
output resistance and hence
05:55
06:18
07:08
07:33
07:18
to connect a current source between the supply and some node in
the circuit then we can use the p-type mosfet so here as you can
see the source terminal is connected to the vdd
07:28
the source terminal is connected to the vdd when the fixed gate
voltage can be applied at the gate terminal and in this way this
voltage vgs can be kept fixed and at the drain terminal the
07:44
so as far as this bias voltage is kept fixed and the vgs will remain
fixed and in this way this circuit can be used as a current source
of course here to ensure the operation
08:11
08:48
09:07
10:20
10:38
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01:20
02:12
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