PCIM Europe digital days 2021, 3 – 7 May 2021
An Inverse Method to Evaluate the Chip Temperature Distribution
within Press Pack IGBT
Jie Chen1, Erping Deng1,2, Yongzhang Huang1,2
1
State Key Laboratory of Alternate Electrical Power System with Renewable Energy Sources (North
China Electric Power University), Beijing, China
2
NCEPU (Yantai) Power Semiconductor Technology Research Institute Co., Ltd, Yantai, Shandong
Province, China
Corresponding author: Jie Chen, huadianchenjie@163.com
Abstract
Press Pack Insulated Gate Bipolar Transistor (PP IGBT) is quite famous for the high power applications
but lacks in-depth reliability research, evaluation of chip temperature distribution will be more meaningful
than classical virtual junction temperature for reliability assessment. In this paper, an inverse method
combining the experimental measurement and numerical solution, called multi-current VCE (T) method is
applied to evaluate the single chip temperature distribution within PPI in the power cycling test, which
extends the capability in chip temperature measurement of the conventional VCE (T) method. Finally, the
calculated results are verified by the designed experimental measurement.
1 Introduction
Press Pack Insulated Gate Bipolar Transistors (PP
IGBTs) are being increasingly attractive in many
high voltage and high power density applications,
such as High Voltage Direct Current (HVDC)
transmission project [1]. Compared to typically
wire bonded power modules, PP IGBTs have
several superiorities due to different package
structure (see Fig. 1), e.g., double side cooling,
higher power density, and ease of connection in
series [2]. Due to the complex operating conditions
and high maintenance costs, how to improve its
reliability has attracted more and more attention
from academia and industry.
Fig. 1: Exploded view of the PP IGBTs [2]
Although the appearance of the PP IGBTs is not
too late, there is not much research on reliability,
ISBN 978-3-8007-5515-8
especially experimental investigation such as
power cycling test (PCT) [3]. The PCT is
considered as the most important test for the
reliability evaluation of power devices with
repetitive junction temperature swings which is
typically generated by on-state losses resulting
from the DC current. As early in the 1990s, the
junction temperature swing ΔTj and the mean
junction temperature Tjm were recognized as the
two important factors affecting the PCT results [4].
Thus, a precise measurement of junction
temperature is crucial for the PCT. Since a direct
measurement is not possible for packaged PP
IGBT, the method using the temperature sensitive
electrical parameters (TSEPs) is an interesting
and potential method [5]. Among these TSEPs
method, the VCE(T) method, using the pn-junction
voltage drop at a small current, has been
established as the standard method for junction
temperature measurement for IGBTs during power
cycling test [6]. However, the method can only
obtain an average junction temperature, called
virtual junction temperature, rather than the
temperature distribution.
With the ever-growing power density in power
devices, evaluation of temperature distribution will
be more meaningful than the classical virtual
junction temperature for reliability assessment.
1152
© VDE VERLAG GMBH · Berlin · Offenbach
Authorized licensed use limited to: North China Electric Power University. Downloaded on March 02,2022 at 08:59:50 UTC from IEEE Xplore. Restrictions apply.
PCIM Europe digital days 2021, 3 – 7 May 2021
Firstly, the temperature difference between the
center and the edge of a chip has easily exceed
40K for single-sided cooling IGBTs by infrared (IR)
measurement [7], but the temperature gradient of
the chip within the PP IGBT is temporarily
unknown. Although the finite-element simulation
can be used to predict the junction temperature
distribution [8], there is still no effective
experimental verification method up to now for the
simulation results. Secondly, as discussed in Ref.
[9], the variables of the CIPS 2008 empirical
lifetime model are not independent, such as the
load pulse duration ton and load current IL. It is not
possible to obtain the same ΔTj and Tjm with the
same ton but different IL or the same IL but different
ton, especially for the wide range. However, both
the IL and ton are related to the lateral temperature
gradient in the chip. As mentioned in Ref. [10], the
temperature gradient may be an option for variable
in empirical lifetime models if it can be determined
without complex simulation.
In [11], a sequential VCE(T) method with separated
gate controller is proposed to measure the junction
temperature distribution among paralleled chips
within PP IGBT, this paper will focus on the single
chip temperature evaluation using the multicurrent VCE(T) method, which essentially belongs
to an inverse method with combination of
experimental measurement and numerical solution.
Moreover, the method is applied in the DC power
cycling test and verified by the designed
experiments.
2 The multi-current VCE(T) method
2.1 Theoretical foundation
Generally, the virtual junction temperature
measured by the conventional VCE(T) method is
seen as average temperature of the chip with the
three-dimensional temperature distribution. Thus,
as long as the temperature distribution remains the
same, the virtual junction temperature is a fixed
value and will not change. In [12], the physical
meaning of the virtual junction temperature,
especially the averaging mechanisms, have been
studied in-depth combined with theoretical
analysis and electro-thermal simulation. The
results show that the virtual junction temperature is
not a fixed value and is related to the measurement
current. The smaller the measurement current, the
larger the virtual junction temperature and the
closer it is to the maximum junction temperature.
Furthermore, the root cause is also given in Ref.
[12] that the measurement current distribution has
ISBN 978-3-8007-5515-8
a positive exponential correlation with the
temperature distribution. The higher the
temperature, the higher the ratio of the
measurement current, and the positive exponential
correlation is more obvious when the
measurement current decreases, as shown in
Fig.2. It is such the coupling effect between the
measurement current and temperature distribution
that provides the theoretical foundation for the
multi-current VCE(T) method.
Fig. 2: Current distribution with temperature
different measurement currents [12].
at
2.2 Method principle
Unlike the traditional VCE (T) method measuring
the voltage at only one measurement current, the
multi-current VCE (T) method requires that the
voltages are measured at multiple different
measurement currents with the same test
conditions. The basic principle of the proposed
multi-current VCE (T) method is shown in Fig. 3.
The IGBT chip is subdivided into N parts, and all
parts are electrically paralleled. Thus, the voltage
drop across these parts is the same, and the total
measurement current is the sum of all partial
measurement currents. When power loss is
generated in the active area, the chip temperature
is not uniform and the temperature of elements at
different locations are different. According to the
results of Ref. [12], the measurement currents
flowing through each part with different
temperature are different. When VCE measurement
is performed at M different measurement currents,
there is always the above relationship established,
and a nonlinear equation group can be expressed
as:
1153
© VDE VERLAG GMBH · Berlin · Offenbach
Authorized licensed use limited to: North China Electric Power University. Downloaded on March 02,2022 at 08:59:50 UTC from IEEE Xplore. Restrictions apply.
PCIM Europe digital days 2021, 3 – 7 May 2021
1 N
­
I
° 1 N ¦ I i (Ti ,V1 )
i 1
°
°
°
1 N
°
I
® j
¦ I i (Ti ,V j )
N i1
°
°
°
1 N
°I
¦ I i (Ti ,VM )
M
°̄
N i1
(1)
distribution evaluation requires N to be large
enough, which seems to be a contradiction. In
order to greatly reduce the number of nonlinear
equations and solve this problem, the chip
temperature distribution is represented by the
quadratic function as shown in Eq. (2) since the
chip surface temperature distribution has strong
regularity.
T ( xˈ y )
The I(T,V) relationship can be obtained through
temperature calibration at different measurement
currents. So, If M ≥ N, it is theoretically possible to
solve the value of Ti in the nonlinear equations,
which represent the temperature of each part in the
chip. More description of the method is given in
[13]. However, the numerical solution of the
nonlinear equations is not an easy task if N is large.
On the contrary, the accurate temperature
p1 p2 ˄
˜ x 2 y 2˅
(2)
After substituting Eq. (2) into Eq. (1), the nonlinear
equations contain only 2 unknown parameters p1
and p2, where the p1 is the maximum temperature
at the center of the chip and the p2 represents the
temperature gradient. In theory, 2 different
measurement currents are enough to obtain the
temperature distribution. To improve the accuracy
of solving the nonlinear equations, the number of
measurement currents can be greater than 2 to
constitute the redundant equations.
Fig. 3: basic principle of the proposed multi-current VCE (T) method.
3 Experiment
For this experiment, a 3300V/75A diode chip
instead of IGBT chip is selected as device under
test (DUT) because the black coating used for
infrared will cause the gate PCB to be insulated.
The active area of diode chip is square with 10.2
mm ×10.2 mm.
3.1 I-V-T calibration
The accurate I-V-T relationship of the DUT is the
basis of the proposed multi-current VCE (T) method,
which are obtained and fitted by temperature
calibration at different measurement currents.
Generally, the calibration of power devices is
generally performed in a thermostat [14]. Raising
the temperature of the thermostat to a certain
temperature and keep it constant, then the
temperature of the DUT is the same and uniform,
ISBN 978-3-8007-5515-8
so the recorded case temperature can be regarded
as the junction temperature of the DUT. This
method requires that the DUT is small in size, so it
can be considered that the air temperature
distribution inside the thermostat is relatively
uniform and stable under a limited spatial range
and long heating time. However, there is inevitable
error exist for press-pack packaged power devices
since it has a large volume and requires a
complicated clamping force fixture, which causes
the total volume to become larger.
Therefore, based on the structure of the PP IGBT,
a double-sided heating calibration method is
proposed here, requiring the same heating power
on both sides, as shown in Fig. 4. Two heating
plates are placed on the collector side and the
emitter side to heat the DUT, and the aluminum
plate with a larger heat capacity needs to be added
between the heating plate and the DUT as a
1154
© VDE VERLAG GMBH · Berlin · Offenbach
Authorized licensed use limited to: North China Electric Power University. Downloaded on March 02,2022 at 08:59:50 UTC from IEEE Xplore. Restrictions apply.
PCIM Europe digital days 2021, 3 – 7 May 2021
thermal buffer to ensure that the heat from the
heating plate reaches the surface of DUT more
uniformly. In addition, the outside of the heating
plate is insulated with a thermal insulation plate to
ensure that the heat only flows to the DUT to
ensure the symmetry of the heat flow.
Lock nut
Force sensor
Thermal insulation board (FR4)
Heating plate
Heating plate
Aluminum plate
Groove for
thermocouple
Aluminum plate
PPI
PPI
Aluminum plate
Aluminum plate
Heating plate
Heating plate
Thermal insulation board (FR4)
Disc spring
Fig. 4: Thermal calibration fixture for PP IGBT.
Where a = 5.52×10−3, b = 24.9559, c = 0.0604, d =
1.6703×10−4.
3.2 Test setup
The multi-current VCE (T) method is applied and
verified in power cycling test at Iload=100 A, ton=20
s to investigate the junction temperature
distribution within single-chip submodule PP IGBT.
In addition, an external clamping force of 1.2 kN is
necessary to make the internal components
contact well. As mentioned in the second part, the
key to the proposed method is to apply different
measurement currents
under the same
temperature distribution. Obviously, it is
impossible to implement it in one cycle since the
junction temperature will decrease during injecting
the measurement current.
Thus, only one
measurement current is injected in each cycle, and
then others measurement currents are injected in
other cycles at the same state. During power
cycling test, all the test conditions are the same to
reach a stable junction temperature in each cycle,
so, it can be considered that the chip surface
temperature distribution of each cycle is the same,
which is the theoretical foundation of injecting
these measurement currents in different cycles. To
reduce the accidental error of measurement, each
measurement current lasts for 5 cycles and the
measured voltage VCE takes an average of 5 times.
(a) External diagram
Fig. 5: I-V-T characteristics of the DUT.
The I-V-T characteristics of the DUT are obtained
as shown in Fig. 5, which can be firstly fitted with
temperature T as a parameter, then the
appropriate fitting function are selected to perform
the fitting:
A(T ) ˜ exp >V B (T ) @
(3)
a ˜ exp T b , B (T ) c +d ˜ T
(4)
I (V , T )
A(T )
ISBN 978-3-8007-5515-8
(b) Internal structure
Fig. 6: Customized single FRD chip submodule.
Experimental verification is not an easy task for
temperature distribution evaluation within PP IGBT,
a combination of the thermocouple and IR is
adopted. The former is used to measure the
1155
© VDE VERLAG GMBH · Berlin · Offenbach
Authorized licensed use limited to: North China Electric Power University. Downloaded on March 02,2022 at 08:59:50 UTC from IEEE Xplore. Restrictions apply.
PCIM Europe digital days 2021, 3 – 7 May 2021
maximum temperature at the center of the active
area, and the latter is used to measure the
minimum temperature at the edge of the active
area. To this end, a single FRD chip submodule is
specially designed and manufactured for
experimental verification, as shown in Fig. 6. There
is a channel on the surface where the molybdenum
and the chip in contact for inserting a thermocouple.
The cross-sectional area of the channel is 0.6
mm×0.6 mm, only slightly larger than the diameter
of the thermocouple 0.5 mm, which has almost
negligible effect on the heat flow. In addition, the
components exposed to the IR camera is coated
with black paint to achieve an identical emissivity.
41.6K of traditional bond wired IGBT at a power
density of about 210 W/cm2, which indicates that
the advantages of double-sided cooling in thermal
management, not only can decrease the average
junction temperature, but also can greatly reduce
the non-uniformity of the chip surface temperature.
3.3 Experimental result
During the power cycling test, the voltage drop of
DUT at the end of each cycle is kept constant after
the thermal equilibrium is reached, which presents
that each cycle is equivalence. Finally, six different
measurement currents were chosen to perform the
measurement using the proposed method, the
results are shown in Table 1.
(a) Three-dimensional temperature distribution
Tab. 1: Measurement results of the multi-current VCE
(T) method
Measurement
current (mA)
Voltage drop
(mV)
Virtual junction
temperature (℃)
100
46.22
96.2
75
45.37
96.5
50
44.43
96.7
20
43.33
97.0
10
41.12
97.1
5
40.63
97.6
(b) Two-dimensional temperature distribution
Fig. 7: calculated chip temperature distribution
These 6 pairs of I-V values are substituted into the
nonlinear equations Eq. (1) for iterative solution,
the calculated temperature distribution is shown in
the Fig. 7, and the temperature distribution function
is:
T ( xˈ y ) 102.3 0.33˄
˜ x 2 y 2˅
(3)
The calculated maximum temperature at the chip
center is 102.3 ഒ, which is awfully close to the
101.5 ഒ measured by the thermocouple, and the
calculated minimum temperature at the edge is
85.1 ഒ, which is also very close to the 86.3 ഒ
measured by the IR, as shown in Fig. 8. The
agreement between the calculation results and
experimental results show the effectiveness and
accuracy of the proposed method. The difference
between the maximum temperature and the
minimum temperature is only 17.2K at a power
density of 283.7 W/cm2, much smaller than the
ISBN 978-3-8007-5515-8
Fig. 8: Temperature measured by the IR camera
4 conclusion
In this paper, the multi-current VCE (T) method is
applied to investigate the single chip temperature
distribution within PPI, and a combination of the
1156
© VDE VERLAG GMBH · Berlin · Offenbach
Authorized licensed use limited to: North China Electric Power University. Downloaded on March 02,2022 at 08:59:50 UTC from IEEE Xplore. Restrictions apply.
PCIM Europe digital days 2021, 3 – 7 May 2021
infrared camera and thermocouple is adopted for
experimental verification. The experimental results
are agreed with the calculated results. Some
conclusions can be drawn as follows:
1) The proposed multi-current VCE (T) method is
suitable for single chip surface temperature
distribution evaluation of PP IGBT during power
cycling test, which extends the capabilities of
conventional VCE (T) method in junction
temperature measurement.
2) Compared with traditional bond wired IGBT, the
double-sided cooling of the PP IGBT has
advantages in thermal management under the
same power density, it not only can decrease the
average junction temperature, but also can greatly
reduce the non-uniformity of the chip surface
temperature.
5 Acknowledgements
Measurement and Management Symposium,
2004.
[6] ECPE/AQG 324, Qualification of Power Modules
for Use in Power Electronics Converter Units
(PCUs) in Motor Vehicles, 2018.
[7] U. Scheuermann, R. Schmidt: Investigations on
the VCE(T)-Method to Determine the Junction
Temperature by Using the Chip Itself as
Sensor, PCIM Europe 2009, 802-807, 2009.
[8] E. Deng, Z. Zhao, Z. Lin, R. Han, and Y. Huang:
Influence of temperature on the pressure
distribution within press pack IGBTs, IEEE Trans.
Power Electronics, 33(7), 6048–6059, 2018.
[9] R. Bayerer, T. Herrmann, T. Licht, J. Lutz, M.
Feller: Model for Power Cycling lifetime of IGBT
Modules - various factors influencing lifetime, 5th
International Conference on Integrated Power
Electronics Systems, 2008.
6 References:
[10] M. Junghaenel, U. Scheuermann: Impact of load
pulse duration on power cycling lifetime of chip
interconnection solder joints, Microelectronics
Reliability, 76-77, 480-484, 2017.
[1] E. Deng, Z. Zhao, P. Zhang, J. Li and Y. Huang:
Study on the Method to Measure the Junction-toCase Thermal Resistance of Press-Pack
IGBTs, IEEE Transactions on Power Electronics,
33(5), 4352-4361, 2018.
[11] Y. Zhang, E. Deng, Z. Zhao, J. Chen, Y. Zhao:
Sequential Vce(T) Method for the Accurate
Measurement of Junction Temperature Distribution
Within Press-Pack IGBTs, IEEE Transactions on
Power Electronics, 36(4), 3735-3743, 2021.
[2] E. Deng, J. Zhang, Z. Zhao, J. Chen, J. Li and Y.
Huang: Influence of the clamping force on the
power cycling lifetime reliability of press pack IGBT
sub-module, The Journal of Engineering, 2019(6),
2435-2439, 2019.
[12] J. Chen, E. Deng, L. Xie, X. Ying, Y. Huang:
Investigations on Averaging Mechanisms of Virtual
Junction Temperature Determined by VCE (T)
Method for IGBTs, IEEE Transactions on Electron
Devices, 67(3), 1106-1112, 2020.
[3] L. Tinschert, A. Rygg Ardal, T. Poller, M.
Bohlländer, M. Hernes, et al.: Possible failure
modes in Press-Pack IGBTs, Microelectronics
Reliability,55(6), 903-911, 2015.
[13] J. Chen, E. Deng, X. Ying, Y. Huang: Temperature
Distribution Evaluation of Single Chip by Multiple
Currents VCE (T) Method, IEEE Transactions on
Components, Packaging and Manufacturing
Technology, 2020. (Early Access)
This work was supported by the National Natural
Science Foundation of China (52007061).
[4] M. Held, P. Jacob, G. Nicoletti, P. Scacco, M.-H.
Poech: Fast power cycling test of IGBT modules in
traction application, Proceedings of Second
International Conference on Power Electronics
and Drive Systems, 425-430, 1997.
[5] D.L. Blackburn. Temperature measurements of
semiconductor devices - a review, Twentieth
Annual IEEE Semiconductor Thermal
ISBN 978-3-8007-5515-8
[14] E. Deng, Z. Zhao, P. Zhang, J. Li, Y. Huang: Study
on the Method to Measure the Junction-to-Case
Thermal Resistance of Press-Pack IGBTs, IEEE
Transactions on Power Electronics, 33(5), 43524361, 2017.
1157
© VDE VERLAG GMBH · Berlin · Offenbach
Authorized licensed use limited to: North China Electric Power University. Downloaded on March 02,2022 at 08:59:50 UTC from IEEE Xplore. Restrictions apply.