Activity 1.1.6: Digital Component Identi cation
9/22/22, 2:33 PM
Activity 1.1.6
Digital Component
Identi cation
Distance Learning Support
Check with your teacher about:
□Using Multisim Live as your Circuit Design Software
□What work you need to turn in and how to submit it
□Collaboration strategies
INTRODUCTION
In this activity, you will investigate both combinational and sequential logic
gates. You will be asked to simulate simple circuits using basic logic gates. You
will then complete atruth table for each logic gate based on the outputs
generated from your simulation. The names of many of the fundamental logic
gates in digital electronics are based on the logic output from the gate. From
the analysis of atruth table, could you determine the name and understand the
function of the gate?
You will examine the basic building block of sequential logic: the
ip- op. The
investigation will conclude with alook at the 555 IC and how it Is used to trigger
events in acircuit.
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Activity I.I.6: Digital Component Identi cation
EQUIPMENT
●Computer with Circuit Design Software (CDS)
RESOURCES
^Component
Identi cation
Digital
presentation
Digital Component Identi cation Worksheet
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Procedure
Using the Circuit Design Software (CDS), create the circuit for each
logic gate shown.
Note: In each of the circuits, an input of 0occurs when the
switch is at GND. An input of 1occurs when the switch is at +5V.
Likewise, when the output probe is on, the output is a1. When
the output probe is off, the output is a0.
Combinational Logic
s i /
Presentation: Review Component Identi cation Digital.
Create the logic gate below using aswitch to provide an Input
for Xand aprobe to indicate the output at Z.
Note: To toggleE^ means to change the state of the
switch. For example, if alight switch in your home is in
the off position, you can toggle it on. Similarly, if the light
switch is on, you can toggle it off.
As shown in the circuit below, one toggle of the switch
changes its state from ground to +5 V. Another toggle would
change it from +5 Vback to ground.
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Activity 1.1.6: Digital Component Identi cation
Toggle the switch, observe output Z, and complete the truth
table in your notebook.
5 V
X
z
o
X
o
0
74LS04N
z
1
1
o
tirGND
Figure 1. Logic Gate Circuit and Truth Table
?jDistance
Learning
Support
Create the circuit in Multlsim Live and toggle the switch,
observe output Z, and complete the truth table in your
notebook.
Show circuit
From the analysis of the truth table, why do you think this is
called an “INVERTER” gate?
because the power Is invertec
Use switches for the inputs Xand Yand aprobe for the output
Z.
Toggle the switches to complete the truth table.
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Activiw 1.1.6: Digital Component Identi cation
5V
X
Y
z
Q
0
Q
>
X
Y
0
0
0
1
1
0
1
1
Z
t
74LS08N
y v
0
^GND
Figure 2. Logic Gate Circuit and Truth Table
*
?0 Distance Learning Support
●
Create acircuit in Multisim Live to complete the truth
table.
Show circuit
From the analysis of the truth table, why do you think this is
called an “AND” gate?
Zis on when xand yare on
Use switches for the inputs Xand Yand aprobe for the output
Z
Toggle the switches to complete the truth table.
5V
X
Y
z
Q
Q
O
X
Y
Z
0
1
1
1
0
1
1
1
0
X
O
74LS00N
0
^GNO
Hgure 3. Logic Gate Circuit and Truth Table
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Activit)’ 1.1.6: Digital Component Identi cation
Distance Learning Support
●
●
Create acircuit in Multisim Live to complete the truth
table.
Show circuit
From the analysis of the truth table, why do you think this is
called a“NAND” gate? (NOT AND)
Oppositeofandgate,sois~^(D^K/
Use switches for the inputs Xand Yand aprobe for the output
Z.
Toggle the switches to complete the truth table.
5 V
X
Y
z
Q
Q
Q
E>
X
Y
Z
0
0
0
0
1
1
0
1
1
74LS32N
> 7
3
^GND
Figure 4. Logic Gate Circuit and Truth Table
?0 Distance Learning Support
Create acircuit in Multisim Live to complete the truth
table.
Show circuit
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From the analysis of the truth table, why do you think this Is
called an “OR” gate?
if Xor Yare on, Zis on
Use switches for the inputs Xand Yand aprobe for the output
Z.
Toggle the switches to complete the truth table.
5 V
X
Y
z
0
Q
Q
I >
X
Y
0
0
0
1
1
0
1
1
74LS02N
y v
Z
e>
^GND
Figure 5. Logic Gate Circuit and Truth Table
●●<55
Distance Learning Support
Create acircuit in Multisim Live to complete the truth
table.
Show circuit
From the analysis of the truth table, why do you think this Is
called a“NOR” gate? (NOT OR)
if either one is on then zIs off'
Use switches for the inputs Xand Yand aprobe for the output
Z.
Toggle the switches to complete the truth table.
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Activity 1.1.6: Digital Component Identi cation
5 V
X
Y
z
Q
Q
Q
X
Y
Z
0
0
O
0
1
1
0
I
I
1
1
74LS86N
^gnd
Figure 6. Logic Gate Circuit and Truth Table
●
To Distance Learning Support
●
Create acircuit in Multlsim Live to complete the truth
table.
Show circuit
From the analysis of the truth table, why do you think this is
called an “XOR” gate? (EXCLUSIVE OR)
Only if one is on iszon
In this course, we will use 2-lnput gates predominantly.
However, gates are available that have more than two inputs.
Figure 7. A3Input AND Gate
hip-h ops
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Activity 1.1.6: Digital Compooent Identi cation
In the combinational logidi3i) circuits above, acircuit immediately
produces an output when an input is changed. As aswitch is toggled
to generate anew input, anew output is generated, and the previous
output is discarded. To have more functionality, you can combine logic
gates to create acircuit that remembers the previous output, in effect,
creating memory. These types of circuits are called sequential
logicli^ devices, where the output states depend not only on the state
of the inputs but also on the sequence in which they reached their
present states. The D ip- op is one such device.
C L K
>
>
>
>
> 0
Figure 8. DFlip- op made from NAND gates
AD ip- op has an input Dand aclock signal CLK. The clock signal is
periodic and constantly changes between 0(low) and 1(high). When it
changes, it triggers the
ip- op to process input D. The
ip- op
generates two outputs, Qand ~Q (pronounced “not Q”). If Qis 1, '“Q is
0, and if Qis 0, ~Q is 1. With every pulse of the clock, the ip- op reads
its inputs and generates output. If the input changes before anew
clock pulse, the ip- op ignores the change, keeping its current output
state until the next clock pulse. This con guration makes the device
“sequential,” allowing it to store data and act as memory.
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Activity 1.1.6: Digital Component Identi cation
A
A ip- op is represented in acircuit by a
PR
simpli ed symbol shown at right This NANDgate diagram simpli cation hides the
~Q
● » C L K
additional inputs called preset (PR) and clear
C L R
T
(CLR). These inputs are not synchronized to
the clock pulse and are used to force the ip- Figure 9. DFlipop to apreset state (high or 1), or to aclear
op symbol
state (low or 0).
Sequential Logic
You will observe a ip- op in action using the simpli ed
ip- op circuit
Using the Circuit Design Software (CDS), enter the test circuit
shown.
Use aswitch for the input Tand probes for the outputs Oand
NOT_Q.
●The 74LS74N has two inputs (Data in and aclock signal
CLK). In this circuit the clock signal input will be aswitch 7
that you ip. The Data in is tied to the NOT_Q.
●The 74LS74 also has preset and clear inputs. In this circuit
the PR (preset) and CLR (clear) are connected to 5V (high),
which makes them both inactive. These PR and CLR inputs
on the 74LS74 are said to be “ocf/Ve /oiv” inputs. (It takes a
low signal to activate them.)
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Data
Q
- Q
o
o
in
o
v c c
1
C L K
V C C
O
- I P R
ID
IQ
,ICLK-IQ
>
~ 1 C L R
74LS74N
^GND
Figure 10.74LS74N Test Circuit
-
●
Distance Learning Support
Create the circuit in Multisim Live,
oUse aDFlip-Flop from the Digital >Flip-Flops &
Latches subpalette. You can also use the
magnifying glass icon at the top of the
components palette to search for components,
oOpen the con guration pane for the DFlip-Flop,
oCheck the box ACTIVE_LOW_SET_and_RESET.
Notice, the inverted oand ~symbols appear on
the
ip- ip when you make this con guration
change. Setting the
ip- op to active low makes it
behave like the 74LS74N
ip- op circuit.
Show circuit
Also notice that the ~PR and ~CLR pins are named
SET and RESET. This is just adifferent naming
convention; the pins behave like the 74LS74N.
a. Toggle the input Tseveral times until 7is /oivand
N0T_0 is low.
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Activity 1.1.6: Digital Component Identi cation
b. Starting with the switch on GROUND, what happens to
output Owhen the switch is moved from GROUND to
VCC (5V)? This is one toggle of the switch.
it Is Increased
c. What happens to output Owhen the switch is moved
from 5V to GROUND? This is one toggle of the switch.
output is turned off
d. Toggle the switch one more time. What happened to
output O? What does this tell you about when
Qchanges (toggles) In relation to when the input at the
CLK Changes. (Helpful hint It might help to cycle
through anumber of changes to spot this relationship
of when Qchanges.)
toggled again
e. What Is the relationship of DData in to Qalways?
output of the que
f. What Is the relationship of Qto NOT_Q always?
opposite in value
g. The 74LS74N is called a“ ip- op”. Based on your
observations, can you explain the relationship between
the DData In, Q, NOT_Q, and the CLK signal? What
does a ip- op do?
it
ips the output
Later in this course, we will learn how to combine
transitions to desired outputs. The
ip- ops to make
ip- op is holding abit of
information, waiting for asignal to change (memory). But in this
example, you are making the transition by
we make the
ipping aswitch. How can
ip- op change without us providing the input directly?
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aclock can do It automatically
A
Clock Signals (The 555 Timer)
Using the Circuit Design Software (CDS), create the three
LM555CN test circuits shown below on the same sheet. The
555 Timer Oscillator is one of the most common circuits used
in introductory electronics. We will use this design to generate
aclock signal in aRandom Number Generator (our
rst full
circuit design). We will look more closely at this circuit in the
next lesson. In each of the three circuits, the only value that is
changed is capacitor C2.
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Figure 11. Circuit A
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Figure 12. Circuit B
LMSS9CN
■* C 2
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Figure 13. Circuit C
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Activity i.1.6: Digital Component Identi cation
●
●
Distance Learning Support
In Multisim Live,
●Select the TLC555 Timer from the Analog >Timers
subpaiette.
●Select aCapacitor from the Passive subpalette.
Show circuit
Due to different optimization times in Multisim Live, use a
value of 50 pF for capacitor C2. For part (a) below, use a
value of 5pF. For part (b), use avalue of 250 pF.
a. When C2 is changed from 12 pF to 6pF, what happens?
speeeds up
b. When C2 is changed from 12 pF to 24 pF, what happens?
slows down
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Activity 1.1.6: Digital Component Identi cation
^CAREER
CONNECTIONS
Combining Analog and Digital Technology
Jack Dorsey and Jim McKelvey co¬
founded Square, Inc—now Block, Inc—in
2009. Their
rst product, the Square card
reader, opened an opportunity for small
businesses to securely process acredit
Square Reader Attached
to Smartphone
Source
card payment using amobile device.
The card reader is an integral part of the credit card processing
system.
How do card readers work?
The Square reader is an adaption of technology previously
perfected to allow asound recording stored on along magnetic
tape to be played through speakers.
The Square functions similarly, where instead of
along magnetic tape, ashort magnetic
stripeti^ on acredit card is swiped through a
Analog Square
Reader
slot on the reader. As the magnetic stripe moves
past areader in the slot, it induces avoltage,
which the reader detects as analog signals and
passes through an analog audio plug. The Square app converts
the analog signals into adigital format that represents the card
information, which the Square POS app uses to process the
payment.
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Activity 1.1.6: Digital Component Identi cation
CONCLUSION
1Can you combine the 555 Timer circuit with the ip- op circuit so the
changes on the
ip- op happen without your input at arate you desire?
Share this simulation with your instructor.
Proceed to next activity
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