Diamond™ Series
Mixed Signal (MultiWave)
Applications
Student Guide
PN: 071-0961-00, January 2008
Credence Systems Corporation
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Milpitas, CA 95035
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© 2008 Credence Systems Corporation
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Revision History
This table lists the revision history for this publication for the current revision and the previous two revisions (if applicable).
2
Date
Part Number
Notes
01-2008
071-0961-00
First production release.
PN: 071-0961-00, January 2008
CONTENTS
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Prerequisites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Completion Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Related Courses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Course Schedule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Day 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Day 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Day 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Document Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Reader Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Safety Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Caution Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Warning Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Danger Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1 - Personnel Safety and Equipment Protection . . . . . . . . . . . . . . . . . . . . . 13
Personnel Safety and Equipment Considerations . . . . . . . . . . . . . . . . . . . . . . . . . .
Operator Safety Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Service Safety Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electromagnetic Compatibility Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Static Electricity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Materials to Avoid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Materials to Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Working With Static-Sensitive Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fire Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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2 - Mixed Signal Help Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Online Help Lab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3 - Hardware Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Hardware Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD1096-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VIS16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VIS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DPS16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DIB Utility Instrument . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MultiWave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4 - Software Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Software Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Linux OS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diamond Series Directory Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Programming Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Integrated Test Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Program Developer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Compiling and Linking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Wavetool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Create Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Algorithm Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Online Debug and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Offline Debug and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operator Interface Control Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSP Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AWT Lab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simulate ADC DNL/INL Ramp Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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5 - Defining Mixed Signal Resources and Signals . . . . . . . . . . . . . . . . . . . 59
Defining Tester Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mapping Signals to Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Defining STIL Signals and SignalGroups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Defining Signals and SignalGroups Lab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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6 - DIBU for Mixed Signal Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
DIBU Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming the DIBU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSCDIBStatus CSCDIBUPerSignalInterface::getDIBStatus . . . . . . . . . . . . . . .
setCBits(vector< unsigned long long > & cBitValue ) . . . . . . . . . . . . . . . . . . . .
setCBits ( const unsigned long long cBitValue ) . . . . . . . . . . . . . . . . . . . . . . . .
unsigned long long getCBits ( ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
unsigned long long getCBits ( std::vector< unsigned long long > & cBitValue )
unsigned long long readCBits ( ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
unsigned long long readCBits ( std::vector< unsigned long long > & BitValue )
connect ( ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
disconnect ( ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSCConnectStatus getConnectStatus () . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
turnOnSupply ( CSCSupplyMode supplyMode ) . . . . . . . . . . . . . . . . . . . . . . . .
turnOffSupply () . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSCSupplyStatus getSupplyStatus ( ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSCDIBUChannelType getChannelType ( ) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Debugging DIBU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DIBU Lab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Contents
7 - MultiWave Instrument . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
MultiWave Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Arbitrary Waveform Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
High Precision (Audio) Generator Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Waveform Digitizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
High Precision (Audio) Digitizer Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
High Frequency (Video) Generator Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
High Frequency Video Digitizer Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
PMU Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
MultiWave Resource Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Example project.res File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
MultiWave Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Example project.sig File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
MultiWave API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
CSCMultiWaveDDSPerSignalInterface Class . . . . . . . . . . . . . . . . . . . . . . . . . . 98
CSCMultiWaveClockPerSignalInterface Class . . . . . . . . . . . . . . . . . . . . . . . . . 98
CSCMultiWaveOutputCtrlPerSignalInterface Class . . . . . . . . . . . . . . . . . . . . . 99
CSCMultiWaveInputCtrlPerSignalInterface Class . . . . . . . . . . . . . . . . . . . . . . 101
CSCMultiWaveMemoryPerSignalInterface Class . . . . . . . . . . . . . . . . . . . . . . 105
CSCMultiWaveMuxPerSignalInterface Class . . . . . . . . . . . . . . . . . . . . . . . . . 106
CSCMultiWaveArmCtrlPerSignalInterface Class . . . . . . . . . . . . . . . . . . . . . . 107
CSCMultiWavePmuPerSignalInterface Class . . . . . . . . . . . . . . . . . . . . . . . . . 107
MultiWave Trigger Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Definition of Waveform Object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
CSCMultiWaveArbitraryWave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
CSCMultiWaveSineWave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
CSCMultiWaveRampWave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Low Frequency AWG Programming Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Low Frequency Digitizer Programming Overview . . . . . . . . . . . . . . . . . . . . . . . . . 116
High Frequency AWG Programming Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
High Frequency Digitizer Programming Overview . . . . . . . . . . . . . . . . . . . . . . . . 118
Precision Kelvin PMU Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Programming Clocks on MultiWave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Clock Setup for HF AWG and HF DIG Mode . . . . . . . . . . . . . . . . . . . . . . . . . 120
Clock Setup for LF AWG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Clock Setup for LF DIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Debugging MultiWave Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
MultiWave Loopback Lab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
8 - VIS16 Instrument . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
VIS16 Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VIS16 Resource Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VIS16 Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VIS16 API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSCVISInterface Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSCVISPerSignalInterface Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Debugging VIS16 Tests—Visualize Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Debugging VIS16 Tests—Shmoo and Margin . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VIS16 Loopback Lab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VIS16 Through Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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9 - Triggering Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Triggering Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD1096-16 Triggers Available . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VIS16 Triggers Available . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MultiWave Triggers Available . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Triggering Lab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Triggering MultiWave with a DD1096 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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10 - Digital Source and Capture in Mixed Signal . . . . . . . . . . . . . . . . . . . . 161
Digital Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Capture Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DCM Capture Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DCM Lab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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11 - DAC Tests Using MultiWave DIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Analog Waveform Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Waveform Digitizer Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Scaling and Level Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog-to-Digital Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage and Digital Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . .
DAC Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Static Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dynamic Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DAC Testing Using a Digitizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Linearity Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Common Formulas and Computations for Static DAC Tests . . . . . . . . . . . . . .
Dynamic Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Common Formulas and Computations for Dynamic DAC Tests . . . . . . . . . . .
Sampling Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Spectral Leakage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Aliasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digitizer Example Code Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trigger Implementation to Start Digitizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DAC Tests Lab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
170
170
171
171
171
172
173
173
174
175
175
176
177
178
179
182
183
185
186
190
12 - ADC Tests Using MultiWave AWG . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Waveform Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Waveform Source Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Waveform Source Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Waveform Memory and Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
194
194
195
195
PN: 071-0961-00, January 2008
Contents
Digital-to-Analog Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Scaling and Level Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADCs Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical ADC Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Static Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dynamic Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Testing Using an Analog Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Static Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Integral Non-Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Histograms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dynamic Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AWG Example Code Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Waveform Generation Using Internal Sinewave . . . . . . . . . . . . . . . . . . . . . . .
Waveform Generation Using the rampWave . . . . . . . . . . . . . . . . . . . . . . . . . .
Trigger Implementation to Start AWG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dynamic ADC Test Lab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Static ADC Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
195
196
196
197
197
198
199
200
200
200
205
206
207
208
209
209
210
214
216
13 - Advanced Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Advanced Waveform Capture Topics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Notch Filter for Audio Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Equivalent Time Sampling or Undersampling . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sampling Theory Lab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Method 1—Whole UTP Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Method 2—Skip Minimum Cycles Method . . . . . . . . . . . . . . . . . . . . . . . . . . .
Method 3—Minimum Sample Time Method . . . . . . . . . . . . . . . . . . . . . . . . . .
220
220
221
225
227
227
228
228
A - Devices Data Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
LT1121 Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
AD5541 Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
MAX195 Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
B - Loadboard Schematic Extracts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
C - VHDM Connector Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
D - Loadboard Design Rules for MultiWave . . . . . . . . . . . . . . . . . . . . . . . . 299
AWG Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digitizer Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PMU Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AGND/DGND Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GND_SENSE Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal and Layer Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MultiWave Instrument Connection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
299
299
300
300
300
301
302
7
Contents
E - Diamond Series Basic Program Development . . . . . . . . . . . . . . . . . . 307
Generating the STIL File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Starting Integrated Test Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Generating the Resource Definition File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Generating the Signal Map File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Generating the C++ Header File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Editing the Header File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Generating the C++ Source File for a Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Editing the C++ Source File for a Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Generating the C++ Source File for user_main() . . . . . . . . . . . . . . . . . . . . . . . . .
Editing the C++ Source File for user_main() . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Generating the Job File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Building the Job File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loading the Job File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enabling Datalog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Running the Job . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Generating the Binning Definitions File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Generating the Binning Map File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Editing the Binning C++ Source File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adding Binning to user_main() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adding Binning to the Job file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recompiling the Job File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reloading the Job File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
308
311
313
317
320
321
322
323
324
325
326
331
333
334
337
338
341
344
346
348
351
353
F - Credence Unified Robot Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Production Robot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test System API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test System Communications Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIB ANSI Connector/IEEE 488 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . .
RS-232 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CURI_CONF.XML Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Default Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Equipment Entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example Code Using Direct Communications Access . . . . . . . . . . . . . . . . . .
uf_series_maps.XML Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A (String):XY Travel (Absolute Distance) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
H:Multisite Location No. Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I:Index Size Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Writing CURI Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Creating a Handler Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Putting It All Together . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ready to Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using NI SPY to Log GPIB Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
355
355
356
357
358
359
360
362
362
363
372
373
373
374
374
379
379
385
385
387
PN: 071-0961-00, January 2008
Preface
This course is designed to provide the student with the skills necessary to develop and
debug a mixed signal test program on the Diamond™ Series test system. Training
includes creating a test using C++ and STIL files, and running and debugging a test using
software tools.
This is a three day classroom course.
Prerequisites
Before attending this course, students must have:
•
Attended the Diamond Series Basic Applications course
•
Knowledge of semiconductor testing concepts
•
Ability to read and interpret device specification sheets
•
Knowledge of mixed signal testing
Note — Those students with no previous mixed signal testing experience must take a
course in Mixed Signal Test Methodology before attending this course.
In addition, it is recommended that students have:
•
C or C++ programming experience
•
Familiarity with Unix or Linux operating system
Completion Requirements
Completion certificates are awarded based upon:
•
Completion of all laboratory assignments
•
Class participation
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
9
Preface
Related Courses
Other related courses include:
•
Diamond Series Digital Applications
•
Diamond Series APG Applications
•
Diamond Series RF and Baseband Applications
•
Diamond Series Basic Maintenance
Course Schedule
Day 1
•
Diamond Series Online Help
•
Diamond Series Hardware Overview
•
Diamond Series Software Overview
•
Signal definition in mixed signal
•
DIBU overview
•
MultiWave overview
•
VIS16 overview
•
Triggering overview
•
DCM overview
•
DAC test
•
ADC test
•
Advanced sampling techniques
Day 2
Day 3
10
PN: 071-0961-00, January 2008
Preface
Document Conventions
Reader Notes
Notes to the reader are identified by the word Note in bold font. Reader notes either
precede or follow the information to which they apply, depending on context.
Note — The bolded Note draws attention to issues other than personnel safety or
equipment protection.
Safety Statements
Safety statements in this manual are indicated by a Caution, Warning, or Danger note to
alert users about specific types of hazards.
Caution Statement
Caution — The caution statement provides information essential to avoiding loss of
data, program failure, or equipment damage.
•
This statement is not used for a personal injury hazard. The hazard can only
result in property damage or loss.
•
Hazard is not immediate.
•
Safety is contingent upon following the message instructions.
Warning Statement
Warning — The warning statement provides information essential to the safety of
the operator.
•
Hazard is not immediately accessible.
•
One level of protection is present between a person and the hazard.
•
Hazard can result in personal injury.
Danger Statement
Danger — The danger statement indicates that an imminent hazard exists.
•
Hazard is immediately accessible.
•
Hazard will result in personal injury.
•
Safety is dependent upon awareness and skill.
•
No safeguards are provided.
Diamond ™ Series Mixed signal Applications– Student Guide
11
Preface
Notes
12
PN: 071-0961-00, January 2008
1
Personnel Safety and Equipment
Protection
Goal
Familiarity with general electrical and safety concepts.
Objectives
After completing this unit, students should be able to:
•
Discuss the symbols and components used in maintaining safety
•
Learn general electrostatic discharge guidelines
In This Module
______
______
Instructor Presentation
Knowledge Check
15
5
Minutes
Minutes
Resources
Diamond Series Online Help
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
13
1 – Personnel Safety and Equipment Protection
Personnel Safety and Equipment Considerations
The safety considerations specified in this document meet the SEMI S2-93 safety
standards as well as those of Underwriters Laboratories (UL), Factory Mutual, Canadian
Standards Association (CSA), and VDE (Verband Deutscher Elektrotechniker
(Association of German Electrical Engineers)).
Product safety information is intended to:
•
Help prevent damage or injury to data, equipment, and personnel
•
Observe government-mandated requirements for safety issues
•
Comply with safety requirements in countries where Credence products are sold
These requirements apply to instructions, operators, maintenance, and service for
semiconductor test systems and associated apparatus manufactured by Credence
Systems Corporation.
14
PN: 071-0961-00, January 2008
Operator Safety Summary
Operator Safety Summary
The operator safety information shown in Table 1 is intended for operating and service
personnel. Specific warnings and cautions throughout this manual may not appear in this
summary.
Table 1. Operator Safety Summary
Terms and Symbols
Description
Terms in this manual
Caution statements identify conditions or practices that could result in
damage to the equipment or other property.
Warning statements identify conditions or practices that could result in
personal injury or loss of life.
Terms as marked on
equipment
Caution indicates a personal injury hazard or a property hazard
including the equipment itself not immediately accessible when reading
the marking.
Danger indicates a personal injury hazard immediately accessible
when reading the marking.
Symbols as marked on
equipment
Danger—High Voltage
Attention
Protective ground (earth) terminal
Power source and
ground
This equipment operates from a power source that applies dangerous
voltage between the supply conductors, and between any supply
conductor and ground.
If the ground connection is interrupted, all accessible conductive parts
could render an electric shock.
If a power cord is not provided with the product, refer to qualified
service personnel.
Do not remove covers
or panels
To avoid personal injury, do not remove product covers or panels.
Do not operate the product without the covers and panels installed.
Refer installation to qualified service personnel.
Do not operate in
explosive atmospheres
To avoid explosion, do not operate this equipment in an explosive
atmosphere unless it has been specifically certified for such operation.
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
15
1 – Personnel Safety and Equipment Protection
Service Safety Summary
The service safety summary in Table 2 is for qualified service personnel only (also see
"Operator Safety Summary" on page 15).
Table 2. Service Safety Summary
Statement
Description
Do not service alone
Do not service or adjust this product internally unless another person
capable of rendering first aid and resuscitation is present.
Use care when
servicing with power on
Dangerous voltages and currents may exist at several points in this
product or in the equipment with which this product is used.
To avoid personal injury, do not touch exposed connections and
components while power is on.
Disconnect power before removing protective covers and making
internal changes.
Do not wear jewelry
Remove jewelry prior to servicing.
Rings, necklaces, watchbands, and other metallic objects could come
into contact with dangerous voltages or currents.
Power source
This product is intended to operate from a single-phase AC power
source with 90-264 VAC, 50/60 Hz. The power source can be L1-L2Ground or L-N-Ground.
Refer to the installation instructions before attempting to connect the
product to a power source.
Grounding the product
The product is grounded through the protective grounding conductor of
the power cord (or service wiring in lieu of a power cord).
To avoid electrical shock, the grounding conductor must be connected
to a properly wired receptacle or junction box.
Replace covers
To avoid injury to other personnel, replace covers before leaving the
equipment unattended.
Lifting
Two or more persons may be needed to lift and maneuver equipment
such as a testhead and rack-mounted units because of their physical
size, shape, weight, or location.
To avoid injury, do not attempt to handle this type of equipment alone.
16
PN: 071-0961-00, January 2008
Electromagnetic Compatibility Immunity
Electromagnetic Compatibility Immunity
Do not use hand-held wireless communication devices within 10 meters (32.8 feet) of the
test system to avoid the possibility of erroneous data or misclassification of devices under
test.
Accessibility of electro static discharge (ESD) sensitive devices and wiring in the vicinity
of the testhead requires that users wear a grounded wrist strap at all times. A wrist strap
ground points are located on the system.
Other ESD abatement practices should also be implemented, such as the use of ESD
abatement flooring, conductive shoe straps, ESD preventive coat, and ESD wrist strap
connectivity monitors.
Static Electricity
Many electronic devices used in test-station circuitry can be damaged by static discharge.
Test-station accessories include a static-discharge wrist strap, which the operator or
service technician should always wear when working with static-sensitive devices such as
circuit boards.
Although the wrist strap discharges static buildup, it presents a high impedance to ground
to limit the current should the wearer come in contact with a high voltage source.
Therefore, despite wearing the strap, it is possible to generate a static charge through
improper procedures and retain it long enough to damage the equipment or compromise
a device test.
Materials to Avoid
The following materials can damage static-sensitive devices:
•
Polystyrene foam items such as Styrofoam cups and packaging materials
•
Clear plastic bags
•
White or gray packaging foam
•
Clear bubble pack
•
Non-conductive plastic containers such as plastic trays and parts bins
•
Plastic items such as vinyl combs, brushes, and notebooks
•
Transparent tape
•
Clear plastic sheets such as page covers
•
Clear film products such as Kodagraphs
•
Candy wrappers and peanut bags
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
17
1 – Personnel Safety and Equipment Protection
Materials to Use
The following materials can be used with static-sensitive devices:
•
Wood
•
Cotton cloth
•
Pink poly bags
•
Metallized bags
•
Conductive plastics
•
Metal tools
•
Silverstat solder suckers
Working With Static-Sensitive Devices
All circuit boards that contain semiconductors (such as transistors, FETs, ICs, and CMOS
ASICs) should be moved between the test system and a shipping container or static free
work area only in conductive containers (such as metallized bags).
Place an unprotected circuit board on an antistatic mat or install it in the system. Do not
handle it without wearing a wrist strap.
To handle circuit boards with the least risk of damage to devices, take the following
precautions:
1. Wear a wrist strap connected to a convenient ground.
2. Set a conductive container (metallized bag) on an antistatic mat.
3. Remove the circuit board and place it in the metallized bag.
4. Move the bagged circuit board to a shipping container or to the next static controlled
work area. The user does not need to wear the wrist strap for this step.
Fire Protection
Locate fire extinguishers, approved for electrical equipment, within easy reach of the
system. If overhead sprinklers are installed in the test area, direct sprinkler heads away
from the testhead and power server to minimize water damage in case of fire.
For added protection, provide a separate storage area for system documentation,
software tapes and disks, and spare parts.
18
PN: 071-0961-00, January 2008
Electromagnetic Compatibility Immunity
Knowledge Check
1. What is ESD?
2. What are some of the safeguards for ESD?
3. When is it necessary to observe ESD precautions?
4. When is a system most vulnerable to ESD hazard?
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
19
1 – Personnel Safety and Equipment Protection
Check Your Work
Review the answers and have the instructor sign off this module.
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2
Mixed Signal Help Resources
Goal
Access and use Online Help and API documentation.
Objectives
After completing this unit, students should be able to use the ITE Online Help
to answer questions about how to program the Diamond Series test system
in the mixed signal context
In This Module
______
Lab Exercise
15
Minutes
Resources
Diamond Series Online Help
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
21
2 – Mixed Signal Help Resources
Lab Exercise
Online Help Lab
This lab uses the ITE Online Help to answer questions about the Diamond Series test
system when used in mixed signal context.
Note — The API documentation is found in Online Help at: Diamond Series Online Help >
Programming Reference > API Documentation.
To complete this lab:
Launch ITE from the home directory and use the Help > Online Help menu to answer the
following questions:
1. What is the name of the API class used to program MultiWave instrument?
2. What is the signal mapping for a multiwave instrument?
3. What are the choices for the path on a multiwave AWG/digitizer?
4. What is the name of the API class used to make DSP computations?
5. What API is used to set the modulation gate on a VIS16?
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6. What is the size of the capture memory (DCM) on a DD1096-16?
Check Your Work
Review the work and have the instructor sign off this module.
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
23
2 – Mixed Signal Help Resources
Notes
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3
Hardware Overview
Goal
Understand the hardware in use during the course.
Objectives
After completing this unit, students should be able to:
•
Describe the mixed signal instrument features and specifications
•
Understand the MultiWave instrument
•
Understand the DCM used inside the DD1096 instrument
In This Module
______
______
Instructor Presentation
Knowledge Check
40
5
Minutes
Minutes
Resources
Diamond Series Online Help
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
25
3 – Hardware Overview
Hardware Overview
Figure 1. Diamond Series Test Systems
Instruments
There are several different instrument cards that can be installed into the testhead.
Additional instruments may be added in the future. At this time, the available instruments
include:
•
DD1096-16 (DPIN96)
•
VIS16
•
VIS2
•
DPS16
•
DIBU
•
MultiWave (replacement for MSAWG and MSDIG)
Figure 2. Diamond Series Instrumentation
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Hardware Overview
DD1096-16
The DD1096-16 (DPIN96) is a 96 channel digital subsystem instrument.
Figure 3. DD1096-16 Instrument
VIS16
The features of the VIS16 voltage/current source are:
•
Single-Ended
•
All channels four quadrant source/measure current/voltage
•
Voltage Force/Meas ranges: from ±2 V to ±60 V
•
Current Force/Meas: from ±300 nA up to 300 mA
•
Per channel AWG and digitizer
•
Timers and TMU per channel
•
Gangable by pair
•
Differential measurements between adjacent channels
Figure 4. VIS16 Instrument
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
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3 – Hardware Overview
VIS2
The VIS2 is a dual channel voltage and current (VI) source. Some of the features of the
VIS16 voltage/current source are:
•
All channels four quadrant source/measure current/voltage
•
Voltage Force/Meas ranges: +100 V/-100 V four quadrants
•
Current Force/Meas: from 200 nA up to 20 A pulsed (5 A continuous)
•
Per channel AWG and digitizer
•
Timers and TMU per channel
•
Gangable by pair
•
Differential measurements between adjacent channels
Figure 5. VIS2 Instrument
DPS16
The DPS16 is a 16 channel Device Power Supply (DPS). It has the following features:
•
6 V voltage range
•
2 A current per channel, gangable to 16 A
•
Current ranges: -100 µA to 2 A per channel
Figure 6. DPS16 Instrument
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Hardware Overview
DIB Utility Instrument
The DIB Utility instrument contains:
•
•
•
•
•
Loadboard reference clocks:
–
400 MHz calibration reference clock—Used for calibration routines
–
10 MHz reference clock—Synchronizes device or equipment reference clocks to
the system reference clock
–
DUT clock (CLK_DUT)—Synchronizes the system clocks to an externally
supplied clock
Loadboard power supplies:
–
±5 V @ 3 A user power supply
–
+5 V @ 5 A relay power supply
–
+12 V @ 2 A user power supply
–
+24 V @ 2 A isolated power supply (floating from ground)
Loadboard utilities:
–
Control bits (CBITs)—64 bits that control relays and logic on the loadboard
–
DIB present—Detects whether or not the loadboard is connected
–
Calibration bus (6 wire)—Provides the link to the external meter
–
DIB ground sense—Provides the loadboard ground sense
Loadboard busses:
–
ID programmable read only memory (IDPROM) bus
–
General Purpose Inter-IC (I2C) bus
–
Serial Peripheral interface (SPI) bus
–
General Purpose Input Output (GPIO) bus
–
Scope Test Point (TP) bus
Power supplies for third party cPCI instruments:
–
48 V system power
–
+5 V @ 10 A power supply
–
±12 V @ 2 A power supply
The DIB Utility instrument must reside in slot 9.
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
29
3 – Hardware Overview
MultiWave
The MultiWave instrument is a quad channel arbitrary waveform generator and digitizer
unit.
Figure 7. MultiWave Instrument
Four wide bandwidth generator channels and four wide bandwidth digitizer channels are
integrated into a single board. In addition to the converter path every I/O channel has a
separate high precision Kelvin PMU for parallel DC parametric tests.
Figure 8 shows how these products apply to today’s device technologies.
Figure 8. Range of Applications By Device Type
24
Audio
22
20
Effective Bits
18
16
14
ADSL
3G BB
Modem
DVD/DTV
12
Video
Graphics
2G BB
10
8
1 MHz
10 MHz
100 MHz
Bandwidth (Log Scale)
The MultiWave is a multi-band, multi-channel arbitrary analog waveform generator
(AWG) and digitizer (DIG). It offers both high frequency and high resolution performance.
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Hardware Overview
Figure 9. MultiWave Block Diagram
Channel 7
Channel 5
Programmable
Ref Clock #1
High
Gain/Filter/
DA Resolution
Amplifier
Gain/Filter/
DA Hi
High-Speed
CLK
Speed
Amplifier
PMU select
ADC
ADC
PMU
Trigger
MUX
DUT Interface
PMU
Amplifier
Gain/Filter/
Amplifier
Gain/Filter/
Amplifier
High
Res
AD HiResolution
ADC
High-Speed
AD
Clock2
PMU
DA
SRAM
Input
mode
SRAM
+ Supply
Monitoring
48 V
DIG ch1
DIG ch2
DIG ch3
Filter
selection
GB
clock
Filter
selection
Range
selection
Input
MUX
DIG ch4
InputTransiver Data
GigaBit
mode
GigaBit Transiver Trigger
DA
Channel 6
High
Resolution
High-Speed
Channel 4
SRAM
GB
clock
High
Speed
AD HiResolution
DAC
DAC AD
High-Speed
Amplifier Control
selection
CLK
Hi Res
select
DAC
High
Gain/Filter/
DA Resolution
Amplifier
Gain/Filter/
DA
High-Speed
Amplifier
GigaSampler CLK
Gain/Filter/
Amplifier
Range
selection
DC / DC
Channel 3
Channel 1
GB
clock
GigaSampler CLK
Gain/Filter/
Amplifier
SRAM
Gain/Filter/
PMU
PMU
AD
High
Resolution
Filter
selection
GB
Filter
clock
selection
GB
clock
Channel
FPGA
Control
GigaSampler CLK
selection
Gain/Filter/
SRAM
Amplifier
Gain/Filter/
Ref Clock
Generators
350 .. 400 MHz
PMU
ADC
Range
selection
SRAM
Channel 0
Output
mode
PMU
DAC
SRAM
PMU
SRAM
PCI
Channel 2
Trigger
AWG
ch1
Output
GigaBit
Transiver Data
mode
GigaBit Transiver Trigger
Range
selection
Channel
FPGA
Clock1
Channel
FPGA
Output MUX
Output
MUX
AWG ch2
AWG ch3
Bus Interface
FPGA
AWG ch4
GigaBit Transiver Data
The MultiWave is made of four fully independent channels source and four fully
independent channels measure. It has a very flexible triggering system with 10 input lines
and 10 output lines. High-speed or high resolution are selectable per channel and it has a
set of differential filters on each AWG/digitizer.
Each channel (one AWG and one digitizer) has its own PMU to perform static
measurements. Each MultiWave channel also has it's own sampling clock derived from
two on-board master clocks.
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
31
3 – Hardware Overview
Notes
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Hardware Overview
Knowledge Check
1. Which set of instruments are used to test a DAC?
2. Which set of instruments are used to test an ADC?
3. Which instrument can drive relays?
4. What is the memory depth for the digital capture on DD1096-16?
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
33
3 – Hardware Overview
Check Your Work
Review the answers and have the instructor sign off this module.
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4
Software Overview
Goal
Understand the software use for mixed signal tests.
Objectives
After completing this unit, students should be able to:
•
Understand software available for program generation
•
Understand software available for program debugging
•
Review the Diamond Series software structure
•
Learn about the Analog Wavetool and DSP library
•
Refresh on ITE and OIC
In This Module
______
______
______
Instructor Presentation
Knowledge Check
Labs
50
5
1
Minutes
Minutes
Hour
Resources
Diamond Series Online Help
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
35
4 – Software Overview
Software Overview
The Diamond Series software has several components to consider:
•
Linux® operating system
•
Diamond’s Integrated Test Environment (ITE) and directory structure
•
AWT for mixed signal analysis
•
OIC Tool
•
DSP library
Linux OS
The Linux OS provides Unix-like functionality to systems with traditional PC-based
hardware. The Diamond Series uses Red Hat® Enterprise Linux 3 with the K Desktop
Environment (KDE).
Figure 10. Linux with KDE
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Diamond Series Directory Structure
Diamond Series Directory Structure
The Diamond Series software resides in the /usr/dmd/ directory (see Figure 11). The
$DMD environmental variable points to the /usr/dmd/<version>/system directory. Note
that MultiWave is supported with version 1.5.2 or later.
Figure 11. Sapphire D Software Directory Structure
/usr/dmd
/v1.2.3
/v1.3.0
/setup
/bin
/cal
/doc
/current
/3rd_party
/cal
/sample
/sys
/system
/include
/lib
/template
The contents of the /usr/dmd directory are:
/vx.x.x
One version of the software.
/current
Soft link that points to the current version of software.
/3rd_party
Contains third party software.
/cal
Contains system calibration files.
/setup
Contains scripts to setup user accounts.
/system/bin
Contains executable files, such as ite, oic, and syscon.
/system/cal
Soft link that points to the /usr/dmd/cal directory.
/system/doc
Contains documentation files.
/system/include
Contains header files (.h) that define C++ classes.
CscDmd.h must be included in all C++ source files.
/system/lib
Contains shared library files (.so).
/system/sample
Contains OIC source code and C++ examples of
generating a custom summary.
/system/sys
Contains text files, such as dmd.alias, NewLot.xml,
offline_cfg.txt, and user.makefile.
/system/template
Contains C++ examples of user_shmoo() and
user_command() functions.
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
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4 – Software Overview
Test Programming Environment
Figure 12. Diamond Series Software System
Source Files
C++
Source
Files
Program
Developer
C++
Compiler
Tester Files
STIL
Source
Files
Resource
Definiton
File
Signal Map
File
Job File
offline_cfg.txt
STIL
Compiler
Integrated Test
Environment
Shared
Object File
(.so)
Pattern
Object File
(. pat)
Runtime
Object File
(.rto)
Job Linker
Test Executive
Test System Hardware
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Test Programming Environment
Below is a description of each of the software components shown in Figure 12:
•
•
•
Source files:
–
C++ source file—ASCII file that uses standard C++ statements and API function
calls to define the operation and flow of device tests
–
STIL source file—ASCII file that contains signal, timing, level, and pattern
information
Tester files:
–
Resource definition file—ASCII file that maps resource names to instruments and
slots
–
Signal map file—ASCII file that maps DUT signal names to resource channels
–
Job file—ASCII file that defines the job elements
–
offline_cfg.txt—ASCII file that defines the offline hardware configuration
C++ compiler—Compiles C++ source files into shared object file:
–
•
Shared object file (.so)—Binary C++ file
STIL compiler—Compiles STIL source files into pattern and runtime object files:
–
Pattern object file (.pat)—Binary pattern data file
–
Runtime object file (.rto)—Binary file that contains signal, timing, and level
information
•
Job linker—Links the pattern and runtime object files into the job
•
Test executive—Links shared object files into the job and coordinates job load and
execution
•
Integrated Test Environment (ITE)—GUI that edits tester files, loads the job, and
executes the test flow
•
Program Developer—GUI based on SlickEdit® that edits ASCII files and debugs C++
source code
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
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4 – Software Overview
Integrated Test Environment
Figure 13. Integrated Test Environment GUI
Menus
Icons
Tabs
Work Area
File Manager
Test Executive
To start ITE, type ite& at the Linux prompt.
Right-click on a file to view the available actions as shown in Figure 13. Each file type has
a different set of actions, such as Edit and Edit in Program Developer.
The work area is divided into three main tabs:
•
Design—Views and edits the tester files.
•
Test—Provides controls to execute, datalog, and debug the test program.
•
Tools—Displays Shmoo and Margin Tool.
Additional tools, such as Pattern Tool and STIL Tool, are available through the Tools
menu.
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Integrated Test Environment
Program Developer
Figure 14. Program Developer
Program Developer can be opened in the following ways:
•
Type vs& at the Linux prompt.
•
Right-click on a file and select Edit in Program Developer from ITE.
•
Select Tester > Start Debug... from ITE.
The features of Program Developer are:
•
Source code debugger
•
Language-sensitive editor (STIL and C++)
•
Argument completion
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
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4 – Software Overview
Compiling and Linking
Figure 15. Build Dialog
Select Build > Build Tool from ITE to open the Build Dialog.
Select Generate Makefile to create a makefile from the selected job file. The makefile
defines the file dependencies for compiling. Generate Makefile must be run after initial job
creation and any time a change is made to the job file.
Select Make to run the makefile. Running make compiles the source files and links the
files together for the job.
Make invokes:
42
•
STIL compiler (dsc)—Compiles STIL source files.
•
Job linker—Links the compiled STIL object files, resource definition file, and signal
map file into the job.
•
C++ compiler (g++)—Compiles the C++ source files into a shared object library.
PN: 071-0961-00, January 2008
Integrated Test Environment
Analog Wavetool
The Analog Wavetool (AWT) is an integral part of developing and debugging mixed signal
test programs, as well as analysis of waveform data. It is really important to become
proficient in its use. This course demonstrates the AWT under a variety of circumstances.
A few of the AWT’s most common applications are:
•
Creating waveforms for use with AWGs
•
Verifying the correct use of the DSP Library in a test program through simulation of
the chosen algorithm
•
Online debug of mixed signal test through the viewing of a captured waveform and its
subsequent DSP processing
•
Offline debug and analysis of waveforms to extract useful information
Figure 16. Analog Wavetool
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
43
4 – Software Overview
Create Waveforms
The AWT can be used to create waveform files from sampling parameters.
Figure 17. Waveform Creation Dialog Box
Waveform
Types
Waveform
Parameters
Waveform
Preview
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Integrated Test Environment
The AWT display acts much like an oscilloscope or spectrum analyzer, as shown in
Figure 18.
Figure 18. AWT Waveform Display
The waveforms can be saved for use with various Credence AWGs.
Figure 19. AWT File Save Options
Credence AWAV
Format
Credence AWG
Format
Text Files
Parallel Vectors
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
45
4 – Software Overview
Algorithm Simulation
The AWT can be used to develop DSP algorithms offline. Every DSP Library function is
available through the buttons at the bottom of the screen.
For example, to capture a waveform, take the waveform’s FFT, and compare the
magnitude of bin 43 to that of another waveform. This process can be duplicated offline
using the AWT. This allows the corresponding DSP code to be written offline.
Figure 20. Algorithm Development Using AWT
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Integrated Test Environment
Online Debug and Analysis
The AWT can be used to view waveforms during online test debug. In this example
(Figure 21), the datalog offers little information about the nature of the failing test. Using
the AWT, it is obvious that the waveform is clipped.
Figure 21. Online Debug Using AWT
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
47
4 – Software Overview
Offline Debug and Analysis
Since waveforms can be saved in the .AWAV format without any loss of resolution,
analysis can be done offline in cases where test system time or availability is limited.
Figure 22 shows a typical baseband gain test signal. The data might be analyzed in either
the time or the frequency domain.
Figure 22. Offline Debug Using AWT
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Operator Interface Control Tool
Operator Interface Control Tool
The Operator Interface Control (OIC) is a job management user interface for production
test. This is the universal robot also known as CURI. It presents similar data, but in
another format.
Figure 23. Operator Interface Control
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
49
4 – Software Overview
DSP Library
The Credence DSP Library is a general purpose library of functions for performing Digital
Signal Processing on signals captured from a device or other sources of data. Originally
developed for the Vista/Duo/Quartet/Octet series of VLSI test systems, it has evolved into
a powerful cross-platform tool that works with all Credence mixed signal test systems,
including Sapphire and ASL products. As a result, it is mature, comprehensive, and
optimized for high throughput.
The DSP Library can run on dedicated DSP processors like the TI 32000 family, as well
as on various host computers such as PCs or SPARCs.
On the Diamond Series, the DSP library runs on the Linux host as a shared object (.so)
file. Functions fall into one of several broad categories:
•
Frequency domain measurement and utility functions
•
Time domain measurement and utility functions
•
Relational and statistical domain measurement functions
•
General DSP utility functions
The DSP library functions use the concept of a DspWaveform. A DspWaveform object
contains both waveform data (a set of magnitudes) and metadata (information about the
data such as number of samples or sampling rate).
Figure 24. DSP Library Use Model Block Diagram
Capture Memory
Dsp
Library
Functions
DspWaveform
The DSP Library is explored in more detail in the lab exercises.
For debugging DSP algorithms, waveforms captured during test programs, or for
designing input waveforms for device testing, the Diamond Series software includes the
Analog Wavetool (AWT). The AWT is a powerful cross-platform graphical tool. The AWT
is also used on other Credence test system platforms.
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DSP Library
Knowledge Check
1. What is the editor of choice for ASCII files?
2. What is the path to the current ITE version?
3. What are the three main purposes of AWT?
4. What formats are supported by AWT?
5. Can an algorithm be used offline?
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
51
4 – Software Overview
Lab Exercise
AWT Lab
This lab is a basic introduction to the usefulness of the AWT. This lab leads students
through the steps for creating waveforms and performing some basic operations.
1. Type awt & from a command prompt to start AWT. The & character runs the
command in background mode so that the command shell can continue to be used.
Alternately it can be started from ITE by selecting Tools > Analog WaveTool. The
AWT displays as shown in Figure 25.
Figure 25. AWT—Main Window
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DSP Library
2. Click on the File/New tab, or the small waveform icon. This opens the waveform
creation dialog box. There are several types of waveforms that can be created (sine,
pulse, sawtooth, and others) from this window.
3. Select sine (it is selected by default) to get the waveform parameters appropriate for
that type of waveform. Notice, in particular, the following settings:
Number of Cycles: 7
Number of Samples: 1024
Sample Interval: 10 ns
Waveform Amplitude: 1.0
These settings create a sine wave with seven cycles, using 1024 samples spaced
10 ns apart. The peak amplitude is 1.0 V.
4. Click OK. The waveform is created
Figure 26. AWT—Waveform Parameters
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
53
4 – Software Overview
5. The sine wave can now be seen. Drag the cursor down into the waveform pane to
track the waveform values or change the Points drop-down menu (see Figure 27)
User Units. The X-axis values change from sample number to nanoseconds (in 10 ns
intervals).
Figure 27. First Waveform Example
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DSP Library
6. Create a second waveform.
a. Open up the new waveform dialog box.
b. Make the following two changes to the default settings:
•
Number of Cycles: 14
•
Waveform Amplitude 0.1
7. Click OK to create the waveform
The waveform (as shown in Figure 28) has twice as many cycles and one-tenth the
amplitude of the other waveform
Figure 28. Second Waveform Example
8. Select the WF Arith/Add buttons at the bottom of AWT. This adds the two waveforms
together, point by point. Notice that the waveform has a slightly tilted character,
indicating that it contains some harmonic distortion.
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
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4 – Software Overview
9. Create another waveform.
a. Open the new waveform dialog box.
b. Select Gaussian Noise.
c. Change the Standard Deviation to 100 µV.
d. Click OK to create.
10. Click the WF Arith/Add button to add the new waveform to the existing one. The
waveform should be similar to the one shown in Figure 29.
Figure 29. Third Waveform Example
Notice that no noise is visible. This is because its magnitude is so small relative to the
waveform amplitude.
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DSP Library
11. Click the WF Trans/Spectrum button. This performs an FFT and some scaling so
that the waveform components can be viewed in the frequency domain.
Figure 30. FFT and Scaling
The AWT is used extensively to make DSP calculations and for waveform creation/
observation.
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
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4 – Software Overview
Simulate ADC DNL/INL Ramp Test
Use this procedure to simulate a ADC DNL/INL ramp test.
1. Create ramp 1024 samples, amplitude 1023 “New Waveform” (Simulates 10 bit ramp
0..1023).
2. Modify ramp to get 8 identical samples per code step.
3. Push a copy of the wave to stack.
“wf Math -> Interleave“ combines both waveforms takes alternating one sample from
each wave.
4. Push a copy to the stack and interleave.
5. Push a copy to the stack and interleave.
6. Create the “New Waveform” Noise signal with 8192 samples and 0.3 Standard
Deviation, Mean 0.0.
7. Add “wf Arith -> Add” Noise signal to ramp.
8. Push a copy to the stack.
9. Calculate INL/DNL from “wf Meas -> INL/DNL (ramp)” ramp.
•
Number of segments 1, 10 ADC bits, 1 ramp/segment
•
Ramp magnitude: 1023, Vref 1023.0, Starting offs 0.0
10. Evaluate results.
11. Select copy of interleaved/noisy waveform.
12. Calculate 10 bit “wf Math Histogram” histogram.
13. Compare DNL with histogram.
14. Calculate another 5 bit histogram from 10 bit histogram result.
15. How does this shape look like?
Check Your Work
Review the answers and have the instructor sign off this module.
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5
Defining Mixed Signal Resources and
Signals
Goal
Define Tester resources and create Signal and SignalGroups.
Objectives
After completing this unit, students should be able to:
•
Define tester resource in the resource definition file
•
Map signal to resource channel
•
Define Signal and SignalGroups in STIL
•
Be able to compile the project
In This Module
______
______
______
Instructor Presentation
Knowledge Check
Lab Exercise
15
5
40
Minutes
Minutes
Minutes
Resources
Diamond Series Online Help
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
59
5 – Defining Mixed Signal Resources and Signals
Defining Tester Resources
The resource definition assigns user-defined names to tester resources. This is done by
editing the tpTemplate.res file. This file is created by default the first time the user creates
an empty test program.
The sections inside the file are:
•
Resource—User defined name for the selected resource
•
Type—Resource type: DIBU, MULTI_WAVE, VIS16, DPS16, DD1096-16
•
Chassis—Chassis number, 0 for a Diamond 10 test system and (0..3) for a Diamond
40 test system
•
Slot—Slot number
Example resource definition file:
ResDef {
Resource "DPIN96_0" {
Type "DPIN96" Version 0;
Location {
Chassis 0;
Slot 0;
}
Resource "MULTIWAVE01_5" {
Type "MULTI_WAVE" Version 0;
Location {
Chassis 0;
Slot 5;
}
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Mapping Signals to Channel
Mapping Signals to Channel
The signal map assigns signal names to user-defined resources and channels for each
site. To do this edit the tpTemplate.res file. This file is created by default the first time the
user creates an empty test program.
The sections inside the file are the following :
•
SiteCount—Number of sites in use for this test program
•
Signal—User defined signal
•
Resource—User defined resource defined in the resource definition file
•
Channel—Channel number used for the signal (declared by site)
Example:
SigMap {
SiteCount = 2;
Signal "Gen1_site" {
S 0 { R "MULTIWAVE01_5;C 0 }
S 1 { R "MULTIWAVE01_5;C 4 }
}
}
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5 – Defining Mixed Signal Resources and Signals
Defining STIL Signals and SignalGroups
The STIL Signals block defines individual signal names and types. STIL signal names
must match the signal names declared in the signal map file. Only on signals block is
allowed per STIL file.
The syntax is:
Signals {
SignalName In|Out|InOut|Supply|Pseudo;
}
Example:
Signals {
trigger InOut;
Dig1_site Supply;
Gen1_site Supply;
}
Depending on the instrument, different types of signals are available. Table 3 lists the
summary for the different instruments and the associated signal types.
Table 3. instruments and Associated Signal Types
Instruments
Signal Types
MultiWave
Supply
VIS16
Supply
VIS2
Supply
DPS16
Supply
DIBU
Supply
DD1096-16
In/Out/InOut/Pseudo
The SignalGroups are declared the same way with the syntax below:
SignalGroups {
GroupName = ’sigref_expr’;
}
GroupName is the name of the SignalGroup. Sigref_exp is the list of signals or previously
defined SignalGroups that constitutes the signal group. Each name in the expression are
concatenated using the + sign.
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Defining STIL Signals and SignalGroups
Knowledge Check
1. What signal type can a MultiWave resource have?
2. What STIL statement creates a ALL_Dig signalGroup made of Dig1_site and
Dig2_site?
3. Which file extension contains the Resource Definition?
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
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5 – Defining Mixed Signal Resources and Signals
Lab Exercise
Defining Signals and SignalGroups Lab
This lab creates the resource definition, signal definition, signals.stil, timing.stil and
example.stil files necessary for the test development. Refer to Appendix B to see the
loadboard schematic.
With a dual site loadboard fitted and working with MultiWave, VIS16, and DIBU, the
MultiWave, VIS16, DD1096-16, and DIBU resources are necessary.
1. Launch ITE in the ./training_mxsl/lab directory
2. Edit the Resource Definition in training_mxsl.res file to map the following resources.
Table 4. Resource Definition
Resource
Type
Chassis
Slot
DPIN96_0
DD1096-16
0
0
MULTIWAVE01_5
MultiWave
0
5
VIS16_3
VIS16
0
3
DIBU_9
DIBU
0
9
3. Validate and save when done.
4. Edit the Signal Mapping in training_mxsl.sig to map the signals in Table 5.
Table 5. Signal Map (Sheet 1 of 2)
64
Signal
Resource
Site0
Site1
Gen1_site
MULTIWAVE01_5
0
4
Dig1_site
MULTIWAVE01_5
1
5
Gen2_site
MULTIWAVE01_5
2
6
Dig2_site
MULTIWAVE01_5
3
7
LT1121_IN
VIS16_3
3
14
LT1121_OUT
VIS16_3
4
15
Bypass_VI
DIBU_9
0
1
Bypass_Multi
DIBU_9
2
3
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Defining STIL Signals and SignalGroups
Table 5. Signal Map (Sheet 2 of 2)
Signal
Resource
Site0
Site1
DIBSENSE
DIBU_9
160
160
Relay5V
DIBU_9
130
130
Minus5V
DIBU_9
129
129
Plus5V
DIBU_9
128
128
trigger
DPIN96_0
12
12
5. Open a terminal.
6. Change to the tp directory.
7. Change to the patterns directory.
8. Create a file named signals.stil. This is where the Signals and the SignalGroups will
be defined.
9. Edit the signals.stil file and fill in this way:
a. Define the Gen1_site, Gen2_site, Dig1_site, Dig2_site, LT1121_IN, and
LT1121_OUT signals as Supply.
b. Define the Bypass_VI, Bypass_multi, Relay5V, Plus5V, Minus5V, and DIBSENSE
as Supply.
c. Define the trigger signal as InOut.
d. Add a SignalGroup ALL_Supplies containing ’Plus5V + Minus5V +
Relay5V’.
e. Add a SignalGroup ALL_ Relays containing ’Bypass_Multi + Bypass_VI’.
f.
Add a SignalGroup ALL_ Meas containing ’Dig1_site + Dig2_site’.
g. Add a SignalGroup ALL_ Src containing ’Gen1_site + Gen2_site’.
h. Add a SignalGroup ALL_ Multi containing ’ALL_Src + ALL_Meas’.
i.
Add a SignalGroup ALL_LT1121 containing ’LT1121_IN + LT1121_OUT’.
j.
Add a SignalGroup ALL_Dig containing ’trigger’.
k. Save all.
10. Create a file named timing.stil. This file is used to program the timing for the only
digital pingroup present for the ALL_dig test as shown:
Spec "frequency_spec" {
Category "frequency_cat" {
period_spec {Max ’100ns’; Typ ’50ns’; Min ’10ns’}
}
}
Selector "Min_freq_selector" {
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
65
5 – Defining Mixed Signal Resources and Signals
period_spec Min;
}
Selector "Typ_freq_selector" {
period_spec Typ;
}
Selector "Max_freq_selector" {
period_spec Max;
}
Timing "grossFuncTiming" {
WaveformTable "wftSimple" {
Period ’period_spec’;
Waveforms {
ALL_Dig {01 {’period_spec * 0.5’ D/U;}}
ALL_Dig {LHX { ’period_spec * 0.9’ L/H/X;}}
}
}
}
11. Create a file named levels.stil. This file is used to program the levels for the only
digital pingroup present for the ALL_dig test as shown:
Spec "level_spec" {
Category "level_cat" {
vdd_spec {Max ’6.0V’; Typ ’5.0V’; Min ’3.0V’}
}
}
Selector "Min_vdd_selector" {
vdd_spec Min;
}
Selector "Typ_vdd_selector" {
vdd_spec Typ;
}
Selector "Max_vdd_selector" {
vdd_spec Max;
}
DCLevels "grossLevels" {
All_Dig {
VIH ’vdd_spec-0.2’;
VIL ’0.2’;
VOL ’vdd_spec/2’;
VOH ’vdd_spec/2’;
}
}
12. Return to ITE.
13. Edit a Pattern example.stil inside the Program Developer:
a. Add an Include for signals/signalgroups as shown below:
Include signals.stil
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Defining STIL Signals and SignalGroups
b. Add an include for the Timing as shown below:
Include timing.stil
c. Add an include for the Level as shown below:
Include levels.stil
d. Add the patternBurst and patternExec.
e. Add these steps to the pattern:
PatternBurst "ExamplePatBurst" {
PatList {
"ExamplePat"
}
}
PatternExec "ExampleExec" {
Selector "Typ_freq_selector";
Category "frequency_cat";
Timing "grossFuncTiming";
Selector "Typ_vdd_selector";
Category "level_cat";
DCLevels "grossLevels";
PatternBurst "ExamplePatBurst";
}
Pattern ExamplePat {
W "wftSimple";
V { ALL_Dig = 0;}
V { ALL_Dig = 0;}
V { ALL_Dig = 0;}
V { ALL_Dig = 0;}
Loop 512 { V { ALL_Dig = 0;}
V { ALL_Dig = 1;}
V { ALL_Dig = 0;}
V { ALL_Dig = 1;}
}
V { ALL_Dig = 0;}
f.
Save the file.
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5 – Defining Mixed Signal Resources and Signals
14. Create the training_mxsl.job job file and add all relevant sections in Main tab.
Figure 31. Main Tab
Hint — The equations.stil pattern does not contain pattern info, but variables used as
globals inside the test program can be changed from STIL Tool utility (SpecBlock
section).
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Defining STIL Signals and SignalGroups
15. Set the STIL & APG tab as shown in Figure 32.
Figure 32. STIL & APG Tab
16. Set the Test Program tab as shown in Figure 33.
Figure 33. Test Program Tab
17. Create the makefile.
18. Compile the project.
19. Verify that the job will load.
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5 – Defining Mixed Signal Resources and Signals
Check Your Work
Review the work and have the instructor sign off this module.
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6
DIBU for Mixed Signal Tests
Goal
Develop and debug code for the DIBU instrument.
Objectives
After completing this unit, students should be able to:
•
Understand the capabilities of the DIBU instrument
•
Exercise the user power supplies and CBits
In This Module
______
______
______
Instructor Presentation
Knowledge Check
Lab Exercise
15
5
40
Minutes
Minutes
Minutes
Resources
Diamond Series Online Help
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71
6 – DIBU for Mixed Signal Tests
DIBU Hardware
The DIBU is an instrument used for several purposes:
•
Loadboard reference clocks are not accessible to the user.
•
Loadboard power supplies—Used to power an active filter to be inserted in the
MultiWave loopback lab. The +5 V relay also is used to insert/de-insert the filter.
•
Loadboard utilities—Use the CBits to switch the relays. This part is an open collector
so it has to be connected through the relay coil to the +5 V relay.
•
Loadboard busses—not available.
•
Power supplies for third party cPCI instruments—Provisioned for future extension or
third parties.
The DIB Utility instrument must reside in slot 9. The DIB resources are considered as
supply in the STIL signal definition.
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DIBU Hardware
Figure 34. DIB Instrument Block Diagram
cscTester->DIBU()->Signal()->
Backplane
Backplane
Interface
Interface
DIB Utility
cscTester ()->DIBU()->Signal ()->
cPCI Bus
cPCI Bus
Utility
Utility
Power
Power
Supplies
Supplies
Backplane
Interface
Backplane
and
Interface
Instrument
and
Control
Instrument
+5 V+5
@V3@A3 A
-5 V @
-5 V3@A3 A
+5 V
+5 Rly
V Rly@
@55 A
A
+12 +12
V@
2
A
V@ 2A
+24 +24
V@
2A
V@ 2A
Floating
Floating
CBIT CBIT
(64)(64)
CBIT
CBIT
Drivers
Drivers
IDPROM Bus
DUT
DUT
Interface
Interface
turnOnSupply()
turnOnSupply ()
turnOffSupply()
turnOffSupply
()
turnOnCBits()
turnOnCBits()
turnOffCBits()
turnOffCBits()
setCBits()
setCBits()
getCBits()
getCBits()
readCBits()
readCBits()
IDPROM Bus
I2C Bus2
Control
I C Bus
SPI Bus
I/O
I/O
Buffers
Buffers
SPI Bus
GPIO Bus
GPIO Bus
Scope TP Bus
Scope TP Bus
DIB Present#
DIB Present#
48 V System/
V System
3.3 V48cPCI
getDIBStatus()
getDIBStatus()
Power
cPCI
+5 V @ 10 A
cPCI
Backplane
+5 V @ 10 A
Backplane
Power
+12 V @ 2 A
Power
-12 V+12
@V2@A2 A Supplies
Supplies
-12 V @ 2 A
400 MHz Calibration Reference
Clock
400 MHz Calibration Reference Clock
10 MHz Reference Clock
10 MHz Reference Clock
CLK_DUT
CLK_DUT
Calibration Bus (6 wire)
CAL_FH,
Calibration
Bus CAL_SH,
(6 wire)GRD_H, CAL_FL, CAL_SL, GRD_L
DIB Ground
SenseGRD_H, CAL_FL, CAL_SL, GRD_L
CAL_FH,
CAL_SH,
connect()
disconnect()
connect()
disconnect()
DIB Ground Sense
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6 – DIBU for Mixed Signal Tests
Programming the DIBU
The cscTester->DIBU()->Signal()-> API selects the DIBU functions. This API accesses
the functions listed in Table 6.
Table 6. cscTester->DIBU()->Signal() Functions
API Function
Description
getDIBStatus ()
Returns the DIB status DIB_PRESENT or DIB_ABSENT
setCBits ()
Sets the CBIT (Utility Control Bits) value for the specified
signal or signal group
getCBits ()
Readback the CBIT status
readCBits ()
Readback the CBIT status
turnOnCBits ()
Turn on the CBIT
turnOffCBits ()
Turn off the CBIT
connect ()
Connect the CALBUS to the defined signal name or
signalGroup name
disconnect ()
Disconnect the CALBUS to the defined signal name or
signalGroup name
getConnectStatus ()
Readback the status of the calbus relay for a defined signal
turnOnSupply
Turns on supply on signal or signalGroup
turnOffSupply ()
Turns off supply on signal or signalGroup
getSupplyStatus ()
Reads back the supply status for a given signal
getChannelType ()
Reads back the channel type of a defined signal
CSCDIBStatus CSCDIBUPerSignalInterface::getDIBStatus
Returns DIB_PRESENT if the DIB sense line associated with the specified signal detects
the presence of a DIBU, otherwise DIB_ABSENT is returned.
If more than one DIBU is installed, a signal group may be used to check the status of
multiple DIBU DIB_PRESENT lines. In this case, DIB_PRESENT is returned if all the DIB
sense lines associated with the specified signal group detect the presence of a DIBU,
otherwise DIB_ABSENT is returned. If DIB_ABSENT is returned at least one of the DIB's
associated with the specified signal group is not present.
The channel associated with the specified signal must be assigned to the DIB_PRESENT
channel (Channel 160); otherwise, an error is returned.
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Programming the DIBU
setCBits(vector< unsigned long long > & cBitValue )
Sets the CBIT (Utility Control Bits) value for the specified signal or signal group. It is
similar to setCBits() in that respect, but this function takes a vector of unsigned long long,
which is used to pass in a value for more than 64 channels. The first element holds bit0 to
bit63, the second element holds bit64 to bit127 and so on.
setCBits ( const unsigned long long cBitValue )
Applies the specified value to the CBIT's (Utility Control Bits) for the specified signal or
signal group on the first active site. No mask can be applied, so subsequent calls to this
API override previous CBIT settings. This function can be used to control up to 64 CBIT
signals at once. Each signal is pulled up with a 69 kOhm resistors to P12V and grounded
with 18 kOhm resistors. Logic inversion occurs before the open collector driver, therefore,
setting the CBIT value to 0 corresponds to setting open collector output grounded, which
creates 0 V on the output. Setting the CBit value to 1 corresponds to a Hi-Z state of open
collector, which creates approximately 2.5 V at the output.
unsigned long long getCBits ( )
Reads back the CBIT (Utility Control Bits) values for the specified signal or signal group
on the first active site.
Note — If invoked for a signal that is not associated with CBIT channels, an error
exception is thrown.
unsigned long long getCBits ( std::vector< unsigned long
long > & cBitValue )
Reads back the CBIT (Utility Control Bits) values for the specified signal or signal group
on the first active site. It is similar to getCBits() but this function returns a vector of
unsigned long long, which is used to return the values of more than 64 signals. The first
64-bit element holds bits0 to bit63, the second element holds bit64 to bit127 and so on.
Note — The CBIT values for the first 64 signals are also returned by the function.
unsigned long long readCBits ( )
Reads back the CBIT (Utility Control Bits) values using the sense line of the CBIT driver
for the specified signal or signal group on the first active site. This output comes from a
comparator with a fixed threshold (around 1.65 V). Therefore, the value returned may be
different than that returned by getCBits(). When this function is used to monitor the state
of the CBIT as a relay driver, the utility supply P12V must be enabled to supply a pull up
voltage. If P12V is not enabled and there is no external circuitry that biases the line, the
readback will always return a 0. virtual unsigned long long getCBits ()=0
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
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6 – DIBU for Mixed Signal Tests
unsigned long long readCBits ( std::vector< unsigned long
long > & BitValue )
Reads back the CBIT (Utility Control Bits) values using the sense line of the CBIT driver
for the specified signal or signal group on the first active site. It is similar to readCBits(),
but this function returns a vector of unsigned long long, which is used to return the values
of more than 64 signals. The first 64-bit element holds bits0 to bit63, the second element
holds bit64 to bit127 and so on.
connect ( )
Connects the Calbus relays for the specified signal or signal group.
disconnect ( )
Disconnects the Calbus relays for the specified signal or signal group.
CSCConnectStatus getConnectStatus ()
Reads back the status of the Calbus relay for the specified signal or signal group on the
first active site. If a signal group is specified, the first signal element of the first active site
is used to get the status.
turnOnSupply ( CSCSupplyMode supplyMode )
Turns on (enables) the utility power supply for the specified signal or signal group. If
KEEP_ON mode is specified, the power supply is left on at EOT. In this case, turn the
power supply off in the user_unload() function.
turnOffSupply ()
Turns off (disables) the utility power supply for the specified signal or signal group.
CSCSupplyStatus getSupplyStatus ( )
Reads back the status of the utility power supply for the specified signal or signal group
on the first active site. If a signal group is specified, the first signal element of the first
active site is used to get the status.
CSCDIBUChannelType getChannelType ( )
Returns the DIBU channel type assigned to the specified signal or signal group on the
first active site. If a signal group is specified, the first signal element of the first active site
is used to get the status.
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Programming the DIBU
The different resources available in the DIBU are listed in Table 7.
Table 7. Resource Assignment on DIBU
Resource
Channel
CBIT_0 ... CBIT_63
0..63
P5V
128
N5V
129
R5V
130
P12V
131
P24V
132
DIBSENSE
160
CALBUS
176
GPIO_0 ... GPIO_7
192..199
IDPROM
224
I2C_0
225
SPI_0
240
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6 – DIBU for Mixed Signal Tests
Debugging DIBU
Visualize Tool is used to debug the setup of DIBU. The tool allows modification of
hardware while paused on a test.
Select Tools > Visualize from ITE to bring up Visualize Tool.
To begin:
1. Select Show > DIBU from Visualize Tool to display the DIBU Settings window.
Figure 35. Visualize Tool—DIBU Selection
2. Select the signals to be displayed.
3. Click Show to view them in Visualize Tool (see Figure 36).
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Debugging DIBU
Figure 36. Visualize Tool—DIBU
Visualize Tool displays the current hardware settings of DIBU hardware.
Individual values can be modified and applied to the test system hardware while paused
on a test. White cells can be modified; gray cells cannot.
To modify a hardware value and re-run the test:
1. Change the value of a cell and press Enter. The cell changes color to yellow to
indicate that the value has been modified, but the hardware has not been updated.
2. Click the Set button to update hardware. Green cells indicate that the hardware was
successfully changed. Red cells indicate the hardware was not successfully changed.
3. Click the Get button to read back the hardware values.
4. Select Retest from the Execution tab to re-run the test with the new hardware
settings. Continuing from the pause and re-running the program resets the hardware
values.
5. Select Show Members from the right-click menu to expand a pin group.
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
79
6 – DIBU for Mixed Signal Tests
Notes
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Debugging DIBU
Knowledge Check
1. How many CBITs are available on the DIBU?
2. Which C++ API returns the DIBU status?
3. List three resources available on the DIBU:
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
81
6 – DIBU for Mixed Signal Tests
Lab Exercise
DIBU Lab
This lab uses some of the API dedicated to DIBU to use the loadboard power supplies
and the CBITs to change relay state.
To complete the lab:
1. In Program Developer, open the mxsl_training.cpp file and uncomment the DIBU_lab
function in user_main.
2. Modify the cbit_delay and pwr_delay parameters inside the equations.stil file. This file
is located in the patterns directory. The parameters are to be defined in spec section.
Spec "dibu_spec" {
Category "dibu_cat" {
cbit_delay = ’3ms’;
pwr_delay = ’3ms’;
}
}
3. Write a piece of code to check the DIBU presence at the very beginning of the
DIBU_lab function.
4. Read the code that is exercising the relays and power supplies. Ask the instructor if
something remains unclear.
5. Write the code to switch off relays and power supplies, and check their final status.
6. Compile the job.
7. Load and validate on the hardware.
8. Pause on one of the tests and use Visualize to observe and change the hardware
state.
Check Your Work
Review the work and have the instructor sign off this module.
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7
MultiWave Instrument
Goal
Develop and debug code for the MultiWave instrument.
Objectives
After completing this unit, students should be able to:
•
Understand the capabilities of the MultiWave instrument
•
Execute loopback tests using the AWG and DIG parts
In This Module
______
______
______
Instructor Presentation
Knowledge Check
Lab Exercise
90
5
2
Minutes
Minutes
Hours
Resources
Diamond Series Online Help
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
83
7 – MultiWave Instrument
MultiWave Hardware
The MultiWave instrument is a multi-channel arbitrary waveform generator and digitizer
unit.
Four wide bandwidth generator channels and four wide bandwidth digitizer channels are
integrated into a single board. In addition to the converter path every I/O channel has a
separate high precision Kelvin PMU for parallel DC parametric tests. The MultiWave
instrument is designed for the Diamond Series test system and enables high performance
mixed signal tests from high precision audio to high-speed video applications. Sample
rates range from 0..250 MS/s with resolutions from 16-bit for video and up to 24-bit for
high precision audio tests. A flexible trigger routing with 10 trigger inputs and 10 trigger
outputs per instrument allows event synchronization to other system components, (digital
pattern).
Figure 37. MultiWave Block Diagram
Channel 7
DC / DC
Programmable
Ref Clock #1
CLK
Hi Speed
GigaSampler CLK
select
ADC
ADC
High
Gain/Filter/Control
AD Resolution
Amplifierselection
Gain/Filter/
AD
High-Speed
Hi Res
SRAM
Amplifier
ADC
PMU
DUT Interface
Trigger
MUX
Clock2
PMU
Gain/Filter/
Amplifier
Gain/Filter/
Amplifier
GigaSampler CLK
Gain/Filter/
AD
Amplifier
Gain/Filter/
AD
Amplifier
SRAM
DAC
PMU
Control
selection
CLK
Gain/Filter/
select
DA
Amplifier
Gain/Filter/
DA
Amplifier
PMU
GigaSampler CLK
Gain/Filter/
Amplifier
Gain/Filter/
Amplifier
84
DA
DA
PMU
ADC
GB
Filter
clock
selection
Filter
selection
GB
clock
Range
selection
High
AD Resolution
AD
High-Speed
Channel 1
SRAM
Input
mode
DIG ch2
DIG ch3
Input
MUX
DIG ch4
GigaBit Transiver Data
Channel 6
Filter
selection
GB
clock
Filter
selection
48 V
DIG ch1
PMU
SRAM
GB
clock
Hi Res
High
DAC
Resolution
High-Speed
+ Supply
Monitoring
Channel 3
Range GigaBit
Input
Transiver Trigger
selection
mode
High
Resolution
High-Speed
High
Resolution
Hi Speed
High-Speed
DAC
Channel 5
SRAM
Channel
FPGA
PMU
High
DA Resolution
DA
High-Speed
SRAM
Range
selection
Channel 2
Channel 0
GigaBit Transiver Data
Output
mode
PCI
Channel 4
Output
MUX
Trigger
AWG ch1
Range GigaBit
Output
Transiver Trigger
selection
mode
AWG ch2
Bus Interface
FPGA
AWG ch3
AWG ch4
SRAM
GB
clock
PMU
DAC
Channel
FPGA
Clock1
Gain/Filter/
Amplifier
Gain/Filter/
Amplifier
Channel
FPGA
Output MUX
Ref Clock
Generators
350 .. 400 MHz
SRAM
PMU
GigaBit Transiver Data
GigaBit Transiver Trigger
PN: 071-0961-00, January 2008
Arbitrary Waveform Generator
Arbitrary Waveform Generator
The four arbitrary waveform generator channels are designed to generate AC or DC
signals in a wide frequency range. Each generator path can be software configured as
high precision or high frequency signal path on-the-fly.
High Precision (Audio) Generator Path
Table 8. AWG High Precision (Audio) Generator Path Features (Sheet 1 of 3)
Feature
Specification
AWG Channels/Unit
4
DAC Resolution
24 bit
Min
Sampling Rate
Max Output Level Absolute
Differential
Typ
16 kS/s
Bandwidth AC
Note
Max
768 kS/s
Resolution: 0.01 Hz
500 kHz
-11.00 V
Output Impedance
+11.00 V
< 5 Ohm
Output Modes
Single Pos, Single
Neg, Differential
Amplitude Scaling
Realtime scaling
Kelvin Output
Force/Sense for
pos. and neg.
output
DC Output Accuracy
DC Baseline Positive/
Negative
Range
Resolution
Accuracy3)
±10.00 V
1.3 µV
±(0.1% + 800 µV)
±5.00 V
650 nV
±(0.1% + 800 µV)
±2.5 V
325 nV
±(0.1% + 800 µV)
±1.25 V
163 nV
±(0.1% + 800 µV)
±10.00 V
305 µV
±(0.1% + 800 µV)
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
85
7 – MultiWave Instrument
Table 8. AWG High Precision (Audio) Generator Path Features (Sheet 2 of 3)
Feature
Specification
Note
Common Mode Voltage
±10.00 V
Can be applied
from external node,
Total voltage not to
exceed ±11.0 V@
no load
Filter
Selectable LP Filter (-3 dB)
1.4 kHz
6 pole Butterworth
5.0 kHz
6 pole Butterworth
10 kHz
4 pole Butterworth
25 kHz
4 pole Butterworth
110 kHz
4 pole Butterworth
Bypass
AC Performance
Min
Typ
Max
Fsignal= 1kHz
fclk =384 kHz
LPF = 1.4 kHz
-1 dB FS
differential
THD
-110 dB
SFDR
110 dB
115 dB
SNR (0.1-25kHz)
103 dB
107 dB
Fsignal <25 kHz
fclk =384 kHz
LPF = 25 kHz
-1 dB FS
differential
THD
-100 dB
SFDR
110 dB
SNR (0.1-25 kHz)
103 dB
Fsignal <100 kHz
fclk =384 kHz
LPF = 110 kHz
-1 dB FS
differential
THD
-98 dB
SFDR
105 dB
86
-100 dB
PN: 071-0961-00, January 2008
Arbitrary Waveform Generator
Table 8. AWG High Precision (Audio) Generator Path Features (Sheet 3 of 3)
Feature
Specification
SNR (0.1-100 kHz)
Note
92 dB
Waveform Digitizer
The 4 waveform digitizer channels are designed to sample AC or DC signals in a wide
frequency range from high precision audio to high-speed video applications. Each
digitizer path can be software configured as high precision or high frequency signal path
on-the-fly.
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
87
7 – MultiWave Instrument
High Precision (Audio) Digitizer Path
Table 9. High Precision (Audio) Digitizer Path AWF Features (Sheet 1 of 2)
Feature
Specification
Digitizer Channels / Unit
4
ADC Resolution
24 bit
Min
Sampling Rate
differential
Typ
48 kS/s
Bandwidth AC
Max Input Level
Note
Max
2.5 MS/s
Resolution: 0.01 Hz
500 kHz
-11.00 V
Input Bias Current
+11.00 V
<1 µA
Input Modes
Single Pos, Single
Neg, Differential
Range
Resolution
Accuracy **
Input Voltage Range
(AC+DC)
±10.00 V
1.3 µV
±(0.1% + 800 µV)
Single Ended
±5.00 V
650 nV
±(0.1% + 800 µV)
±2.5 V
325 nV
±(0.1% + 800 µV)
±1.25 V
163 nV
±(0.1% + 800 µV)
Range
Resolution
Accuracy
Input Voltage Range
(AC+DC)
±20.00 Vpp
2.6 µV
±(0.1% + 800 µV)
Differential (Vpos-Vneg)
±10.00 Vpp
1.3 µV
±(0.1% + 800 µV)
±5.00 Vpp
650 nV
±(0.1% + 800 µV)
±2.50 Vpp
325 nV
±(0.1% + 800 µV)
low or high input
connected to GND
Input differential
connected
Filter
Selectable LP Filter
(-3 dB)
1 kHz Notch
-35 dB Attenuation
25 kHz
4 pole Butterworth
100 kHz
4 pole Butterworth
250 kHz
4 pole Butterworth
Bypass
88
PN: 071-0961-00, January 2008
Arbitrary Waveform Generator
Table 9. High Precision (Audio) Digitizer Path AWF Features (Sheet 2 of 2)
Feature
Specification
Note
AC Performance
Min
Typ
Max
Fsignal= 1kHz
Condition
ODR = 78 kHz
LPF = 25kHz
-1 dB
FS differential
THD
-98 dB
SFDR
115
SNR (0.1-25kHz)
106
- 95 dB
High Frequency (Video) Generator Path
Table 10. High Frequency (Video) Generator Path AWG Features (Sheet 1 of 2)
Feature
Specification
AWG Channels / Unit
4
DAC Resolution
16 bit
Min
Sampling Rate
0
Bandwidth AC
100 MHz
Slew Rate
Note
differential
Typ
Max
250 MS/s
120 MHz
Resolution: 0.01 Hz
±1 V range
750 V/µs
Max Output Level
Absolute
-3.4 V
Output Impedance
47 Ohm
+3.4 V
50 Ohm
no load
53 Ohm
Output Modes
Single Pos, Single
Neg, Differential
Amplitude Scaling
Realtime scaling
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
89
7 – MultiWave Instrument
Table 10. High Frequency (Video) Generator Path AWG Features (Sheet 2 of 2)
Feature
Specification
Note
Range
Resolution
Accuracy
±3.4 V (4.0 V)
128 µV
±(0.1% + 3 mV)
±4 V Range, Max
output level is
±3.4 V@ no load
± 2.0 V
64 µV
±(0.1% + 3 mV)
no load
± 1.0 V
32 µV
±(0.1% + 3 mV)
no load
± 0.5 V
16 µV
±(0.1% + 3 mV)
no load
DC Baseline Positive/
Negative
±3.4
153 µV
±(0.1% + 3 mV)
Common Mode Output
Voltage
±3.0 V
DC Output Accuracy
±(0.1% + 3 mV)
Can be applied
from external node,
Total output voltage
not to exceed
±3.4 V @ no load
Filter
Selectable LP Filter
(-3 dB)
1.2 MHz
5 pole Butterworth
12 MHz
5 pole Butterworth
50 MHz
5 pole Butterworth
Bypass
AC Performance
Min
Typ
Max
Fsignal= 1 MHz
fclk=100 MHz,
Load = 50 Ohm,
LPF= 1.2 MHz,
-1 dB FS
THD
-92 dB
SFDR
83 dB
90 dB
SNR (0.1-25 MHz)
78 dB
80 dB
90
Condition
-85 dB
PN: 071-0961-00, January 2008
Arbitrary Waveform Generator
High Frequency Video Digitizer Path
Table 11. High Frequency Video Digitizer Path AWG Features (Sheet 1 of 2)
Feature
Specification
Digitizer Channels / Unit
4
ADC Resolution
16 bit
Min
Notes
differential
Typ
Max
Sampling Rate
1 MS/s
130 MS/s
Bandwidth AC
100 MHz
Max Input Level Absolute
-3.5 V
Input Impedance
47 Ohm
50 Ohm
53 Ohm
Single ended
termination mode
94 Ohm
100 Ohm
106 Ohm
Differential
terminated mode
10 µA
15 µA bias
current
high impedance
mode
150 MHz
Resolution: 0.01 Hz
±3.3 V range
+3.5 V
Input Modes
Single Pos, Single
Neg, Differential
Range
Resolution
Accuracy
Input Voltage Range
(AC+DC)
±3.33 V
100 µV
±(0.5% + 10 mV)
Single Ended
±1.00 V
30 µV
±(0.5% + 5 mV)
±0.5 V
15 µV
±(0.5% + 3 mV)
Input Voltage Range
(AC+DC)
±6.66 V
200 µV
±(0.5% + 10 mV)
Input differential
connected/pos
Differential (Vpos-Vneg )
±2.00 V
60 µV
±(0.5% + 5 mV)
±1.00 V
30 µV
±(0.5% + 3 mV)
Differential (VposVneg ) range/2.0
and neg peak
voltage not to
exceed
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
Low or high input
connected to GND
91
7 – MultiWave Instrument
Table 11. High Frequency Video Digitizer Path AWG Features (Sheet 2 of 2)
Feature
Specification
Notes
Filter
Selectable LP Filter
(-3dB)
1.2 MHz
5 pole Butterworth
12 MHz
5 pole Butterworth
50 MHz
5 pole Butterworth
Bypass
Min
AC Performance
Typ
Max
Condition
Fsignal= 1 MHz
fclk= 100 MHz,
LPF = 1.2 MHz,
-1 dB
THD
-92 dB
SFDR
90 dB
SNR (0.1-25 MHz)
75 dB
FS differential
PMU Data
Table 12. PMU Data Features (Sheet 1 of 3)
Feature
Specifications
Notes
PMU Channels / Unit
8
Shared between
differential P and N
node
Kelvin Force/Sense
Connections
Mode
Range
Resolution
Accuracy
Voltage Force
-4.0 V .. +14.00 V
16 bit
±(0.1%+5 mV)
Current Force
±2.0 µA
16 bit
±(0.1%+10 nA)
± 20.0 µA
16 bit
±(0.1%+100 nA)
±200.0 µA
16 bit
±(0.1%+1 µA)
± 2.0 mA
16 bit
±(0.1%+10 µA)
± 25.0 mA
16 bit
±(0.1%+100 µA)
-4.0 V .. +14.00 V
16 bit
±(0.1%+5 mV)
Voltage Measurement
92
PN: 071-0961-00, January 2008
Arbitrary Waveform Generator
Table 12. PMU Data Features (Sheet 2 of 3)
Feature
Specifications
Notes
Current Measurement
±2.0 µA
16 bit
±(0.1%+10 nA)
± 20.0 µA
16 bit
±(0.1%+100 nA)
±200.0 µA
16 bit
±(0.1%+1 µA)
± 2.0 mA
16 bit
±(0.1%+10 µA)
± 25.0 mA
16 bit
±(0.1%+100 µA)
Protection Circuit
Over Voltage
±80 V
Maximum external
over voltage
Over Current
Protection
260 mA
limiting current
<1 ms
instrument
disconnection time
**
Memory Configuration
Organization
HF mode
LF mode
Note
AWG Memory/Channel
36 bit x 1 Meg
2 MSample
1 MSample
Memory shared
between HF and
LF mode
Capture Memory/
Channel
36 bit x 1 Meg
2 MSample
1 MSample
Memory shared
between HF and
LF mode
Triggering AWG/Digitizer
Trigger Sources
Trigger Conditions
Software
Trigger from software command
Backplane Event
Trigger
For example, trigger from digital
pattern or other tester hardware
DUT Board
Trigger
Trigger event from DUT board signal
Rising Edge
Falling Edge
Both Edges
Gate
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
93
7 – MultiWave Instrument
Table 12. PMU Data Features (Sheet 3 of 3)
Feature
Specifications
Trigger Modes
Single Step
Continuous
94
Notes
Single sample step on every trigger
(AWG and Capture)
Continuous
wave I/O
mode
PN: 071-0961-00, January 2008
MultiWave Resource Definition
MultiWave Resource Definition
In order to use MultiWave in a project, the instrument has to be listed in the resource
definition file of the project. The correct chassis and slot where the instrument resides in
the test system has to be entered and a resource name for the instrument has to be
assigned. There are two ways to do this use the ITE *.res editor or use the Program
Developer ASCII editor to write the resources with the defined format.
Example project.res File
RESDEF 1.00 { }
Header {
Title "Resource definition for Multiwave test";
Date "Fri Oct 27 10:55:51 CEST 2006";
}
ResDef {
Resource "MULTIWAVE01" {
Type "MULTI_WAVE" Version 0;
Location {
Chassis 0;
Slot 3;
}
//
Location
} // Resource
} // ResDef
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
95
7 – MultiWave Instrument
MultiWave Signal Mapping
Each MultiWave board contains 8 resources (C 0..7). The resources are mapped to the
physical channels as shown in Table 13.
Table 13. MultiWave Instrument
Resource in “.sig“ File
Physical MultiWave channel
C0
DAC Channel 0 (AWG)
C1
ADC Channel 0 (Digitizer)
C2
DAC Channel 1 (AWG)
C3
ADC Channel 1 (Digitizer)
C4
DAC Channel 2 (AWG)
C5
ADC Channel 2 (Digitizer)
C6
DAC Channel 3 (AWG)
C7
ADC Channel 3 (Digitizer)
Example project.sig File
SIGMAP 1.00 { }
Header {
Title "Signal mapping for Multiwave test";
Date "Mon May 8 14:52:45 CEST 2006";
}
SigMap {
SiteCount = 1;
// single mode
Signal "Gen_1" {
S 0 { R "MULTIWAVE01";
}
Signal "Dig_1" {
S 0 { R "MULTIWAVE01";
}
Signal "Gen_2" {
S 0 { R "MULTIWAVE01";
}
Signal "Dig_2" {
S 0 { R "MULTIWAVE01";
}
Signal "Gen_3" {
S 0 { R "MULTIWAVE01";
}
Signal "Dig_3" {
S 0 { R "MULTIWAVE01";
96
C
0; }
C
1; }
C
2; }
C
3; }
C
4; }
C
5; }
PN: 071-0961-00, January 2008
MultiWave Signal Mapping
}
Signal "Gen_4" {
S 0 { R "MULTIWAVE01"; C
}
Signal "Dig_4" {
S 0 { R "MULTIWAVE01"; C
}
} // SigMap
6; }
7; }
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
97
7 – MultiWave Instrument
MultiWave API
CSCMultiWaveDDSPerSignalInterface Class
Contains the basic DDS reference clock setup used to drive the on board PLL master
clocks.
Each MultiWave boards has two DDS channels and two PLL master clock units. Each
channel sample clock can be derived from the two PLL master clocks with independent
per channel clock dividers. The DDS frequency has a range of 350–385 MHz. The PLL
multiplies the DDS clock with a factor of 10 to 3.5-3.85 GHz, which forms the two master
clocks.
setRefFrequency(CSCClockSelection clock_e, double refFrequ)
Setup DDS frequency for master clock generation. Two DDS units are available per board
clock_e:
CLOCK_1, CLOCK_2
Master clock source
refFrequ:
350..385 MHz
DDS frequency -> x10 = PLL frequency
powerUpRefClock(CSCClockSelection clock_e, bool enable)
Power up of onboard DDS chip. Auto enabled during program load
clock_e:
CLOCK_1,CLOCK_2
Master clock source
enable:
true, false
Power up/down reference clock
enableRefClock(CSCClockSelection clock_e, bool enable)
Enable clock output of DDS. Auto enabled during program load
clock_e:
CLOCK_1,CLOCK_2
Master clock source
enable:
true, false
enable/disable reference clock
CSCMultiWaveClockPerSignalInterface Class
setClockDivider(CSCClockSelection clock_e, unsigned long divider)
Setup master clock divider for individual channels
clock_e:
CLOCK_1,CLOCK_2
Master clock source
divider:
1..(2^32-1)
per channel divider ratio
setClockEnable(bool enable)
Alternative sample clock setup programs all clock settings in one command:
enable:
98
true, false
Enable/disable divider output
PN: 071-0961-00, January 2008
MultiWave API
setClock(CSCClockSelection clock, double freq, unsigned long divider, bool
enable)
Enables and programs DDS frequency (PLL freq/10) and setup divider for sample clock
clock_e:
CLOCK_1,CLOCK_2
Master clock source
freq:
3.5 GHz .. 3.9 GHz
Master clock PLL frequency/10
Converter Sample Clock Range:
LF - AWG: 0 .. 25 MHZ (ICLK)
Output Data Rate ODR = ICLK / 32
LF - DIG: 1 MHz .. 20 MHz (ICLK)
Output Data Rate = ICLK / OSR
OSR (Over Sampling Ratio) see setLfOSRMode()
for more details
HF- AWG: 1 MHz .. 250 MHz
HF - DIG: 1 MHz .. 130 MHz
divider:
1..(2^32-1)
divider ratio to generate sample clock
enable:
true, false
enable/disable master clock
CSCMultiWaveOutputCtrlPerSignalInterface Class
Contains all functionality to control the generator path settings. Four high-speed and four
high precision generator paths are available per MultiWave board. The analog highspeed and high precision paths share the same DUT output lines and can be alternatively
selected in the test program upon demand.
apply (CSCMultiwaveRipples waveObject)
Apply a Waveformobject to generator.
waveObject:
pointer to a waveform object
setHfClock(bool enable)
enable:
true, false
enable/disable sample clock for HF Generator
setLfClock(bool enable)
enable:
true, false
enable/disable sample clock for LF Generator
CSCRunStatus status getAWGStatus()
status:
READY, BUSY
AWG is ready or busy
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
99
7 – MultiWave Instrument
setHfFilter(CSCFilterSelections filter)
Select a low pass filter for the high-speed generator path. The -3 dB attenuation point of
the filter is located at the frequencies listed below:
filter:
BYPASS
No Low Pass Filter
F_1P2_MHZ
1.2 MHz LP (5 pole Butterworth)
F_12_MHZ
12 MHz LP (5 pole Butterworth)
F_50_MHZ
50 MHz LP (5 pole Butterworth)
setLfFilter(CSCFilterSelections filter)
Select a low pass filter for the high precision, low frequency generator path. The -3dB
attenuation point of the filter is located at the frequencies listed below.
filter:
BYPASS
No LP Filter
F_1P4_KHZ
1.4 kHz LP (6 pole Butterworth)
F_5_KHZ
5 kHz LP (6 pole Butterworth)
F_10_KHZ
10 kHz LP (4 pole Butterworth)
F_25_KHZ
25 kHz LP (4 pole Butterworth)
F_110_KHZ
100 kHz LP (4 pole Butterworth)
setHfRange(double range)
Setup the high-speed generator range.
Note — Range refers to maximum amplitude to be generated without external load. With
a load of 50 Ohm for optimal line termination only half of the amplitude applies on the
generator output.
range:
x <= 0.5 V
±0.5 V range
(0.25 V @ 50 Ohm load)
0.5 < x <= 1 V
±1.0 V range
(0.5 V @ 50 Ohm load)
1 < x <= 2 V
±2.0 V range
(1 V @ 50 Ohm load)
x>2V
±3.4 V range
(1.7 V @ 50 Ohm load)
setHfBaseline(double pos, double neg )
alternative: setHfDcBase(double neg,double pos)
Setup DC baseline voltage for positive and negative high frequency generator output
terminal.
Note — Baseline voltage setting applies for open load.
100
pos:
±3.4 V
positive baseline
neg:
±3.4 V
negative baseline
PN: 071-0961-00, January 2008
MultiWave API
setLfRange(double range)
Setup the high precision, low frequency generator range.
range:
x <= 1.25
1.25 V input range
1.25 < x <= 2.5
2.50 V input range
2.5 < x <= 5.0
5.00 V input range
x > 5.0
10.00 V input range
setLfBaseline(double pos, double neg )
alternative: setLfDcBase(double neg,double pos)
Setup DC baseline voltage for positive and negative low frequency generator output
terminal.
pos:
-10.0 .. +10.0 V
positive baseline
neg:
-10.0 .. +10.0 V
negative baseline
start()
Start generator
stop()
Stop generator
CSCMultiWaveInputCtrlPerSignalInterface Class
Contains all functionality to control the digitizer input path settings. Four high-speed and
four high precision digitizer paths are available per MultiWave instrument. The analog
high-speed and high precision paths share the same DUT input lines and can be
alternatively selected in the test program upon demand.
powerUpLf(bool powerUp)
Enable/disable Low Frequency ADC. Auto powered up during program load.
powerUp:
true, false
resetLf()
Reset Lf Path.
setHfClock(bool enable)
enable:
true, false
Enable/disable sample clock for HF ADC
setLfClock(bool enable)
enable:
true, false
Enable/disable sample clock for LF ADC
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
101
7 – MultiWave Instrument
setLfOSRMode(unsigned long divider, CSCFilterTypeSettings mode)
Setup the AD-Converter operating mode. The converter core is build up as a SigmaDelta-Converter. The converter has a decimation unit and a built in FIR filter. The output
data rate (FODR) depends on the converter clock (FICLK) and the OverSampling Ratio
(OSR).
FICLK = FODR * OSR
The Passband Frequency depends on the OverSampling Ratio and one of the two FIR
filter settings.
Table 14 shows the possible settings and the achievable output data rates and baseband.
Table 14. Converter Settings
Decimation
Mode
Output Data Rate
Pass Band
Frequency
8
FULLY_FILTERED
0.125*ICLK
0.05*ICLK
16
FULLY_FILTERED
0.0625*ICLK
0.025*ICLK
32
FULLY_FILTERED
0.03125*ICLK
0.0125*ICLK
64
FULLY_FILTERED
0.015625*ICLK
0.00625*ICLK
128
FULLY_FILTERED
0.0078125*ICLK
0.003125*ICLK
256
FULLY_FILTERED
0.00390625*ICLK
0.0015625*ICLK
4
PARTIAL FILTERED
0.25*ICLK
0.0675*ICLK
8
PARTIAL FILTERED
0.125*ICLK
0.028125*ICLK
16
PARTIAL FILTERED
0.0625*ICLK
0.0140625*ICLK
32
PARTIAL FILTERED
0.03125*ICLK
0.00703125*ICLK
64
PARTIAL FILTERED
0.015625*ICLK
0.003515625*ICLK
128
PARTIAL FILTERED
0.0078125*ICLK
0.0017578125*ICLK
ICLK (converter clock derived from board master clock): 1 MHz .. 20 MHz
102
PN: 071-0961-00, January 2008
MultiWave API
setHfLowPassFilter(CSCFilterSelections filter)
Select a low pass filter for the high-speed digitizer path. The -3 dB attenuation point of the
filter is located at the frequencies listed below.
filter:
BYPASS
No LP Filter
F_1P2_MHZ
1.2 MHz LP (5 pole Butterworth)
F_12_MHZ
12 MHz LP (5 pole Butterworth)
F_50_MHZ
50 MHz LP (5 pole Butterworth)
setLfLowPassFilter(CSCFilterSelections filter)
Select a low pass filter for the high precision, low frequency digitizer path. The -3 dB
attenuation point of the filter is located at the frequencies listed below.
filter:
BYPASS
No LP Filter
NOTCH
1 kHz, 40 dB Notch filter
F_25_KHZ
25 kHz LP (4 pole Butterworth)
F_100_KHZ
100 kHz LP (4 pole Butterworth)
F_250_KHZ
250 kHz LP (4 pole Butterworth)
setHfRange(double range , CSCChannelConfiguration mode )
Setup the high frequency digitizer range.
range:
mode:
x <= 0.5
0.5 V input range
0.5 < x <= 1.0
1.0 V input range
x > 1.0
3.3 V input range
SINGLE_ENDED
x 1.0 scaling
DIFFERENTIAL
x 0.5 attenuator for correct scaling
setLfRange(double range, CSCChannelConfiguration mode)
Setup the high precision, low frequency digitizer range.
range:
mode:
x <= 1.25
1.25 V input range
1.25 < x <= 2.5
2.50 V input range
2.5 < x <= 5.0
5.00 V input range
x > 5.0
10.00 V input range
SINGLE_ENDED
x 1.0 scaling
DIFFERENTIAL
x 0.5 attenuator for correct scaling
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
103
7 – MultiWave Instrument
setHfInputTermination(CSCChannelConfiguration mode)
mode:
SINGLE_ENDED
Both P and N are terminated with 50 Ohm to ground
DIFFERENTIAL
P and N are terminated with 100 Ohm differential
setHfTermMinus(CSCDIGHighFreqTermination term)
term:
DIG_HF_TERMINATION_50
50 Ohm input impedance
DIG_HF_TERMINATION_500
High impedance input
setHfTermPlus(CSCDIGHighFreqTermination term)
term:
DIG_HF_TERMINATION_50
50 Ohm input impedance
DIG_HF_TERMINATION_500
High impedance input
start()
Start digitizing
stop()
Stop digitizing
CSCRunStatus status getStatus()
Readback actual digitizer status
status:
READY
Digitizer ready
BUSY
Digitizer is busy sampling data
bool waitForCaptureFinish ( double t)
This functions waits until the digitizer has finish running sample job. The command is
applied site by site inside a serial loop for multi site applications.
104
t:
Time in seconds for timeout (by default 5.0)
true
Digitizer(s) finished
false
Digitizer(s) did not finish in selected time
PN: 071-0961-00, January 2008
MultiWave API
CSCMultiWaveMemoryPerSignalInterface Class
Contains the memory management functions of the generator and digitizer paths.
createWaveform(CSCMultiWaveArbitraryWave *wave)
Allocate waveform in capture memory.
wave:
Pointer to waveform object to be allocated in capture memory
removeWaveform(CSCMultiWaveArbitraryWave *wave)
Free memory space in generator or capture memory.
wave:
Pointer to waveform object to be removed from generator or capture memory
loadWaveform(CSCMultiWaveArbitraryWave *wave)
Download data into generator memory from waveform object.
wave:
Pointer to waveform object
getWaveform(CSCMultiWaveArbitraryWave *wave)
Upload data from capture memory and store data in waveform object.
wave:
Pointer to waveform object
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
105
7 – MultiWave Instrument
CSCMultiWaveMuxPerSignalInterface Class
Contains the board resources connection commands of to the DUT connector.
connect(CSCLinkPath path, CSCMuxPath mode)
path:
SIGNAL_PATH_LF
Low frequency path
SIGNAL_PATH_HF
High frequency path
PMU_PATH
PMU path
GND_SENSE
Ground sense path
mode:
possible connections for SIGPATH_LF:
MUX_DIFFERENTIAL
Connect P and N terminals
MUX_SINGLE_P
Connect P terminal, N is grounded
MUX_SINGLE_N
Connect N terminal, P is grounded
MUX_VCM_SENSE_INTERN Common mode AWG voltage AGND or GND_S (see
GND_SENSE)
MUX_VCM_SENSE_EXTERN Common mode AWG voltage from DUT connector
MUX_KELVIN_P
Not verified yet / P and P_Sense in LF AWG mode
MUX_KELVIN_N
Not verified yet / N and N_Sense in LF AWG mode
MUX_KELVIN_DIFF
Not verified yet / F/S for P and N in LF AWG mode
MUX_DISCONNECT
Remove all connections
possible connections for SIGPATH_HF:
MUX_DIFFERENTIAL
Connect P and N terminals
MUX_SINGLE_P
Connect P terminal, N is grounded
MUX_SINGLE_N
Connect N terminal, P is grounded
MUX_VCM_SENSE_INTERN Common mode AWG voltage AGND or GND_S (see
GND_SENSE)
MUX_VCM_SENSE_EXTERN Common mode AWG voltage from DUT connector
MUX_DISCONNECT
Remove all connections
possible connections for PMUPATH:
106
MUX_KELVIN_P
PMU connected to P terminals with Kelvin F/S connection
MUX_KELVIN_N
PMU connected to N terminals with Kelvin F/S connection
MUX_SINGLE_P
PMU connected to P Force terminal, internal F/S link closed
PN: 071-0961-00, January 2008
MultiWave API
MUX_SINGLE_N
PMU connected to N Force terminal, internal F/S link closed
MUX_DISCONNECTRemove all connections
possible connections for GND_SENSE:
MUX_EXTERN
Channel ground referenced to Ch_GND_Sense on DUT
connector
MUX_INTERN
Channel ground referenced to AGND
MUX_DISCONNECTRemove all connections
CSCMultiWaveArmCtrlPerSignalInterface Class
Contains the arming of the generator and digitizer channels. The basic channel setup is
written to the hardware.
armAWG(CSCMultiWaveArbitraryWave *wave)
Prepare AWG setup: amplitude scaling, amplitude vs. range check, memory handling,
and fill internal data pipeline
wave:
Pointer to waveform object to be generated
The waveform object can be a type of arbitrary wave, sine or ramp wave.
armDIG(CSCMultiWaveArbitraryWave *wave)
Prepare digitizer setup: memory handling, sample length
wave:
Pointer to waveform object to be digitized.
CSCMultiWavePmuPerSignalInterface Class
Contains the setup and measurement functions for the per channel PMU functionality.
Each MultiWave board contains 8 PMU circuits. The PMU is shared between the positive
and negative channel inputs and outputs.
setForceMode(CSCForceMode mode)
Setup the PMU operation mode
mode:
VFVM
Force voltage and measure voltage
VFIM
Force voltage and measure current
IFVM
Force current and measure voltage
IFIM
Force current and measure current
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7 – MultiWave Instrument
setVForce(double voltage, double range)
Set PMU force voltage
voltage:
-4..+14 V
Force voltage setting
range:
-4..+14 V
Only 1 force range exists, use same value as force setting
setIForce(double current, double range)
Set PMU force current
current:
-25 mA..+25 mA
force current, not to exceed actual range setting
range:
x <= 2 µA
2 µA range
2 µA < x <= 20 µA
20 µA range
20 µA < x <= 200 µA 200 µA range
200 µA < x <= 2 mA
2 mA range
x > 2 mA
25 mA range
setMultiple(unsigned long count)
Set number of single measurements done on each PMU trigger. The measurement result
is the average value over all single measurements. The internal PMU sample rate is
100 kHz.
count:
0..2^16
setVClampPositive(double clamp)
Set positive voltage clamp. Notice: Negative value not to exceed positive clamp value.
clamp:
-5..+15 V
setVClampNegative(double clamp)
Set negative voltage clamp. Notice: Negative value not to exceed positive clamp value.
clamp:
-5..+15 V
linkFS(bool linkIt)
linkIt
true, false
close, open internal PMU Force/Sense link
turnOn()
Enable PMU circuit
turnOff()
Disable PMU circuit
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MultiWave API
trigger()
Start PMU measurement
double getMeasValueV()
return voltage measurement value
double getMeasValueI()
return current measurement value
setVMeasRange(double range)
alternative: setExpectedVoltage(double range)
Set voltage measurement range.
range:
0 <= x <= 10
0..+10 V measurement range
x < 0, x > 10
-4..+14 V measurement range
setIMeasRange(double range)
alternative: setExpectedCurrent(double range)
Set current measurement range
range:
x <= 2 µA
2 µA range
2 µA < x <= 20 µA
20 µA range
20 µA < x <= 200 µA
200 µA range
200 µA < x <= 2 mA
2 mA range
x > 2 mA
25 mA range
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
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7 – MultiWave Instrument
MultiWave Trigger Modes
The Trigger Modes are based on the resource. The methods listed below apply the same
way to Output and Input. They are part of CSCMultiWaveOutputCtrlPerSignalInterface
and CSCMultiWaveInputCtrlPerSignalInterface. Since they share the same events they
are grouped in this section.
They are mostly used with the eventRouting to create a coherent triggering method.
forceEvent (CSCTriggerForceEvent event)
Force an event through software command.
event:
FE_STEP_TRIGGER, FE_RAMP_UPC, FE_RAMP_DOWN, FE_START
selectStartInput(CSCtriggerQualification triggerQualification)
Setup Generator start source. The start source can be either controlled from SOFTWARE
through the command forceEvent() from a back plane event or through the DUT interface
trigger line.
triggerQualification:
TQ_SOFTWARE(default), TQ_GATE_LB, TQ_GATE_BP,
TQ_GATE_INVERTED_LB, TQ_GATE_INVERTED_BP,
TQ_RISING_EDGE_LB, TQ_RISING_EDGE_BP,
TQ_FALLING_EDGE_LB, TQ_FALLING_EDGE_BP,
TQ_ANY_EDGE_LB, TQ_ANY_EDGE_BP
selectStepTrigger(CSCtriggerQualification triggerQualification)
Setup the control signal for the single trigger mode. A single sample is generated or
digitized when a trigger occurs. The trigger source can be either from SOFTWARE, from
the backplane trigger line, or from the DUT interface trigger line. The TQ_DISABLE
mode, which is the default value, switches back to normal generator/sample mode.
triggerQualification:
110
TQ_SOFTWARE generates trigger for next generator sample
with software command forceEvent(FE_STEP_TRIGGER),
TQ_RISING_EDGE_LB, TQ_RISING_EDGE_BP,
TQ_FALLING_EDGE_LB, TQ_FALLING_EDGE_BP,
TQ_ANY_EDGE_LB, TQ_ANY_EDGE_BP, TQ_DISABLE
(default)
PN: 071-0961-00, January 2008
MultiWave API
AWG single step trigger by software control example:
//prepare Multiwave awg to be triggered in step by software
cscTester->MultiWave()->Signal("myAWGChannel")
->selectStepTrigger(TQ_SOFTWARE);
//arm awg
cscTester->MultiWave()->Signal("myAWGChannel")->armAWG(&awgWave);
// start AWG
cscTester->MultiWave()->Signal("myAWGChannel")->start();
//make 10 steps by sw trigger
for (i=0;i<10;i++){
CSCUtil::wait ( 1 ms );
cscTester->MultiWave()->Signal("myAWGChannel")
->forceEvent(FE_STEP_TRIGGER);
}...
// stop AWG
cscTester->MultiWave()->Signal("myAWGChannel")->stop();
AWG hardware trigger example:
// start AWG on trigger condition on rising edge of loadboard line event
cscTester->MultiWave()->Signal("myAWGChannel")
->selectStartInput(TQ_RISING_EDGE_LB);
cscTester->MultiWave()->Signal("myAWGChannel")
->armAWG(&awgWave);
... // wait for the hardware trigger line
// stop AWG
cscTester->MultiWave()->Signal("myAWGChannel")->stop();
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
111
7 – MultiWave Instrument
Definition of Waveform Object
CSCMultiWaveArbitraryWave
This object is used to generate and digitize arbitrary waveforms. Random data can be
downloaded to the per channel generator memory. Also captured data from the digitizer
memory is uploaded using the arbitrary waveform object.
setDspWaveform (DspWaveform *wave)
Set pointer to waveform data.
wave:
Pointer to waveform data
setPath (CSCSignalPath path)
Select the generator or digitizer signal path. This is necessary due to the different data
format in the memory for data up and download.
path:
LOW_FREQUENCY , HIGH_FREQUENCY
setIncrement (unsigned long increment)
Set the number of ADC samples skipped during waveform recording.
For example, 1 store every sampled data, 4: store every 4th converter sample and skip
three samples
increment:
1..max nr of samples
Note — For arbitrary generator mode the increment must be set to 1. This means every
sample is generated.
void setAmplitude (double amplitude)
Setup the amplitude of the waveform to be generated. The amplitude must not exceed
the range setting of the generator.
amplitude:
0..range
void setLength (unsigned long length)
Setup the length of the sample array.
length:
1..1M
setLoop (double mode)
Setup the loop mode for waveform generation.
mode:
0..n
Number of waveform cycles to generate
0 (LOOP_FOREVER)
Endless waveform generation
For example, 1.3 generates 1.3 x the waveform
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MultiWave API
setOffset (unsigned long offset)
Set start position in the waveform data for generator mode.
offset:
0.. nr of samples
CSCMultiWaveSineWave
Each generator channel contains a sine wave table with a length of 1024 samples in the
onboard FPGA. This allows generation of sine waves without downloading data to the
onboard memory.
setPath (CSCSignalPath path)
Select the generator signal path. This is necessary due to the different data format of the
sine wave table.
path:
LOW_FREQUENCY , HIGH_FREQUENCY
setAmplitude (double)
Setup the amplitude of the waveform to be generated. The amplitude must not exceed
the range setting of the generator.
amplitude:
0..range
setIncrement (unsigned long increment)
Set the increment value of the data pointer of the sine waveform data. With the help of the
increment it is possible to generate different sine output frequencies without touching the
converter sample clock.
For example, increment of 3 triples the output frequency compared to increment 1. Only
every 3rd sample of the internal sine wave table gets generated.
increment:
1..1023
setLoop (double mode)
Setup the loop mode for waveform generation.
mode:
0..n
Number of waveform cycles to generate
0 (LOOP_FOREVER)endless waveform generation
For example 1.3 generates 1.3 x the waveform
setPhaseOffset (double phOffset)
Set the start position for sine waveform generation in the internal sine wave table.
double
phOffset:
0..2*PI
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
113
7 – MultiWave Instrument
CSCMultiWaveRampWave
This wave object is used to generate a triangle waveform on the generator output. This
signal can be used for threshold tests on DUT inputs. A special loop ramp mode will be
available soon.
setPath (CSCSignalPath path)
Select the generator or digitizer signal path. This is necessary due to the different data
format in the memory for data up and download.
path:
LOW_FREQUENCY , HIGH_FREQUENCY
setLoop (double mode)
Setup the loop mode for waveform generation.
mode:
0..n
Number of waveform cycles to generate
0 (LOOP_FOREVER)endless waveform generation
For example, 1.3 generates 1.3 x the waveform
setMax (double maxU)
Set maximum voltage of triangle.
setMin (double minU)
Set minimum voltage of triangle.
setSlewRatePositive (double pos)
Set slew rate of rising triangle slope.
pos:
-gen range … + gen range
V/converter update
Converter update can be sample clock or external trigger event.
setSlewRateNegative (double neg)
Set slew rate of falling triangle slope.
neg: -gen range … + gen range
V/converter update
Converter update can be sample clock or external trigger event.
setStartDirection (rampDirection_t direction)
Set ramp direction for start of triangle.
direction: DIRECTION_POSITIVE, DIRECTION_NEGATIVE
setStartOffset (double start)
Set start voltage level for triangle generation.
start:
114
-generator range..
+ generator range
PN: 071-0961-00, January 2008
Low Frequency AWG Programming Overview
Low Frequency AWG Programming Overview
Four identical LF DAC channels per MultiWave instrument.
Figure 38. Low Frequency AWG Programming
setLfFilter(lpfilter )
armAWG(&wave)
wave: DspWaveform *wave
loadWaveform(&wave)
wave: DspWaveform *wave
start()
stop()
Data
normalized to
-1.0 ..+1.0
24 bit
Output Data Rate:
ODR = ICLK/32
lpfilter:
F_1P4_KHZ, F_5_KHZ,
F_10_KHZ, F_25_KHZ,
F_110_KHZ, BYPASS
LF
DAC
X
NOTE:
Sum of LfBaseline, external V_COMM/
GND_S and LF_DAC voltage not to
exceed ±11.0 V at AWG output
setLfRange(range)
range:
1.25 V, 2.5 V, 5.0 V, 10.0 V
DAC_CHx_P_S
DAC_CHx_P
+
LP_Filter
Fsample = ICLK/32
connect(path, mode)
path:
SIGNAL_PATH_HF,
SIGNAL_PATH_LF
mode:
MUX_SINGLE_P,
MUX_SINGLE_N,
MUX_KELVIN_P,
DAC_CHx_N
MUX_KELVIN_N,
MUX_KELVIN_DIFF,
DAC_CHx_N_S
MUX_DIFFERENTIAL
MUX_DISCONNECT
Range
+
ICLK: 0..25 MHz
Divider
/N
Real Time Scaling:
waveObj.setAmplitude(ampl)
ampl: not to exeed range setting
max. +/-10.0 V
x10
DAC_CHx_VCOMM
DDS1
(CLK1)
setClock(clk, pllFreq, divider , enable )
clk:
pllFreq:
divider:
enable:
CLOCK_1, CLOCK_2
3.5 GHz .. 3.9 GHz
140..2^32
true, false
setLfBaseline(pos, neg)
pos,neg: -10.0 V .. +10.0 V
3.5 .. 4.0 GHz
DDS2
(CLK2)
350..400 MHz
LF DAC Connections
DAC_CHx_P_S
DAC_CHx_P
+
DAC_CHx_N
connect(path,mode)
path:
SIGNAL_PATH_LF
mode:
MUX_VCM_SENSE_EXTE
RN
MUX_VCM_SENSE_INTE
RN
connect(path,mode)
path:
GND_SENSE
mode:
MUX_INTERN
MUX_EXTERN
AGND
DAC_CHx_GND_S
AGND
DUT Interface
DAC_CHx_N_S
DAC_CHx_VCOMM
DAC_CHx_GND_S
A_GND
DAC_CHx
(x = 0,1,2,3)
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
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7 – MultiWave Instrument
Low Frequency Digitizer Programming Overview
Four identical LF ADC channels per MultiWave instrument.
Figure 39. Low Frequency Digitizer Programming
connect(path,mode)
path:
mode:
DUT Interface
setLfLowPassFilter(lpfilter)
SIGNAL_PATH_HF,
SIGNAL_PATH_LF
lpfilter :
NOTCH (1kHz,-40dB),
F_22_KHZ, F_100_KHZ,
F_250_KHZ, BYPASS
MUX_SINGLE_P,
MUX_SINGLE_N,
MUX_DIFFERENTIAL
MUX_DISCONNECT
armAcp(&wave)
wave: DspWaveform *wave
start()
stop()
ADC_CHx_P
x1
x 0.5
Range
getWaveform(&wave)
wave: DspWaveform *wave
LF
ADC
LP_Filter
Data
ADC_CHx_N
ICLK: 1 MHz..20 MHz
AGND
ADC_CHx_GND_S
AGND
connect(path,mode)
path:
GND_SENSE
mode:
MUX_INTERN
MUX_EXTERN
setLfRange(range, mode)
range:
1.25 V, 2.5 V, 5 V, 10 V
mode:
SINGLE_ENDED (x1), DIFFERENTIAL (x0.5)
4
8
16
32
64
128
mode:
FULLY_FILTERED
FULLY_FILTERED
FULLY_FILTERED
FULLY_FILTERED
FULLY_FILTERED
FULLY_FILTERED
Outp Data Rate:
0.125*ICLK
0.0625*ICLK
0.03125*ICLK
0.015625*ICLK
0.0078125*ICLK
0.00390625*ICLK
Pass Band Frequ:
0.05*ICLK
0.025*ICLK
0.0125*ICLK
0.00625*ICLK
0.003125*ICLK
0.0015625*ICLK
PART_FILTERED
PART_FILTERED
PART_FILTERED
PART_FILTERED
PART_FILTERED
PART_FILTERED
0.25*ICLK
0.125*ICLK
0.0625*ICLK
0.03125*ICLK
0.015625*ICLK
0.0078125*ICLK
0.0675*ICLK
0.028125*ICLK
0.0140625*ICLK
0.00703125*ICLK
0.003515625*ICLK
0.0017578125*ICLK
setClock(clk, pllFreq, divider , enable )
/N
x10
setLfOSRMode(decimation, mode )
decimation:
8
16
32
64
128
256
Divider
DDS1
(CLK1)
3.5 .. 3.9 GHz
clk:
pllFreq:
divider :
enable:
CLOCK_1, CLOCK_2
3.5 GHz .. 3.9 GHz
175..2^32
true, false
DDS2
(CLK2)
350..390 MHz
Digitizer Connections
ADC_CHx_P_S
Differential
Single_N
Single_P
ADC_CHx_P .
ADC_CHx_N .
ADC_CHx_N_S
ICLK: 1 MHz ..20 MHz
ADC_CHx_GND_S
A_GND
ADC_CHx
116
(x = 0,1,2,3)
PN: 071-0961-00, January 2008
High Frequency AWG Programming Overview
High Frequency AWG Programming Overview
Four identical HF DAC channels per MultiWave instrument.
Figure 40. High Frequency AWG Programming
setHfFilter(lpfilter )
armAWG(&wave)
wave: DspWaveform *wave
loadWaveform(&wave)
wave: DspWaveform *wave
lpfilter :
F_1P2_MHZ, F_12_MHZ,
F_50_MHZ, BYPASS
start()
stop()
NOTE:
Sum of HfBaseline, external V_COMM/
GND_S and HF_DAC voltage not to
exceed ±3.4 V at HF AWG output
setHfRange(range)
range:
0.5 V, 1.0 V, 2.0 V, 3.4 V
50R
DAC_CHx_P
Data
normalized to
-1.0 ..+1.0
16 bit
+
X
HF-DAC
connect(path,mode)
path:
SIGNAL_PATH_HF,
SIGNAL_PATH_LF
mode:
MUX_SINGLE_P,
MUX_SINGLE_N,
DAC_CHx_N
MUX_DIFFERENTIAL
MUX_DISCONNECT
Range
LP_Filter
+
50R
1 MHz..250 MHz
Divider
Real Time Scaling:
waveObj.setAmplitude(ampl)
ampl: not to exeed range setting
max. ±3.4 V
setHfBaseline(pos, neg)
pos,neg: -3.5 V .. +3.4 V
/N
x10
DDS1
(CLK1)
3.5 .. 3.9 GHz
DAC_CHx_VCOMM
connect(path,mode)
path:
SIGNAL_PATH_HF
mode:
MUX_VCM_SENSE_EXTERN
MUX_VCM_SENSE_INTERN
DDS2
(CLK2)
350..390 MHz
connect(path,mode)
path:
GND_SENSE
mode:
MUX_INTERN
MUX_EXTERN
setClock(clk, pllFreq, divider, enable )
clk:
pllFreq:
divider:
enable:
CLOCK_1, CLOCK_2
3.5 GHz .. 3.9 GHz
14..2^32
true, false
AGND
DAC_CHx_GND_S
AGND
DUT Interface
HF DAC Connections
DAC_CHx_P .
+
DAC_CHx_N .
DAC_CHx_VCOMM
DAC_CHx_GND_S
A_GND
DAC_CHx
(x = 0,1,2,3)
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
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7 – MultiWave Instrument
High Frequency Digitizer Programming Overview
Four identical HF ADC channels per MultiWave instrument.
Figure 41. High Frequency Digitizer Programming
connect(path,mode)
path:
SIGNAL_PATH_HF,
SIGNAL_PATH_LF
mode:
DUT Interface
Note: Close this relay if operating
in MUX _SINGLE _N mode
MUX_SINGLE_P,
MUX_SINGLE_N,
MUX_DIFFERENTIAL
MUX_DISCONNECT
setHfTermPlus(term)
term:
DIG_HF_TERMINATION_50,
DIG_HF_TERMINATION_500
setHfLowPassFilter(lpfilter)
lpfilter :
F_1P2_MHZ, F_12_MHZ,
F_50_MHZ, BYPASS
armAcp(&wave)
wave: DspWaveform *wave
ADC_CHx_P
getWaveform(&wave)
wave: DspWaveform *wave
start()
stop()
50R
x1
x 0.5
AGND
AGND
Range
Data
HF ADC
LP_Filter
50R
1..130 MHz
setHfRange(range, mode)
range:
0.5 V, 1.0 V, 3.0 V
mode:
SINGLE_ENDED (x1), DIFFERENTIAL (x0.5)
ADC_CHx_N
setHfInputTermination(mode)
setHfTermMinus(term)
mode: SINGLE_ENDED, DIFFERENTIAL term:
DIG_HF_TERMINATION_50,
DIG_HF_TERMINATION_500
Note: Close this relay if operating
in MUX _SINGLE _P mode
Divider
/N
x10
Digitizer Connections
ADC_CHx_P_S Differential
Single_N
3.5 .. 3.9 GHz
Single_P
DDS1
(CLK1)
ADC_CHx_P .
DDS2
(CLK2)
350..390 MHz
ADC_CHx_N .
setClock(clk , pllFreq, divider, enable )
ADC_CHx_N_S
clk:
pllFreq:
divider:
enable:
A_GND
CLOCK_1, CLOCK_2
3.5 GHz .. 3.9 GHz
26..3900
true, false
ADC_CHx_GND_S
ADC_CHx
118
(x = 0,1,2,3)
PN: 071-0961-00, January 2008
Precision Kelvin PMU Overview
Precision Kelvin PMU Overview
Eight PMU cores, four AWG channels, and four DIG channels per MultiWave instrument.
These are shared between the CHx_P and CHx_N nodes.
Figure 42. Precision Kelvin PMU
setForceMode(mode)
mode:
VFIM
force voltage, measure current
IFVM
force current, measure voltage
VFVM
force voltage, measure voltage
IFIM
force current, measure current
setVClampPositive (pClamp)
pClamp: -4.0 V .. +14.0 V
setVClampNegative(nClamp)
nClamp: -4.0 V .. +14.0 V
connect(path,mode)
path:
mode:
setVForce(voltage,range)
voltage,range: -4.0 V..+14.0 V
setIForce(current,range)
current,range:
-2.0..+2.0 uA
-20.0..+20.0 uA
-200.0..+200.0 uA
-2.0..+2.0 mA
-25.0..+25.0 mA
turnOn()
turnOff()
muxed
ADC_CHx_P_S
DAC_CHx_P_S
ADC_CHx_P .
DAC_CHx_P .
ADC_CHx_N .
DAC_CHx_N .
ADC_CHx_N_S
DAC_CHx_N_S
F
F
S
S
F
F
S
S
DAC_CHx_VCOM
ADC_CHx_GND_S
DAC_CHx_GND_S
A_GND
A_GND
ADC_CHx
muxed
8 x PMU P/N muxed
(x = 0,1,2,3)
DAC_CHx
LO_SENSE
ADC/DAC_CHx_P
Force
ADC/DAC_CHx_P_Sense
linkFS(mode)
mode: true,false
ENABLE
F
S
S
F
F
ADC/DAC_CHx_N
HI_SENSE
ADC/DAC_CHx_N_Sense
measV = getMeasValueV();
measI = getMeasValueI();
ADC
trigger()
F
PMU_PATH
MUX_SINGLE_P
MUX_SINGLE_N
MUX_KELVIN_P
MUX_KELVIN_N
MUX_DISCONNECT
S
S
(x = 0,1,2,3)
setMultiple(noOfMeas)
noOfMeas: 0..2^16
setVMeasRange(vRange)
vRange:
0.0 V .. +10.0 V
-4.0 V .. +14.0 V
setIMeasRange(iRange)
iRange:
-2.0..+2.0 uA
-20.0..+20.0 uA
-200.0..+200.0 uA
-2.0..+2.0 mA
-25.0..+25.0 mA
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
AGND
ADC/
DAC_CHx_GND_Sense
connect(path,mode)
path:
mode:
AGND
GND_SENSE
MUX_INTERN
MUX_EXTERN
119
7 – MultiWave Instrument
Programming Clocks on MultiWave
Clock Setup for HF AWG and HF DIG Mode
The divider output is directly connected to the sample clock of the generator/digitizer.
The converter output data rate is equal to the divider output:
FDIV = FODR
The valid range for the divider/converter sample clock for the HF AWG is:
FDIV = FODR = 1 MHz .. 250 MHz
The valid range for the divider/converter clock for the HF DIG is:
FDIV = FODR = 1 MHz .. 130 MHz
Clock Setup for LF AWG
The AWG has a fixed sample clock to output a data rate ratio of 32. The divider output
clock is 32x higher than the final output data rate of the AWG channel. This is related to
the 32 bit word length of each AWG sample.
FDIV = FODR*32
The valid range for the converter bit clock FDIV (BCLK) for the LF AWG is:
FDIV = 0 .. 25 MHz
This leads to a LF AWG converter output sample rate of:
FODR = 0 .. 781.25 kHz
Clock Setup for LF DIG
The ADC of the LF DIG path is a sigma-delta converter design.
The effective output data rate and the pass band bandwidth can be user programmed to
optimize the analog performance. The user can choose between 7 different oversampling
ratios from 4 – 256 and 2 different predefined FIR filter settings.
The behavior of the LF ADC can be changed by the command:
setLfOSRMode( unsigned long osRatio, CSCFilterTypeSettings firSetting);
osRatio: 4,8,16,32,64,128,256
The effective output data rate is related to the set over sampling ratio:
FDIV = FODR * osRatio
Note — For a osRatio of 32 in LF DIG mode, the effective data rate is equal to the LF
AWG if the same divider clock is used for the AWG and ADC channel.
120
PN: 071-0961-00, January 2008
Programming Clocks on MultiWave
The valid range for the converter clock FDIV (ICLK) for the LF DIG is:
FDIV = FODR * osRatio = 1 MHz .. 20.0 MHz
Table 15. Choose OSR Based on Expected Effective Sampling Frequency
OSR
FIR Mode
Output Data
Sample Rate
Sample Rate Min
(ICLK = 1 MHz)
Sample Rate Max
(ICLK = 20 MHz)
8
FULLY_FILTERED
0.125 * ICLK
125 kHz
2.5 MHz
16
FULLY_FILTERED
0.0625 * ICLK
62.5 kHz
1.25 MHz
32
FULLY_FILTERED
0.03125 * ICLK
31.25 kHz
625 kHz
64
FULLY_FILTERED
0.015625 * ICLK
15.625 kHz
312.5 kHz
128
FULLY_FILTERED
0.0078125 * ICLK
7.8125 kHz
156.25 kHz
256
FULLY_FILTERED
0.00390625 * ICLK
3.90625 kHz
78.125 kHz
4
PART_FILTERED
0.25 * ICLK
250 kHz
5.0 MHz
8
PART_FILTERED
0.125 * ICLK
125 kHz
2.5 MHz
16
PART_FILTERED
0.0625 * ICLK
62.5 kHz
1.25 MHz
32
PART_FILTERED
0.03125 * ICLK
31.25 kHz
625 kHz
64
PART_FILTERED
0.015625 * ICLK
15.625 kHz
312.5 kHz
128
PART_FILTERED
0.0078125 * ICLK
7.8125 kHz
156.25 kHz
Setup LF AWG and LF DIG with effective data rate of 210 kHz example:
1. Setup DIG clock:
Pick LF ADC setting from Table 16 which covers the desired sample frequency of
210 kHz and a preferred sample rate higher than 10 MHz
Table 16. ADC Setup to Pick
osrRatio
FIR mode
Outp Data Rate
ODR Min
ODR Max
64
FULLY_FILTERED
0.015625 * ICLK
15.625 kHz
312.5 kHz
...->setLfOSRMode( 64, FULLY_FILTERED);
2. Calc FDIV (ICLK) for the chosen ADC setting (divider output clock):
FDIV = 210 kHz * 64 = 13.440 MHz
64 is the over sampling ratio for the chosen ADC mode above
3. Pick a PLL frequency which is in the valid PLL locking range of 3.5-3.9 GHz and
calculate the necessary divider ratio:
(double) divider = 3.8 GHz / 13.440 MHz = 282.73;
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7 – MultiWave Instrument
4. The divider has to be an integer number. Therefore pick the next integer number:
(long) ldivider = (long) divider;
5. Recalculate the PLL frequency with the rounded divider:
fpll= 13.440 MHz * (double) ldivider = 3.79008 GHz;
6. Setup the DIG clock setting with the derived values:
cscTester->MultiWave()->Signal(signal_dig)->Clock->setClock(CLOCK_1,
3,79008e9, 282, true);
7. Setup AWG clock for coherent sampling.
8. Calculate FDIV for a sample rate of 210 kHz:
FDIV = 210 kHz * 32 = 6.72 MHz
32 is the fixed ratio of bit clock to sample clock.
9. Choose the same PLL as used for the DIG channel and calculate the required divider
for the AWG channel:
dividerAWG = 3.790008/6.72 MHz = 564
10. Setup the AWG clock setting with the derived values:
cscTester->MultiWave()->Signal(signal_awg)->Clock->setClock(CLOCK_1,
3,79008e9, 564, true);
Debugging MultiWave Tests
Version 1.5.2 or earlier of visualize does not support MultiWave.
Currently, the only way to debug MultiWave is by mean of a scope and STILTool utility.
STILTool allows the user to modify parameters of instruments setup without recompiling.
It is recommended that tests have parameters located in a STIL file so they can be
modified during a debugging session.
AWT is the second entry point for debugging. The digitized waveform can be observed,
modified, and evaluated through algorithms available to the cpp program in the same
manner as AWT handles them. They share the same DSP library.
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Programming Clocks on MultiWave
Knowledge Check
1. How many resources (DIG and AWG) are available on a MultiWave?
2. What is the resolution of the AWG part in high resolution mode?
3. What is the sampling frequency range in AWG high frequency mode?
4. What is the purpose of the PMU?
5. Is the PMU shared among N and P on a differential pin?
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7 – MultiWave Instrument
Lab Exercise
MultiWave Loopback Lab
This lab creates two kind of loopback tests, high frequency and low frequency.
To complete this lab the student must be able to create a generic function to program the
loopback. The source is the onboard sinewave.
1. Open ITE and load the training_mxsl.job file.
2. Use the patterns/equations.stil file variable to get specs for the 1 MHz sinewave and
1 kHz waveform to be created.
3. Create two tests named HF_loopback_multiwave and LF_loopback_multiwave with
the predefined functions listed below. Use the direct loopback connections available
from the loadboard from Gen2_site to Dig2_site on Single N MUX. Refer to the
loadboard schematic in Appendix B, "Loadboard Schematic Extracts," on page 287.
The functions have been developed as macros so the user does not need to write all
APIs. In the section below the digitizer is referred as digCh and the AWG is referred
as genCh.
a. Clock setup for AWG and Digitizer:
•
setupAwgClock(genCh,CLOCK_1,fpll,divider,SIGNAL_PATH_HF)
•
setupDigClock(digCh,CLOCK_1,fpll,divider,SIGNAL_PATH_HF) (choose LF
for 1 KHz and HF for 1 MHz)
b. MUXing connection for AWG and Digitizer:
•
AwgDigConnect(genCh,SIGNAL_PATH_HF,MUX_SINGLE_N)
•
AwgDigConnect(digCh,SIGNAL_PATH_HF,MUX_SINGLE_N)
c. Memory preparation for AWG (loading data) and Digitizer (allocate memory for
capture):
•
CSCMultiWaveSineWave sinWave("hf_sine") - sinWave or rampWave or
arbWave
•
AwgSineWaveSetup(genCh,sinWave,HIGH_FREQUENCY,bin,LOOP_FOREVE
R,amplitude_src*2,0.0) (internal sinewave is used with increment equal to bin
from spec)
Hint — Choose the LOOP_FOREVER loop count to be able to observe the sinewave
with the scope when paused on the tests.
124
•
CSCMultiWaveArbitraryWave digWave("hf_capture")
•
DigWaveSetup(digCh,digWave,HIGH_FREQUENCY,1,capture_fft *2)
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Programming Clocks on MultiWave
d. Analog path setup for AWG and Digitizer:
•
AwgSetup(genCh,SIGNAL_PATH_HF,F_1P2_MHZ,amplitude_src*2,offset_src)
•
DigSetup(digCh,SIGNAL_PATH_HF,F_1P2_MHZ, range_meas,
SINGLE_ENDED, DIG_HF_TERMINATION_50,0,FULLY_FILTERED)
(FULLY_FILTERED is referring to the LF mode only and the
DIG_HF_TERMINATION is for HF mode only)
e. Start execution and stop on end of capture:
•
startAwg(genCh,sinWave)
•
startDig(digCh,digWave)
•
stopDigEOC(digCh,SIGNAL_PATH_HF,1.0) with a 1.0 second is the timeout
4. Upload captured data:
•
DigUpload(digCh,digWave)
5. DSP processing and test results
a. Test amplitude, snr, and thd with appropriate DSP function.
b. Save the data in an awav file to be read later with AWT.
int sitenum = *cscIter;
DspWaveform *acpDspWave = digWave.getDspWaveform();
char my_char[256];
sprintf(my_char,"./waves/hf_multiwave_loopback_site%d.awav",sitenum);
acpDspWave->writeAwavFile(my_char,true);
Hint — Steps 4, 5, and 6 have to be executed within a CSC_SERIAL_BLOCK_BEGIN/
END since this is running in multisite.
6. Release the MultiWave (stop clocks, disconnect output MUX and remove memory
segment allocated to capture):
•
stopAwg(genCh,SIGNAL_PATH_HF)
•
AwgDigConnect(genCh,SIGNAL_PATH_HF, MUX_DISCONNECT);
•
AwgDigConnect(digCh,SIGNAL_PATH_HF, MUX_DISCONNECT);
•
DigClean(digCh,digWave);
7. Insert the two tests for loopback
8. Compile, load, and run test program.
9. Check the waveforms with AWT (or a scope) and use STILTool to modify the test
parameters of frequency and amplitude.
10. Use Visualize tool to setup the filter in the loopback path and see the effect of the
active filter (calculated cutoff frequency 15.6 kHz).
a. Place a dummy test_var after the AWG has been started.
b. Open visualize on the site of interest when paused on this dummy test.
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
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7 – MultiWave Instrument
c. Set plus 5 V, Minus 5 V, and 5 V relay power supplies ON.
d. Set relay bypass_multi to 1 -> filter is bypassed.
e. Set relay bypass_multi to 1 -> filter is in the path.
f.
Compare the results with and without the filter.
Check Your Work
Review the work and have the instructor sign off this module.
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8
VIS16 Instrument
Goal
Develop and debug code for the VIS16 instrument.
Objectives
After completing this unit, students should be able to:
•
Understand the main capabilities of the VIS16
•
Execute loopback tests using the VIS16
In This Module
______
______
______
Instructor Presentation
Knowledge Check
Lab Exercise
1
5
90
Hour
Minutes
Minutes
Resources
Diamond Series Online Help
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8 – VIS16 Instrument
VIS16 Hardware
The VIS16 is a versatile instrument aimed at powering devices (forcing voltage) or testing
other special functions of a mixed signal device (typically current DACs or low dropout
regulators).
It can force current or voltages and has an additional path to generate voltage modulated
waveform. It has also the measure side or digitizer embedded making it a perfect
candidate for mixed signal application,
Figure 43 shows a block diagram of a single VIS16 voltage/current source.
Figure 43. VIS16 Block Diagram—Basic Operation
HI_S_KEL
FS-LINK
setCompensation()
COMP_VERY_SLOW
setVoltageSlewRate() COMP_SLOW
COMP_NORMAL
setVoltage() SLEW_NORM
COMP_VERY_FAST IRange
SLEW_SLOW
300 nA, 3 µA, 300 µA
VForce
3 mA, 30 mA,
setCurrent()
300 mA/100 mA
IPos
setCurrentBipolar()
INeg
FS-CLAMP
cscTester->VIS()->Signal()->
Kelvin
Detect
HI_F
HI_F_KEL GUARD
gateOn()
gateOff()
LO_F_KEL
128
I
FS-LINK
FS-CLAMP
measure()
measureBySite()
getMeasData()
getMeasDataBySite()
getMeasSampleData()
clearMeasSampleData()
setMeasDataAutoClear() setMeasFilter()
0, 5 kHz, 21 kHz
ADC
(16 bit)
LO_S_KEL
Kelvin
Detect
GND
setMeasDelay()
0 – 6.7 s
setMeasFrequency ()
1 Hz – 250 kHz
setMeasSampleCount ()
SAMPLE_AVERAGE 1 – 65536
SAMPLE_CAPTURE 1 – 4096
HI_S
LO_F
LO_S
connect()
disconnect()
close()
open()
V
VRange
2 V, 6 V, 20 V, 60 V
I
V
Diff
V
setMeasMode()
MEAS_CURRENT
MEAS_VOLTAGE
MEAS_DIFF_V
V (chan N+1)
setDiffVMeasRange()
20 mV, 200 mV, 2 V, 5 V
Note — One channel shown
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VIS16 Hardware
The VIS16 voltage/current source has 16 sources. Each source can force ±20 V @
±300 mA or ±60 V @ ±100 mA.
The VIS16 voltage/current source has the following features: triggers and timers, Time
Measurement Unit (TMU), modulation generator, and digitizer.
Figure 44 shows a block diagram of the VIS16 features. Figure 45 shows a detailed block
diagram of triggers and timers.
Figure 44. VIS16 Block Diagram—Features
cscTester->VIS()->Signal()->
Triggers
and Timers
Triggers
and Timers
VGate
OGateHi
VForce
HI_S
SlewRate
IPos
Compensation
Kelvin
Detect
IRange
INeg
GUARD
IGate
LO_F
Triggers
and Timers
Triggers
and Timers
Kelvin
Detect
GND
Modulation Generator
MGate
HI_F
OGateLo
Modulation
Generator:
- Sine
- Ramp
- Wave
I
V
Triggers
and Timers
VRange
loadWaveform()
setGeneratorWaveform()
cscTester->VIS()->createSineWave()
cscTester->VIS()->createRampWave()
cscTester->VIS()->createArbitraryWave()
Time Measurement Unit
cmp1
cmp2
cmp1
cmp2
Digitizer
Digitizer
Memory
1 k X 16
LO_S
I
ADC
(16 bit)
Control
V
Diff
V
Measure:
- Pulsewidth Internal &
- Frequency External
- Risetime Trigger Bus
- Falltime
cscTester->TMS()
V (chan N+1)
MeasFilter
Trigger at Measure
Trigger Edge:
- Positive
- Negative
- Any
cscTester->EventRouting()
Internal Trigger
Bus [15..0]
External Trigger
Bus [7..0]
setADCTriggerControl()
Note — One channel shown
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8 – VIS16 Instrument
Figure 45. Triggers and Timers Block Diagram
cscTester->EventRouting()->createRoute()
cscTester->EventRouting()->createRoute()->setSource()
cscTester->EventRouting()->createRoute()->addDestination()
cscTester->EventRouting()->apply()
cscTester->EventRouting()->clearRoutes()
External Trigger
Bus [7..0]
Internal Trigger
GATE_ON
Bus [15..0]
GATE_OFF
GATE_TIMER
Delay
trigger()
stopTimers()
Duration
setVGate()
setIGate()
setOGateHi()
setOGateLo()
setMGate()
setGenerator()
setVGateTimer()
setIGateTimer()
setOGateHiTimer()
setOGateLoTimer()
setMGateTimer()
setGeneratorTimer()
cscTester->VIS()->Signal()->
Table 17. VIS16 Specifications (Sheet 1 of 4)
Specification
Channels Per Instrument
16
Basic Voltage/Current Range
±60V
100 mA per channel, gangable to 200 mA
±20V
300 mA per channel, gangable to 600 mA
Force Voltage
Range
Resolution
Accuracy
±2 V
16 bit
±0.03% FSR
±6 V
16 bit
±0.03% FSR
±20 V
16 bit
±0.03% FSR
±60 V
16 bit
±0.03% FSR
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VIS16 Hardware
Table 17. VIS16 Specifications (Sheet 2 of 4)
Specification
Current Clamp
Range
Resolution
Accuracy
±300 nA
16 bit
±0.2% FSR +1 nA/V
±3 µA
16 bit
±0.05% FSR +1 nA/V
±300 µA
16 bit
±0.05% FSR
±3 mA
16 bit
±0.05% FSR
±30 mA
16 bit
±0.05% FSR
±300 mA (100 mA)
16 bit
±0.05% FSR
Range
Resolution
Accuracy
±2 V
16 bit
±0.03% FSR
±6 V
16 bit
±0.03% FSR
±20 V
16 bit
±0.03% FSR
±60 V
16 bit
±0.03% FSR
Range
Resolution
Accuracy
±300 nA
16 bit
±0.2% FSR +1 nA/V
±3 µA
16 bit
±0.05% FSR +1 nA1/V
±300 µA
16 bit
±0.05% FSR
±3 mA
16 bit
±0.05% FSR
±30 mA
16 bit
±0.05% FSR
±300 mA (100 mA)
16 bit
±0.05% FSR
Measure Voltage
Measure Current
Modulation/Generator (Per Channel)
SGT,CGT,MGT,OGT_HI/LO, Measurement Strobe
Range
DC .. 10 kHz
Resolution
16 bit
Waveforms
sine, triangle, Arbitrary
Waveform Memory
up to 8 k Samples
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8 – VIS16 Instrument
Table 17. VIS16 Specifications (Sheet 3 of 4)
Specification
Timer
6 Timers for Programmable Gates (Per Channel)
SGT,CGT,MGT,OGT_HI/LO, Measurement Strobe
Range
Resolution
100 ns ... 6.7 s
100 ns
Digitizer (Per Channel)
Capture Memory
up to 8 k Samples
Sample Frequency
100 k Samples/s
Resolution
16 bit
Time Measurement Per Channel
Range
Resolution
1 µs ... 65 ms
100 ns
65 ms ... 6.5 s
1 µs
Differential Voltage Measurement*
Range
Accuracy
20 mV
0.5% FSR
(Offset calibration procedure at operating voltage required on
application board.)
200 mV
0.1% FSR
2.00 V
0.1% FSR
5V
0.1% FSR
CMRR
70 dB
* Available between
CH0 ->CH1
CH8 ->CH9
CH2 ->CH3
CH10 ->CHl1
CH4 ->CH5
CH12 ->CHl3
CH6 ->CH7
CHI4 ->CH15
Comparator
Mode
Voltage / Current
Resolution
14 bit
Accuracy
0.5% FSR
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VIS16 Hardware
Table 17. VIS16 Specifications (Sheet 4 of 4)
Specification
Propagation Delay
Maximum 1.0 µs
Interface to Digital Synchronization Bus
VIS16 Resource Definition
In order to use VIS16 in a project, the instrument has to be listed in the resource definition
file of the project. The correct chassis and slot where the instrument resides in the test
system has to be entered and a resource name for the instrument has to be assigned.
There are two ways to do this use the ITE *.res editor or use Program Developer ASCII
editor to write the resources with the defined format.
Example project.res file:
RESDEF 1.00 { }
Header {
Title "Resource definition for VIS16";
Date "Mon Jun 25 06:49:34 PDT 2007";
}
ResDef {
Resource "VIS16_3" {
Type "VIS16" Version 0;
Location {
Chassis 0;
Slot 3;
}
//
Location
} // Resource
} // ResDef
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8 – VIS16 Instrument
VIS16 Signal Mapping
Each VIS16 board contains 16 resources (C 0..15). The resources are mapped to the
physical channels as shown in Table 18.
Table 18. VIS16 Board
Resource in .sig File
Physical VIS16 Channel
C0
VI0
C1
VI1
C2
VI2
C3
VI3
C4
VI4
C5
VI5
C6
VI6
C7
VI7
C8
VI8
C9
VI9
C 10
VI10
C 11
VI11
C 12
VI12
C 13
VI13
C 14
VI14
C 15
VI15
Example project.sig file:
SIGMAP 1.00 { }
Header {
Title "Signal mapping for VIS16 test";
Date "Mon May 8 14:52:45 CEST 2006";
}
SigMap {
SiteCount = 2;
Signal "LT1121_IN" {
S 0 { R "VIS16_3"; C 12; }
S 1 { R "VIS16_3"; C 14; }
} // Signal
Signal "LT1121_OUT" {
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VIS16 Signal Mapping
S 0 { R "VIS16_3"; C 13; }
S 1 { R "VIS16_3"; C 15; }
} // Signal
} // SigMap
Additional channels 16 – 23 are allocated to ganged channels (16 is equivalent to
channel 0 and 1 together). Ganged channels are only allowed by pair of even and
adjacent odd channels.
VIS16 API
The list presented below is aimed at showing the most used API. (It is not a complete list.)
For a complete set of available API refer to the software online help.
CSCVISInterface Class
Contains the API necessary to control all VIS16 related actions.
deleteAllWaveforms
Delete all waveform objects. Deletes all existing VISWaveforms.
deleteWaveform (const string &name)
Delete waveform object. Deletes the specified waveform if it exists. The waveform can be
of any type.
name:
Name of the waveform.
setRampMaxValue(const string &name, double value)
Sets up the maximum value for a given ramp waveform.
name:
Name of the ramp waveform.
value:
Maximum value for the ramp.
setRampMinValue(const string &name, double value)
Sets up the minimum value for a given ramp waveform.
name:
Name of the ramp waveform.
value:
Minimum value for the ramp.
setRampSlewRate(const string &name, double rate)
Sets up the slew rate value for a given ramp waveform.
name:
Name of the ramp waveform.
rate:
Slew rate for the ramp.
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8 – VIS16 Instrument
setSineFrequency(const string &name, double freq)
Sets up the frequency value for a given sinewave waveform.
name:
Name of the sine waveform.
freq:
Frequency for the sinewave.
setSinePhaseOffset(const string &name, double phase)
Sets up the phase offset value for a given sinewave waveform.
name:
Name of the sine waveform.
phase:
Phase for the sinewave.
setWaveformAmplitude(const string &name, double amp)
Sets up the amplitude valuefor a given sinewave or arbitrary waveform.
name:
Name of the waveform.
amp:
Amplitude for the waveform.
setWaveformData(const string &name, DspWaveform *wave)
Sets up the data for a given arbitrary waveform.
name:
Name of the waveform.
wave:
Data to be used for the given waveform name.
setWaveformRange(const string &name, double range)
Sets up the range to use for the given waveform.
name:
Name of the waveform.
range:
Range for the waveform.
setWaveformRepeat(const string &name, unsigned long count)
Sets up the repeat count to execute the waveform. 0 will repeat infinitely while any
number greater than 0 will repeat the waveform x times. This applies to arbitrary, ramp
and sinewave waveform.
name:
Name of the waveform.
count:
Amplitude for the waveform.
setWaveformSampleFrequency(const string &name, double frequency)
Sets up the sampling rate for the arbitrary waveform. Range for sampling frequency is
1 Hz - 250 kHz.
name:
Name of the waveform.
frequency: Sampling frequency.
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VIS16 Signal Mapping
setWaveformSingleStep(const string &name, bool single)
Sets up the single step mode. When enabled, the waves (sine, ramp or arbitrary) are
stepped by one sample every time it receives a trigger event. This trigger event has to be
generated through the EventRouting API.
name:
Name of the waveform.
single:
True, false.
setWaveformStartPos(const string &name, unsigned long pos)
Sets up the start position inside the waveform as a start point. This way several portions
of a single waveform could be used to make generate different waveforms.
name:
Name of the waveform.
pos:
Sample number where to start.
setWaveformStopPos(const string &name, unsigned long pos)
Sets up the stop position inside the waveform as a stop point. This way several portions
of a single waveform could be used to make generate different waveforms.
name:
Name of the waveform.
pos:
Sample number where to stop.
CSCVISPerSignalInterface Class
void clearMeasSampleData()
This function is used to remove all acquired samples to start with a memory filled with 0s.
open(const CSCVISConns connection)
This function is used to disconnect a specific portion of the VIS.
connection:
VIS_HI_FORCE,VIS_HI_SENSE,VIS_HI_GUARD,VIS_LO_FORCE,VIS_LO_SENSE,VI
S_BUS_FORCE,VIS_BUS_SENSE,VIS_DIFF_CHAN_SHORT,VIS_KELVIN_LINK,VIS_
KELVIN_CLAMP,VIS_MODULATION
close(const CSCVISConns connection)
This function is used to connect a specific portion of the VIS.
connection:
VIS_HI_FORCE,VIS_HI_SENSE,VIS_HI_GUARD,VIS_LO_FORCE,VIS_LO_SENSE,VI
S_BUS_FORCE,VIS_BUS_SENSE,VIS_DIFF_CHAN_SHORT,VIS_KELVIN_LINK,VIS_
KELVIN_CLAMP,VIS_MODULATION
connect()
This function makes the connection of force/sense and guard on high and low side of the
VIS.
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8 – VIS16 Instrument
disconnect()
This function makes the disconnection of force/sense and guard on high and low side of
the VIS.
doKelvinTest()
Check the connection to the DUT. This test only detects severe problems like broken
prober needles.
gateOff()
Turns off the source voltage gate and the clamp gate.
gateOn()
Turns on the source voltage gate and the clamp gate
loadWaveform(const string &wave)
Load arbitrary waveform data of given name to the selected channel.
Name:
Name of the waveform to be loaded.
double measure()
This function makes the measurement happen. It returns the result for the selected
channel. It can only be used in single site.
double measureBySite(const unsigned long siteNum)
This function makes the measurement by site in multisite context.
void resetAlarms()
This function resets the alarm status on the VIS16 instrument.
void setADCTriggerControl(CSCTimerTrigger triggerSource)
Defines trigger input used to start ADC measurement.
triggerSource: TIMER_SOFTWARE (default), TIMER_RISING, TIMER_FALLING,
TIMER_ANY
setCompensation(const CSCCompensationSetting compensation)
Sets up the compensation for the VIS16 channel.
compensation:
COMP_VERY_SLOW, COMP_SLOW, COMP_NORMAL,
COMP_FAST, COMP_VERY_FAST
setCurrent(const double current, const double range)
Programs the current clamp and range to apply to the channel.
138
current:
Value of current clamp expected.
range:
Range in which to apply the defined current.
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VIS16 Signal Mapping
setCurrentBipolar(const double currentPos, const double currentNeg, const
double range)
This function is used if we want to apply an assymetric current clamp on the given
channel.
currentPos:
Value of current clamp expected on the positive side.
currentNeg:
Value of current clamp expected on the positive side.
range:
Range in which to apply the defined current.
setDiffVMeasRange(const double range)
The VIS allows the differential measurements between two adjacent channels.
range:
20 mV, 200 mV, 2 V, 5 V
setGeneratorWaveform(const string &name)
This functions defines which already loaded waveform is used by the given channel.
name:
Waveform name.
setGenerator(const CSCGateControl gate)
This functions will connect the generator gate to the specified gate condition.
gate:
GATE_ON, GATE_OFF, GATE_TIMER.
setGeneratorTimer(const double delay, const double duration, const
CSCTimerTrigger triggerSource)
When using a gate timer, the timer has to be defined in terms of delay and duration.
delay:
delay between trigger and timer execution (0 to 6.7 s).
duration:
duration for the timer (0 to 6.7 s).
triggerSource:
TIMER_SOFTWARE, TIMER_EXTERNAL, TIMER_NOCHANGE.
setIGate(const CSCGateControl gate)
Sets the current gate state for the given channel or channel group.
gate:
GATE_ON, GATE_OFF, GATE_TIMER, GATE_NOCHANGE.
setMGate(const CSCGateControl gate)
Sets the modulation gate state for the given channel or channel group.
gate:
GATE_ON, GATE_OFF, GATE_TIMER.
setOGateHi(const CSCGateControl gate)
Sets the output gate high state for the given channel or channel group.
gate:
GATE_ON, GATE_OFF, GATE_TIMER, GATE_UNCHANGED.
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setOGateLo(const CSCGateControl gate)
Sets the output gate low state for the given channel or channel group.
gate:
GATE_ON, GATE_OFF, GATE_TIMER, GATE_UNCHANGED
setVGate(const CSCGateControl gate)
Sets the voltage gate state for the given channel or channel group.
gate:
GATE_ON, GATE_OFF, GATE_TIMER, GATE_UNCHANGED
setIGateTimer(const double delay, const double duration, const CSCTimerTrigger
triggerSource)
Sets the delay and duration of the current gate timer.
delay:
Delay between trigger and timer execution (0 to 6.7 s).
duration:
Duration for the timer (0 to 6.7 s).
triggerSource:
TIMER_SOFTWARE, TIMER_EXTERNAL.
setMGateTimer(const double delay, const double duration, const CSCTimerTrigger
triggerSource)
Sets the delay and duration of the modulation gate timer.
delay:
Delay between trigger and timer execution (0 to 6.7 s).
duration:
Duration for the timer (0 to 6.7 s).
triggerSource:
TIMER_SOFTWARE, TIMER_EXTERNAL, TIMER_NOCHANGE.
setOGateHiTimer(const double delay, const double duration, const
CSCTimerTrigger triggerSource)
Sets the delay and duration of the high output gate timer.
delay:
Delay between trigger and timer execution (0 to 6.7 s).
duration:
Duration for the timer (0 to 6.7 s).
triggerSource:
TIMER_SOFTWARE, TIMER_EXTERNAL, TIMER_NOCHANGE.
setOGateLoTimer(const double delay, const double duration, const
CSCTimerTrigger triggerSource)
Sets the delay and duration of the low output gate timer.
140
delay:
Delay between trigger and timer execution (0 to 6.7 s).
duration:
Duration for the timer (0 to 6.7 s).
triggerSource:
TIMER_SOFTWARE, TIMER_EXTERNAL, TIMER_NOCHANGE.
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VIS16 Signal Mapping
setVGateTimer(const double delay, const double duration, const CSCTimerTrigger
triggerSource)
Sets the delay and duration of the voltage gate timer.
delay:
Delay between trigger and timer execution (0 to 6.7s).
duration:
Duration for the timer (0 to 6.7 s).
triggerSource: TIMER_SOFTWARE, TIMER_EXTERNAL, TIMER_NOCHANGE.
setILimitHi(double current, double range)
Sets the current comparator high limit.
current:
Value
range:
Range
setVLimitHi(double voltage, double range)
Sets the voltage comparator high limit.
voltage:
Value
range:
Range
setLimitHi(const double limit)
Sets the limit high for a VIS test.
limit:
Limit high
setILimitLo(double current, double range)
Sets the current low comparator value.
current:
Value
range:
Range
setVLimitLo(double current, double range)
Sets the voltage low comparator value.
voltage:
Value
range:
Range
void setLimitLo(const double limit)
Sets the limit low for a VIS test.
limit:
Limit low
setMeasDataAutoClear(bool auto)
Controls if the measurement and sample counter are automatically reset after each
measurement.
auto:
True, False
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setMeasDelay(const double delayTime)
Sets the delay between the trigger to make the measurement and the time it occurs on
the hardware.
delayTime:
0 to 6.7 s
setMeasFilter(const double bandwidth)
Sets the measure filter bandwidth.
bandwidth:CONDITION VIS16_NO_FILTER (0 Hz), CONDITION VIS16_FAST_FILTER
(21 kHz), CONDITION VIS16_SLOW_FILTER (5 kHz)
setMeasFrequency(const double frequency)
Sampling frequency for the measurements.
frequency:
1 Hz to 250 kHz
setMeasMode(const CSCMeasMode mode)
Sets the measure mode for the given signal or SignalGroup.
mode:
MEAS_VOLTAGE, MEAS_CURRENT, MEAS_DIFF_V
setMeasPeriodic(const unsigned long periodic)
Sets the number of period to make the acquisition on.
periodic:
1 to 26
setMeasSampleCount(const unsigned long numberOfSamples, const
CSCSampleMode sampleMode)
Sets the parameters for sampling: number of samples and sampling mode.
numberOfSamples:
1 to 65536 in Average mode; 1 to 4096 in Capture mode.
sampleMode:
SAMPLE_AVERAGE, SAMPLE_CAPTURE
setMemoryConfiguration(unsigned long waveMem, unsigned long measMem,
unsigned long sampleMem, unsigned long tmuMem)
Advanced users can decide to split the allocated memory for waveform, measurement in
a different manner than the default. Blocks of 1k are allowed, 8k to share total per
channel.
waveMem:
Memory for generator waveforms.
measMem:
Memory for measurement results.
sampleMem: Sample Memory for measurement samples.
tmuMem:
Memory for TMU timer events.
setSupplyMode(CSCSupplyMode supplyMode)
Control if VIS is used as a supply that is kept on after eot().
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VIS16 Signal Mapping
setVoltage(const double voltage, const double range)
Writes the specified VIS force output DAC voltage value to the hardware for the specified
signal or signal group.
voltage:
Value
range:
Range
setVoltageSlewRate(const CSCSlewRateSetting slewRate)
Selects the slew rate of the source output signal. For stable operation at complex loads
(inductive or capacitive) the source provides the possibility of programming the slew rate
and settling time. This allows the program to avoid overshoot and oscillation on those
loads. The slew rate is controlled by a hardware switch, not by the software.
slewRate:
SLEW_FAST, SLEW_NORMAL, SLEW_SLOW
stopTimers()
Resets timers.
trigger()
Triggers the ADC conversion to start or triggers the timers to start if GATE_TIMER mode
is selected.
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Debugging VIS16 Tests—Visualize Tool
Visualize Tool is used to debug the levels and setup of VIS16. The tool allows
modification of levels and hardware setup while paused on a test.
Select Tools > Visualize from ITE to bring up Visualize Tool.
To begin:
1. Select Show > VIS from Visualize Tool to display the VIS Settings window (see
Figure 46).
Figure 46. VIS Setting Window
2. Select the signals to display.
3. Click Show to view them in Visualize Tool (see Figure 47).
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Debugging VIS16 Tests—Visualize Tool
Figure 47. Visualize Tool—VIS16
Visualize Tool displays the current hardware settings of VIS16 hardware.
Individual values can be modified and applied to the test system hardware while paused
on a test. White cells can be modified. Gray cells cannot.
To modify a hardware value and re-run the test:
1. Change the value of a cell and press Enter. The cell changes color to yellow to
indicate that the value has been modified, but the hardware has not been updated.
2. Select Set to update hardware. Green cells indicate that the hardware was
successfully changed. Red cells indicate the hardware was not successfully changed.
3. Select Get to read back the hardware values.
4. Select Retest from the Execution tab to re-run the test with the new hardware
settings. Continuing from the pause and re-running the program resets the hardware
values.
5. Select Show Members in the right-click menu to expand a pin group.
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Debugging VIS16 Tests—Shmoo and Margin
Shmoo and Margin tool can be used to debug a test using VIS, but they are limited to the
measurement result.
The parameters that can be varied are limited to:
•
setVoltage (force voltage value)
•
setCurrent (force currentvalue)
•
LimitLo
•
LimitHi
•
measDelay
•
measSampleCount
Figure 48. VIS16 Shmoo and Margin Parameters
This does not re-run a complete test with a new set of values but modifies the parameters
exercised and depending on the method selected re-executes the appropriate test. For
example, if functional is selected as a method then the functional test is re-executed.
The only mean to re-execute a full sequence is to use a user_shmoo section where the
user can define what needs to be done for each new set of parameters of the
margin/shmoo.
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Debugging VIS16 Tests—Shmoo and Margin
Knowledge Check
1. How many resources are available on a VIS16?
2. What are the current ranges available on the VIS16?
3. What are the voltage ranges available on the VIS16?
4. How would you create a voltage made of 1 V DC and 1 V sinewave modulation?
5. What is the purpose of the kelvin test?
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Lab Exercise
VIS16 Loopback Lab
This lab creates several loopback tests on VIS used in different modes.
To complete this lab the student must be able to create tests using spec from STIL, the
different modes for the VIS16, and the advanced capture modes.
1. Open ITE and load the job file.
2. Add a new test VIS16_loopback for VIS16 with Program Developer
a. Turn on the ±5 V and +5 V relay user supplies.
b. Disconnect relay Bypass_VI to allow direct loopback.
c. Setup LT1121_IN as a voltage source forcing 5 V, slew rate SLEW_FAST, and
compensation COMP_FAST.
d. Set current range to 300 mA, measure mode to MEAS_CURRENT.
e. Setup LT1121_OUT as a current source sinking 10 mA on the 30 mA range.
Note — Between force and measure the user can vary the setup using the vi_setup
variable inherited from the STIL file.
f.
Set the measure mode to MEAS_VOLTAGE.
g. Check the voltage at LT1121_OUT and the current at LT1121_IN.
Hint — For test time efficiency the user can trigger the measure on two VIS16
instruments in one instruction and then retrieve results per site and per VIS as described
below.
cscTester->VIS()->Signal("ALL_LT1121")->trigger();
double result_VIsrc, result_VImeas = 0.0;
CSC_SERIAL_BLOCK_BEGIN
result_VImeas = cscTester->VIS()->Signal("LT1121_OUT")
->getMeasData();
result_VIsrc = cscTester->VIS()->Signal("LT1121_IN")
->getMeasData();
test_var("V LT1121OUT loopback @10mA", 4.9, 5.1 ,result_VImeas,
"V", 400);
test_var("I LT1121IN loopback @10mA", 9.5e-3, 10.5e3,result_VIsrc, "A", 401);
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Debugging VIS16 Tests—Shmoo and Margin
CSC_SERIAL_BLOCK_END
h. Reset the load to 0 mA.
i.
Create a ramp from 0 to 5 V in 5 ms on LT1121_IN using the
setupGeneratorRamp(src,0.0,5.0,5e-3); //ramp 0 to 5 V in 5 ms.
j.
Start the ramp with gate timer of 0 s and a duration of 100 ms.
k. Measure 100 samples in SAMPLE_CAPTURE mode on LT1121_OUT with
sampling frequency of 10 kHz.
l.
Trigger for all source and measure signals.
m. Save the result as an VI_timer{sitenum}.awav using the savedouble2awav
function. Check it with AWT.
Hint — Use int sitenum = *cscIter as parameter of the function.
n. Stop generator and modulation gate.
o. Modify the gate timer to start after 3.4 ms and trigger for all signals.
p. Measure 100 samples in SAMPLE_CAPTURE mode on LT1121_OUT.
q. Save the result as an awav using the savedouble2awav function and check it with
AWT.
r.
Stop the generator.
s. Disconnect everyting.
t.
Compare the two awav files.
What do you expect as a phase shift in term of sample number?
VIS16 Through Voltage Regulator
1. Add a new test VIS16_LT1121 to allow connection of LT1121_IN to LT1121_OUT
through the 5 V voltage regulator (LT1121).
a. Connect relay Bypass_VI to connect the VI through the regulator.
b. Setup LT1121_IN as voltage source (6 V force, 6 V range, SLEW _FAST,
MEAS_CURRENT mode, 300 mA clamp) and connect.
c. Setup LT1121_OUT to current source 1 mA force (3 mA range,
SAMPLE_AVERAGE_MODE, 12 as samples count).
d. Test Vout on LT1121_OUT.
e. Test Iin on LT1121_IN.
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f.
Sink 10 and 20 mA out of the regulator on the 30 mA range and check that
LT1121_OUT keeps the correct regulated value (5 V). Use the
SAMPLE_AVERAGE on 12 samples to make the measurement on LT1121_OUT.
g. Sink back 0 mA on LT1121_OUT and disconnect.
h. Then source 0 V on LT1121_IN and disconnect.
Check Your Work
Review the work and have the instructor sign off this module.
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9
Triggering Methods
Goal
Understanding the general theory in triggering to make a mixed signal test.
Objectives
After completing this unit, students should be able to:
•
Make proper trigger definition
•
Use triggers to realize optimized tests
In This Module
______
______
______
Instructor Presentation
Knowledge Check
Lab Exercise
30
5
2
Minutes
Minutes
Hours
Resources
Diamond Series Online Help
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9 – Triggering Methods
Triggering Hardware
All instruments in a Diamond Series are connected together through a backplane. On this
backplane 10 lines are dedicated to triggers and 8 are available to the user.
The event routing class allows the user to setup routes. Typically there is a set of events
available on each board that will send/receive events to/from the backplane.
The case presented in Figure 49 is a simple digital pin triggering event on the MultiWave
and VIS16 instrument.
Figure 49. Routing Example in Dual Site
DD1096
DD1096
DD1096
[TRGA]
Multiwave Awg
[TRGB]
Multiwave Dig
[TRGC]
VIS16
Routing
DD1096
Mutiwave Awg
Multiwave Dig
VIS16
Doing such routing translates in code to:
cscTester->EventRouting()->createRoute("adcTriggerLine", REGISTERED,
DISALLOW_LOCAL);
cscTester->EventRouting()->Route("adcTriggerLine")->setSource
("dpin1", EVTTYPE_DPIN96_COMP_HI);
cscTester->EventRouting()->Route("adcTriggerLine")
->addDestination("vis16", EVTTYPE_VIS16_ADC_TRIG);
cscTester->EventRouting()->Route("adcTriggerLine")
->addDestination("multi_awg", EVTTYPE_MW_AWG_START);
cscTester->EventRouting()->Route("adcTriggerLine")
->addDestination("multi_dig", EVTTYPE_MW_DIG_START);
cscTester->EventRouting()->apply()
All single EVTTYPE are located in $DMD/include/*.h.
As the number of routes is limited to 8, the user might need to reconfigure the routes. This
is possible by defining all routes that might be needed for the program and then using the
enable/disable method followed by the apply method.
The EventSource can also be a logical combination of individual EVTTYPE leading to
very complex scheme. Logical equations available are: OR, AND, and NOT.
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DD1096-16 Triggers Available
DD1096-16 Triggers Available
In most of the mixed signal devices the digital interface is the main location to trigger. It
means that most of the devices trigger analog measurements or analog sourcing based
on synchros or triggers emerging from the digital world (STIL pattern).
Table 19 is the list of allowed routings for the DD1096.
Table 19. Triggers Available as Source for DD1096
Event Type
Definition
EVTTYPE_DPIN96_COMP_HI
Comparator high result
Note — DD1096-16 currently supports only one event source per hardware unit routed to
the backplane. For multi-site operation the same signal pin has to be defined in the signal
map for multiple sites
VIS16 Triggers Available
For the VIS16, there are multiple sources and destinations available for the triggers. The
possible sources are listed in Table 20.
Table 20. Triggers Available as Source on VIS16
Event Type
Definition
EVTTYPE_VIS16_COMP_V_HI
High voltage comparator result
EVTTYPE_VIS16_COMP_V_LO
Low voltage comparator result
EVTTYPE_VIS16_COMP_V_HYST
Hysteresis voltage comparator result
EVTTYPE_VIS16_COMP_I_HI
High current comparator result
EVTTYPE_VIS16_COMP_I_LO
Low current comparator result
EVTTYPE_VIS16_COMP_I_HYST
Hysteresis current comparator result
The possible destinations are listed in Table 21.
Table 21. Triggers Available as Destination on VIS16 (Sheet 1 of 2)
Event Type
Definition
EVTTYPE_VIS16_OGT_HI
Output gate hi
EVTTYPE_VIS16_OGT_LO
Output gate lo
EVTTYPE_VIS16_V_GATE
Voltage gate
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Table 21. Triggers Available as Destination on VIS16 (Sheet 2 of 2)
Event Type
Definition
EVTTYPE_VIS16_I_GATE
Current gate
EVTTYPE_VIS16_M_GATE
Modulation gate
EVTTYPE_VIS16_GENERATOR
Arbitrary generator start
EVTTYPE_VIS16_STEP_TRIG
Step triggering
EVTTYPE_VIS16_ADC_TRIG
ADC trigger
EVTTYPE_VIS16_TMU_START
TMU start
EVTTYPE_VIS16_TMU_STOP
TMU stop
EVTTYPE_VIS16_TMU_ARM,
TMU arm
Note — The triggers can be combined with the timers on VIS16 and the sequence can be
pretty complex. For example, start the generator and the ADC trigger by the same
DD1096 comparator high, and delay the ADC trigger to be sure the setup time is
respected.
//example to setup route1 and 2 to measure a rise time
// comp_lo on VIS16 -> tmu_start on VIS16
// comp_hi on VIS16 -> tmu_start on VIS16
cscTester->EventRouting()->createRoute("route1", REGISTERED,
DISALLOW_LOCAL);
cscTester->EventRouting()->Route("route1")->setSource(signal,
EVTTYPE_VIS16_COMP_V_LO);
cscTester->EventRouting()->Route("route1")->addDestination(signal,
EVTTYPE_VIS16_TMU_START);
cscTester->EventRouting()->createRoute("route2", REGISTERED,
DISALLOW_LOCAL);
cscTester->EventRouting()->Route("route2")->setSource(signal,
EVTTYPE_VIS16_COMP_V_HI);
cscTester->EventRouting()->Route("route2")->addDestination(signal,
EVTTYPE_VIS16_TMU_STOP);
cscTester->EventRouting()->apply();
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MultiWave Triggers Available
MultiWave Triggers Available
For MultiWave, there are multiple destinations available for the triggers. They can allow
various actions such as single measurements, AWG start, digitizer start, and so on.
The possible destinations are listed in Table 22.
Table 22. Triggers Available as Destination on MultiWave
Event Type
Definition
EVTTYPE_MW_DIG_TRIG
Triggers the digitizer in single step mode
EVTTYPE_MW_AWG_TRIG
Triggers the AWG in single step mode
EVTTYPE_MW_DIG_START
Starts or gates the digitizer
EVTTYPE_MW_AWG_START
Starts or gates the AWG
//create new trigger
cscTester->EventRouting()
->createRoute("my_route",REGISTERED,DISALLOW_LOCAL);
//add source
cscTester->EventRouting()->Route("my_route")->setSource("trigger",
EVTTYPE_DPIN96_COMP_HI);
//add destinations
cscTester->EventRouting()>Route("my_route")
->addDestination(genCh,EVTTYPE_MW_AWG_TRIG);
cscTester->EventRouting()->Route("my_route")
->addDestination(digCh,EVTTYPE_MW_DIG_TRIG);
cscTester->EventRouting()->apply();
//mode single sample per trigger
cscTester->MultiWave()->Signal(genCh)->OutputCtrl()
->selectStartInput(TQ_SOFTWARE);
cscTester->MultiWave()->Signal(genCh)->OutputCtrl()
->selectStepTrigger(TQ_RISING_EDGE_BP);
cscTester->MultiWave()->Signal(digCh)->InputCtrl()
->selectStartInput(TQ_SOFTWARE);
cscTester->MultiWave()->Signal(digCh)->InputCtrl()
->selectStepTrigger(TQ_FALLING_EDGE_BP);
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9 – Triggering Methods
Notes
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MultiWave Triggers Available
Knowledge Check
1. How many routes are available on the backplane?
2. What logical operators are supported in a source event?
3. What is the EVTTYPE representing the result of the voltage comparator high on a
VIS16?
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Lab Exercise
Triggering Lab
This lab creates a test that ramps 0 to 10 V with a given slew rate and allows the user to
measure the rise time using a TMU.
To complete this lab the student must be able to create tests using spec from STIL, create
a ramp on a VIS16 and use the TMU. In addition, the triggering method is used to start
the measurements.
1. Open ITE and load the job file.
2. Edit the CPP code and add a new test VIS16_Ramp_TMS.
3. Create the spec from parameters present in the equations_ref.stil to define the
minimum, maximum, and duration of the ramp. Use the level threshold definition the
same way for both start and stop level.
4. Use channel LT1121_IN to define a ramp 0->10 V in 5 ms (range 20 V, 30 mA). The
predefined code setupGeneratorRamp can be used.
5. Define two triggers routes. One route to have source event on the TMU from
comparator low result and the destination event on TMU from comparator high result
on TMU. You can use the setupEventRoutingTMS for this purpose.
6. Set the comparator levels to be the level threshold values (for example, 1 V and 6 V)
7. Define the polarity of the TMS given the fact that the rise time is to be measured.
10 V
high
low
0 V
Comparator low
Rise time
Comparator high
8. Start the modulation and generator gate.
9. Trigger the start of measurement.
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MultiWave Triggers Available
10. Make sure the measurement ended properly (timeout if the TMS remains busy). An
example of code is shown below:
//timeout function
int count = 0;
while((count < 2000) && cscTester->TMS()->Signal("LT1121_IN")->IC()
->isBusy())
{
cscUtil->wait(1e-3);
count++;
};
if(count >= 1000) { // Timeout detected
cscExec->Test()->variable(1.0, "s");
}
else {
double value = 0.0;
value = cscTester->TMS()->Signal("LT1121_IN")->IC()->
getMeasData();
cscExec->Test()->variable(value, "s");
}
11. Readback the TMS value and test it using test_var function.
12. Stop Generator.
13. Clear routes.
Note — The wave can be observed with a scope on J111 or J211 (site 0 and site1
respectively).
Triggering MultiWave with a DD1096
This lab creates a test that uses loopback to step a ramp from the MultiWave source and
measure in step on MultiWave measure. The source and measure steps are controlled in
phase by the DD1096 comparator high result (one dedicated channel is used for both
sites).
To complete this lab the student must be able to create tests using a pattern generation,
and create a ramp on a MultiWave and source/capture in steps using dedicated routes.
1. Open ITE and load the job file.
2. Edit the CPP code and copy the HF_loopback_multiwave test to
HF_quasi_static_by_trigger.
3. Change the waveform to be loaded from internal sine to an arbitrary waveform taken
from ./waves/myRamp.awav file.
4. Keep everything identical to the loopback setup until the AWG setup.
5. Before the AWG starts, add a section to control the trigger pin as a source for trigger
and AWG and DIG as destinations for Step triggers.
6. Add a start trigger to be software on both AWG and DIG.
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9 – Triggering Methods
7. Keep the loopback setup again until the digitizer starts.
8. After the DIG starts, execute the ExampleExec PatternExec to make the pattern to
execute and the sampling start.
9. Wait for the capture to be completed and save the resulting waveform in an awav file.
10. Stop AWG and digitizer, disable step trigger, and clear routes.
Note — In version 1.5.2 of software the result on measure side is not as expected due to
an FPGA issue. As a consequence a scope is needed to observe the MultiWave AWG
output (J108 or J208 to observe with a scope).
Check Your Work
Review your answers and have the instructor sign off this module.
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10
Digital Source and Capture in Mixed Signal
Goal
Learn to use the capture memory for Mixed Signal tests.
Objectives
After completing this unit, students should be able to:
•
Understand how to source digital data with DD1096
•
Understand the features of the Digital Capture memory
•
Create a loopback test using digital source and digital capture
In This Module
______
______
Instructor Presentation
Lab Exercise
20
1
Minutes
Hour
Resources
Diamond Series Documentation Set
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10 – Digital Source and Capture in Mixed Signal
Digital Source
The instrument uses the DD1096 to source a digital wave. Use AWT to generate the
binary data for the converter and then copy and paste inside a STIL pattern to properly
drive data to the DUT. The various sources offered by the DD1096 can be used.
Either write a straight STIL file to generate the code for the converters and it could be a
very long pattern or use the advanced features (mainly scan and APG modes) of the
DD1096.
In the example used later in the lab, scan mode is used because it offers the flexibility to
load any waveform and the writing of such a pattern (even for serial input devices)
remains short provided a limited number of samples are used.
To generate a ramp instead of a sinewave and measure all the codes, the APG might be
an alternative in terms of STIL statements.
Write a source data in scan mode STIL example:
//Signals definition
Signals {
"dig_loopback_in" In {ScanIn;}
"dig_loopback_out"Out{ScanOut;}
}
//Macro definition
MacroDefs {
DACStep {
W "wftSimple";
V {ALL_dig_DAC = H
V {ALL_dig_DAC = L
Shift {
V { dig_loopback_in
}
V {ALL_dig_DAC = H
V {ALL_dig_DAC = L
}
}
0
0
1
1
0
0
1;}
1;}
= #; dig_loopback_out = L;}
0
0
1
1
0
0
1;}
1;}
//Pattern
Pattern DACPat {
W
V
V
V
V
"wftSimple";
{ ALL_dig_DAC
{ ALL_dig_DAC
{ ALL_dig_DAC
{ ALL_dig_DAC
Macro
Macro
Macro
Macro
Macro
162
DACStep
DACStep
DACStep
DACStep
DACStep
{
{
{
{
{
=
=
=
=
X
X
X
X
0
0
0
0
1
1
1
1
dig_loopback_in
dig_loopback_in
dig_loopback_in
dig_loopback_in
dig_loopback_in
X
X
X
X
1;
1;
1;
1;
=
=
=
=
=
}
}
}
}
1000000000000000;}
1000000011001001;}
1000000110010010;}
1000001001011011;}
1000001100100100;}
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Digital Source
V
V
V
V
}
{
{
{
{
ALL_dig_DAC
ALL_dig_DAC
ALL_dig_DAC
ALL_dig_DAC
=
=
=
=
X
X
X
X
0
0
0
0
1
1
1
1
X
X
X
X
1;
1;
1;
1;
}
}
}
}
Digital Capture Memory
The Data Capture memory (DCM) is a 16 M capture space for non-deterministic vector
capture. Applications include ADC testing and memory reads. It is the same memory that
is used by the digital subsystem to capture pass/fail data.
Figure 50. DCM Conceptual Diagram
ADC
11011001
To DCM
In the case of ADC testing the data can be sent to the host for processing by the DSP
library. Other applications for DCM memory include:
•
Readback of EEPROM or other memory data
•
Readback of device or loadboard IDs
•
Learn mode
There are some restrictions to know when designing a loadboard.
•
The bus wide is maximum of 48 bits.
•
The bus has to be located on a single Omni for a given site for optimization using
DCM_HW, while the DCM_SW is able to re-assemble spread bits over Omnis or over
instruments.
Best practice—Choose bus mapped over pins (0..47) or (48..95) and located on a single
instrument.
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10 – Digital Source and Capture in Mixed Signal
DCM Capture Example
Typical calls for an ADC test look like:
Register the capture set with a name, start, and stop labels list and signal list.
cscTester->DCM()->add(“ADC_test”, “s1”, “s2”, “ADC”);
The specified capture set takes effect on the next pattern burst:
cscTester->DCM()->enable(“ADC_test”);
Returns the number of samples captured:
samples = cscTester->DCM()->getCapturedCycleCount();
Retrieves the captured data:
cscTester->DCM()
->getCapturedDataBySite(sitenum,"ADC",start_idx,
number_of_samples,data,DCM_HW);
Table 23. DCM Capture Code Implementation
API
Functionality
add()
Registers a capture set
enable()
Enable DCM on next pattern burst
getCapturedCycleCount()
Returns how many cycles were captured
getCapturedDataBySite()
Retrieves the captured data
release()
Frees the DCM memory
disable()
Turn off data capture on next pattern burst
getNames()
Get a list of all potential capture sets
getEnableName()
Get the current enables capture set
Below is a full example of a capture code for a 16 bits serial out device:
void Digital_loopback_Test()
{
vector <string> start_label_list, stop_label_list;
cscExec->Test()->setCurrentName("Digital Loopback Test (16 bits serial)");
cscExec->Test()->setCurrentNumber(200);
//fill label lists
start_label_list.push_back("DLBPat.label1");
stop_label_list.push_back("DLBPat.label2");
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Digital Source
//setup DCM
cscTester->DCM()>add("my_capture_lb",start_label_list,stop_label_list,"dig_loopback_out");
cscTester->DCM()->enable("my_capture_lb");
cscTester->DCLevels()->Signal("ALL_lb")->enableComparator();
cscTester->DCLevels()->Signal("ALL_lb")->setForcePattern();
//execute the pattern burst
cscExec->PatternExec("DLBExec")->execute();
long int numcapt = cscTester->DCM()->getCapturedCycleCount();
printf("Capture length = %d \n",numcapt);
CSC_SERIAL_BLOCK_BEGIN
int sitenum = *cscIter, i, j;
unsigned long int myData[numcapt];
//retrieve data
cscTester->DCM()
->getCapturedDataBySite(sitenum,"dig_loopback_out",0,numcapt,myData,DCM_HW);
double data[numcapt];
vector<double> my_data_double;
for(i=0;i<numcapt/20;i++)
data[i]=0;
//serial out (16bits with significant bits 2 to 18) to integer
for (i=0;i<numcapt;i+=20) {
for (j=2;j<18;j++) {
data[i/20] += myData[i+j] * pow(2.0,double(17-j));
}
}
for (i=0;i<numcapt/20;i++) {
my_data_double.push_back((double)data[i]);
}
DspWaveform *dspData
= new
DspWaveform(DspWaveform::wftRRect,"myWave",my_data_double,NULL);
char my_char[256];
sprintf(my_char,"./waves/digital_capture_site%d.awav",sitenum);
//save as awav
dspData->writeAwavFile(my_char,true);
// get characteristics
double snr,thd,sinad,magn,fund,spur,maxSpur;
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10 – Digital Source and Capture in Mixed Signal
dspData->ratiosMeas( 5,NULL,&snr,&thd,&sinad,&magn,NULL);
//use test_var function to evaluate the results
test_var("Ampl digitizer", 32767.0, 32768.0,magn, "V", 201);
test_var("SNR", 6.02*15+1.76, 6.02*17+1.76 ,snr, "dB", 202);
CSC_SERIAL_BLOCK_END
//release DCM
cscTester->DCM()->release("my_capture_lb");
}
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Digital Source
Lab Exercise
DCM Lab
This lab is aimed at emulating a digital source for a DAC and retrieving a digital output
from an ADC. To do this some files and functions have been prepared. The sourced data
(on dig_loopback_in) is serialized with 16 significant bits and 20 bits total. The user has to
extract the 16 significant bits to be able to do DSP computation.
For the following labs, change directory to ./training_dacadc/lab. The res and sig files are
already defined for the DAC and ADC to be used.
1. Open Program Developer by typing vs & in a command prompt or launching program
developer from ITE.
2. Go inside the ./patterns directory and open the digital_loopback.stil file.
Note — This pattern is using a scan mode to generate the serial_data necessary to feed
the DAC. dig_loopback_in is the source and dig_loopback_out_out is used as a pure
output to capture the fails. This is why a L is used. Any expected L failing are actually 1
and passing will be 0 so the data will be coded properly.
3. Create a new test Digital_Loopback_Test with the following actions:
a. Create a cpp <vector> start_label_list made of pattern_name.label1 and a vector
stop_label_list made of pattern_name.label2.
b. Setup and enable a DCM capture from start_label_list to stop_label_list on
dig_loopback_out pin.
c. Execute the DLBLevelsExec patternExec with comparators enabled on ALL_lb
pingroup to setup levels and timing
d. Use the cscTester->Seq()->setStartAdress and cscTester->Seq()->start
commands to execute the pattern without P/F status. The pattern is expected to
fail and we are only interested in the captured data.
e. Count the numbers of captured data using API.
f.
Retrieve the data and save as awav using DSP waveform API
g. Test the Amplitude and SNR (Amplitude = 65535 and SNR = 6.02 x Neff + 1.76)
with Neff being 16.
4. Add the test in the user_main section.
5. Add the digital_loopback.stil file in the job file.
6. Compile the job file.
7. Load and execute the test.
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10 – Digital Source and Capture in Mixed Signal
8. You can aso check the result in AWT by opening the generated awav file.
9. Optionally, use AWT to create another waveform like a ramp on 1024 pts.
a. For that purpose generate a waveform.
b. Select File > Save As command and select SWAV Parallel Files (*.swav) in the
Files of Type menu.
c. Select number of bits 16 in Natural Binary. The other options can remain.
d. Copy and paste the generated parallel code instead of the existing code.
e. Recompile the pattern, reload the test program and re-run the test.
The AWT generated file should be similar to the one just created.
Check Your Work
Review your answers and have the instructor sign off this module.
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11
DAC Tests Using MultiWave DIG
Goal
Learn to use MultiWave to perform typical DAC tests.
Objectives
After completing this unit, students should be able to:
•
Review typical DAC tests and methods
•
Be able to build tests for DAC using MultiWave digitizer
•
Understand the triggering concept to sync digital and analog
In This Module
______
______
______
Instructor Presentation
Knowledge Check
Lab
1
5
90
Hour
Minutes
Minutes
Resources
Diamond Series Online Help
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11 – DAC Tests Using MultiWave DIG
Analog Waveform Capture
This chapter concentrates on using the Diamond Series MultiWave Digitizer (DIG).
Starting with a high level view of what digitizing is all about, and then focus on how to use
the MultiWave digitizer to test DACs.
This chapter also contains information on common tests that utilize the digitizer, as well
as a review of some sampling theory concepts needed to realize the best possible
performance from the instrument.
The lab exercise at the end of this chapter provides the student with the opportunity to
use the various features of the MultiWave digitizer and to see how common tests are
accomplished.
Typical Waveform Digitizer Architecture
Figure 51 depicts a typical waveform digitizer architecture. It consists of five blocks or
stages:
•
Input scaling and level shifting
•
Input filtering
•
Analog-to-digital conversion
•
Storage into digital memory
•
Digital Signal Processing
Figure 51. Waveform Digitizer Architecture
Analog
Signal
170
Scaling
and Level
Shifting
Anti-Alias
Filter
ADC
Waveform
Storage
Digital
Signal
Processing
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Analog Waveform Capture
Input Scaling and Level Shifting
The primary purpose of this block is to match the signal to the digitizer’s input. This is
done with a combination of scaling and level shifting, as shown in Figure 52.
Figure 52. Waveform Scaling Issues—Courtesy Soft Test Inc.
Amplitude
Vinfs
ADC
Input
Signal
Vinzs
ADC
Output
All Ones
ADC
Output
All Zeroes
ADC
Output
All Ones
ADC
Output
All Ones
Time
In addition, the input signal may be single-ended or differential.
Input Filtering
Before an analog signal can be properly digitized, it should be filtered to restrict its
bandwidth. The filters used for this purpose are usually called anti-alias filters. Anti-alias
filters are generally fixed frequency, analog filters.
In addition, some digitizers have a notch, or band-reject, filter in the signal path. This
allows the user to remove the test frequency from the signal and use the entire dynamic
range of the digitizer to find the small distortion and noise components present.
Analog-to-Digital Conversion
The process of analog-to-digital conversion consists of both sampling and quantization.
Because of the wide range of signals that need to be digitized by an ATE system, a single
ADC may not suffice. For example, audio signals require high precision at low sampling
frequencies, while video signals require less precision at higher frequencies.
There are several different ADC device architectures. Each has their own pros and cons.
Most waveform digitizers use either Successive-Approximation Register (SAR) or Sigma
Delta ADCs.
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11 – DAC Tests Using MultiWave DIG
Quantization is part of the process of digitization. An ADC is capable of producing a finite
set of outputs, and quantization refers to the many-to-one mapping of an analog input to a
digital output.
The other part of digitization is sampling, meaning when this quantization is to occur.
4XDQWL]DWLRQ
Figure 53. Digitization Consists of Sampling and Quantizing
Sampling
Quantization Error puts an upper limit on just how good a particular device or instrument
can be. The more bits a digitizer has the more possible quantization levels, and the more
accurate the representation of the corresponding analog input signal.
The Quantization Error Q is bounded by plus or minus one-half an LSB. How Q limits the
Signal to Noise ratio of an ADC is detailed later.
Figure 54. Quantization Error Illustration
Quantized
Ideal
Storage and Digital Signal Processing
Most mixed-signal test systems have dedicated memories for storing captured data,
separate from vector or program memory. This memory is often called waveform memory,
and contains captured waveform data that is then processed by the test system to
calculate various parametric values such as distortion, gain, and so on.
This memory may be dedicated or general purpose, and may reside on the instrument,
controller, CPU, or a shared resource.
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DAC Description
DAC Description
A Digital-to-Analog Converter (DAC) is a device whose output is analog signal. The tests
performed might also be done on other types of analog ICs. The tests fall into one of two
categories:
•
Static tests
•
Dynamic tests
Both tests are important and indicate how well the device performs its intended
application. Certain applications may value one test type over another for technical and
cost considerations.
Static Tests
Static tests are a measure of a device’s linearity. This could also be viewed as the
accuracy of its transfer function. For example, a unity gain buffer has a transfer function
similar to that shown in Figure 55.
Analog Output 0–5 V
Figure 55. Unity Gain Buffer Transfer Function
Analog Intput 0–5 V
Many DACs have the same type of transfer function, but the X-axis is the digital input.
Analog Output 0–5 V
Figure 56. DAC Transfer Function
In the case of the transfer
function y = mx + b, the
variable b represents the
DC offset error, while m
represents the gain.
Digital Input 0x00–0xFF
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11 – DAC Tests Using MultiWave DIG
There are four basic measures of linearity:
•
Gain
•
Offset
•
Integral non-linearity
•
Differential non-linearity
These tests are normally done by stimulating the device in such a way that it outputs a
ramp, or linear transfer function. Because these tests are often done slowly, without
dynamic considerations, they are generally considered static tests.
Linearity tests are detailed later in this chapter.
Dynamic Tests
Dynamic tests look at the operation of the device under conditions that more closely
approximate the application. For most DACs, the signals generated by the device is a
sine wave.
Figure 57. Dynamic Testing and Frequency Domain Analysis
The most common dynamic tests are:
•
Signal-to-Noise Ratio (SNR)
•
Total Harmonic Distortion (THD)
•
Signal-to-Noise and Distortion (SINAD)
The captured data for these tests is usually processed using frequency domain analysis,
utilizing a Fast Fourier Transform (FFT). More details follow later in the chapter.
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DAC Testing Using a Digitizer
DAC Testing Using a Digitizer
Linearity Testing
Static testing is often called linearity testing, and can further be broken down into Integral
Non-Linearity (INL) and Differential Non-Linearity (DNL). Two other common
measurements are Offset and Gain.
INL is a measure of the absolute error at a given point relative to the ideal transfer
function. DNL is a measure of the step size error from one output to the next.
INL and DNL tests are usually conducted using signals that represent ramps. It steps
through each value of possible inputs and measures the resulting outputs. It can then
compare the observed transfer function to an ideal one predicted by the specification, and
come up with measurements for offset, gain, INL, and DNL.
Figure 58. Linearity Errors in DACs Summary—Courtesy Soft Test, Inc.
Gain Error
Ideal full scale output
Actual full scale output
Actual full scale—offset error
Analog output (V)
Non-monotonic
Actual output
Optimum output
INL = Actual output—Optimum point on line
Straight line
between endpoints
Device FSR
Actual LSB Step
Calculated Device LSB size
DNL = Actual step—Calculated size
0
Offset Error
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Digital code input
175
11 – DAC Tests Using MultiWave DIG
Common Formulas and Computations for Static DAC Tests
Full Scale Range: V FSR = V FS – V ZS
Where VFS is the full scale voltage measurement and VZS is the zero scale measurement.
FSR
measured
LSB: LSB = --------------------------
2bits – 1
Offset Error Voltage: V OFFSET = V ZS [ measured ] – V ZS [ ideal ]
Offset Error:
Units
Conversion
%FS
VOFFSET
------------------------- ⋅ 100
FSR IDEAL
ppm
V OFFSET
------------------------- ⋅ 10 6
FSR IDEAL
LSB
V OFFSET
------------------------LSB IDEAL
The offset error voltage is often normalized to another unit. Typical units in the device
specification are %FS, ppm, and LSB.
Gain Error Voltage: Gain Error Voltage = ( V FS – V ZS ) – V FSR [ ideal ]
Gain Error: GainError = ( FSR ACTUAL – FSR IDEAL )
Normalized to the unit of choice.
Differential Nonlinearity: = ( V code[i] – V code[i-1] ) – 1LSB
DNL an INL are usually normalized to LSBs. Then the formula is:
( V code[i] – V code[i-1] ) – LSB
DNL code [ i ] = -------------------------------------------------------------LSB
n=i
Integral Nonlinearity: INL [ i ] =
∑ DNL [ n ]
n=1
Note — The above formula for INL is based on the end-point or straight-line method. An
alternative to this is the best fit method, which uses a curve fitting algorithm such as the
sum of least squares.
The Credence DSP library does not contain a high level function for either one of these
methods. The user must decide which one to implement and write it explicitly. The lab
exercise requires writing some code to calculate linearity.
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DAC Testing Using a Digitizer
Dynamic Testing
Dynamic testing is usually done using sinusoidal test signals, and result processing is
done using Frequency Domain techniques. Common dynamic tests include Signal-toNoise Ratio (SNR), Signal-to-Distortion Ratio (SDR), and Signal-to-Noise-and-Distortion
Ratio (SNDR).
Distortion and Noise testing looks at the output of a signal and how it differs from the
ideal. All devices add at least some small amount of unwanted signal content to their
outputs, in addition to the desired output signal.
Linear Systems theory tells us that a circuit with an input at frequency Fi can only output
signals containing Fi. In the real world that is not true. Signal content is classified into
these three categories:
•
Signals at same frequency as input
•
Signals at integer multiples of input frequency
•
Everything else
Fi
Fi
Harmonics are integer multiples of the original frequency. They are a result of the nonlinearities of the DUT. While in theory these harmonics extend out to infinite frequencies,
most users are interested in the first 5 to 10 harmonics.
Figure 59. Harmonic Distortion in DACs
Fi
Fi
2*Fi
3*Fi
n*Fi
Noise is categorized as everything in the frequency spectrum that is not signal or
harmonic distortion. Some sources of noise include:
•
Gaussian (random) noise
•
Quantization noise
•
Correlated noise
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11 – DAC Tests Using MultiWave DIG
Common Formulas and Computations for Dynamic DAC Tests
⎛
⎞
⎜
⎟
⎜
⎟
⎜ Magnitude Fundamental ⎟
Signal-to-Noise Ratio: 20 log ⎜ ---------------------------------------------------------⎟
⎜ ( Fs ) ⁄ 2
⎟
⎜
2⎟
( Magni tude Noise ) ⎟
⎜
⎝
⎠
∑
0
⎛
⎞
⎜
⎟
⎜
⎟
⎜
⎟
⎜ Magnitude Fundamental ⎟
--------------------------------------------------------------------Signal-to-Distortion Ratio: 20 log ⎜
⎟
⎜ Fs
⎟
-----2
⎜
⎟
⎜
2⎟
( Magnitude Harmonics ) ⎟
⎜
⎝
⎠
∑
0
Signal-to-Noise-and-Distortion Ratio:
⎛
⎞
⎜
⎟
⎜
⎟
⎜
⎟
⎜
⎟
Magnitude Ft
20 log ⎜ ------------------------------------------------------------------------------------⎟
F
⎜ -----s
⎟
⎜ 2
⎟
⎜
2⎟
( Magnitude Noise + Distortion ) ⎟
⎜
⎝
⎠
∑
0
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Sampling Theory
Sampling Theory
Sampling theory is an important part of mixed signal testing. A complete introduction to
the subject is beyond the scope of this class. There are many additional resources that
cover the topics of sampling and Fourier transforms.
An important concept in mixed signal testing is the concept of coherence. One of the
characteristics of performing an FFT on a sampled signal is that the Fourier Transform
assumes the signal is a continuous function that exists for all time. In reality, a captured
signal can be thought of as a continuous signal stretching from minus infinity to infinity,
multiplied by a time window that represents the amount of time over which the samples
have been taken as shown in Figure 58.
Figure 60. A Time Sampled Waveform
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11 – DAC Tests Using MultiWave DIG
The FFT assumes that the signal passed into it is a windowed representation of a
continuous waveform. When the window corresponds to an integer number of waveform
cycles, the sampling is said to be coherent. Coherent sampling has the following
advantages:
•
Signal FFT displays frequency content in a set of discrete bins
•
FFT magnitudes are undistorted by the process of sampling
For example, 1 KHz waveform to be sampled over three cycles of the signal:
Call the waveform frequency Ft (or Fi) by convention (test frequency, or frequency of
interest). Use the variable M to denote the number of cycles.
Figure 61. Test Frequency
)
0
.003
t
1
Ft
The sampling period, or unit test period (UTP) is: UTP = M ⋅ ----Sample this waveform by capturing 16 equally spaced points along the waveform as
shown in Figure 62.
Figure 62. Equally Spaced Samples
1
Fs
Define the UTP in terms of sampling: UTP = N ⋅ ----Where N is the number of samples and Fs is the frequency sampling is performed.
M
3
16
N
By substitution, define the coherence equation as: ----- = ----- or ------------ = ------------------Ft
180
Fs
1000
5333.33
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Sampling Theory
Take the Fast Fourier Transform (FFT) of the signal as shown in Figure 63.
Figure 63. A Frequency Spectrum
Waveform
WaveformininTime
time
FFT
FFTMagnitude
Magnitude
1000
1000
0
0.001 0.002
0.002
0.001
0.003
0.003
Coherent sampling results in a spectrum where frequency content falls into N/2 bins,
each equally spaced by Fs/N (sometimes called Fres, of FF, or for Fourier Frequency).
Figure 64. FFT Using AWT
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Spectral Leakage
The importance of coherent sampling is illustrated by showing an example of noncoherent sampling as shown in Figure 65 with these parameters:
•
Same time domain signal sampled (3 cycles @ 1000 Hz)
•
Sampling rate Fs is set to 5.555 KHz, with N = 16
•
Note that the coherence equation is not met
Figure 65. Spectral Leakage
Waveform
WaveformininTime
time
FFT
FFTMagnitude
Magnitude
1000
1000
0.001 0.002
0.002 0.003
0.003
0 0.001
Note that the time domain waveform shows no noticeable difference. The frequency plot,
however, shows a characteristic known as spectral leakage (or spreading, or skirting).
The primary problem cause by leakage is an artificially high SNR measurement, as
shown in the lab.
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Sampling Theory
Aliasing
When a set of amplitude samples is converted into the frequency domain, the frequency
information returned from the FFT can be ambiguous regarding frequency, because more
than one sinusoid might fit the sample points.
Figure 66. Spectral Ambiguity, or Aliasing—Courtesy Soft Test, Inc.
Signal
Replica
Time
Amplitude
Replica
Signal
Replica
Replica
Replica
Frequency
Ft - Fs
Ft
Ft + Fs
Ft + 2Fs
Ft + 3Fs
A sample set contains the original test signal frequency (Ft), replicated at frequencies
every k times the sample frequency in both the positive and negative directions:
F replica = k ⋅ F s ± F t , k = integer
Notice how the sampled waveform has identical components at additional frequencies;
these replicas extend to infinity. The information returned by an FFT can be analyzed
using the low pass data, the band of frequencies out to Fs/2, ignoring the replicas.
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Figure 67. Continuous Nature of Discrete Spectra
Amplitude
Fs/2
Fs
3Fs/2
Nyquist Band
Mirror
Image
Signal
Mirror
Image
Replica
Mirror
Image
Frequency
Ft - F s
F s - Ft
Fs - F t
Fs + F t
2Fs - F t
Note that the replicas extend to infinity in both directions. A sampled signal with a
component higher than those in the band of interest, but lower than the sample frequency
Fs can end up aliased into the frequency band of interest. This can be a problem. If the
input signal being sampled contains signal components greater than Fs/2, those signal
components are folded into the frequency data for the original signal, distorting the
spectral information.
The spectrum from Fs/2 to Fs is not a replica, it is a mirror image. As is the spectrum from
3Fs/2 to 2Fs, and each even numbered spectrum. The odd numbered spectra are
replicas.
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Digitizer Example Code Implementation
Digitizer Example Code Implementation
The following code example shows several of the Digitizer APIs in use.
Setup of the DIG waveform:
CSCMultiWaveArbitraryWave digWave("hf_capture");
digWave.setPath(HIGH_FREQUENCY);
digWave.setLength(8192*2);
digWave.setIncrement(1);
Allocate DIG memory:
cscTester->MultiWave()->Signal("Dig_1")->Memory()
->createWaveform(&digWave);
Sample clock setup:
double fsample = (4.43e6/46.0)* 1024.0;
long divider = (long)(3.85e9/fsample);
fsample *= divider;
//fi=4.43Mhz, N=1K , M=46
DDS selection and divider per channel:
cscTester->MultiWave()->Signal(signal)->Clock()
->setClock(CLOCK_1,fsample, divider, true);
cscTester->MultiWave()->Signal(signal)->InputCtrl()
->setHfClock(true);
DIG setup:
cscTester->MultiWave()->Signal(signal)->InputCtrl()
->setHfLowPassFilter(F_1P2_MHZ);
cscTester->MultiWave()->Signal(signal)->InputCtrl()
->setHfInputTermination(SINGLE_ENDED )
cscTester->MultiWave()->Signal(signal)->InputCtrl()
->setHfTermMinus(DIG_HF_TERMINATION_50);
cscTester->MultiWave()->Signal(signal)->InputCtrl()
->setHfTermPlus(DIG_HF_TERMINATION_50);
cscTester->MultiWave()->Signal(signal)->InputCtrl()
->setHfRange(range_meas, DIFFERENTIAL);
Turn On DIG:
cscTester->MultiWave()->Signal(signal)->ArmCtrl()
->armDIG(&digWave);
cscTester->MultiWave()->Signal(signal)->InputCtrl()->start();
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Trigger Implementation to Start Digitizing
The trigger implementation on Diamond Series allows the user to decide when to start
and stop the digitizer and/or when to step digitizer.
This flexibility is available by the definition of up to 8 routes made of source and
destinations.
Common routes are:
•
A route from digital world to start the digitizer—Most of the mixed signal devices need
a digital sequence to setup the mode and access the analog cells so some samples
are taken without a need for them.
•
- A route from digital world to analog—To sample by step (case of digital ramp on a
serial DAC for example).
The digital pin triggers the start of the digitizer as shown in Figure 68.
Figure 68. Start Digitizer in Continuous Mode on Rising Edge
trigger
Effective sampling
Converter clock
//Event routing to the backplane
//create new trigger
cscTester->EventRouting()->
createRoute("my_route1",REGISTERED,DISALLOW_LOCAL);
//add source
cscTester->EventRouting()->Route("my_route1")->
setSource("trigger",EVTTYPE_DPIN96_COMP_HI);
//add destination-start digitizer
cscTester->EventRouting()->Route("my_route1")->
addDestination(digCh,EVTTYPE_MW_DIG_START);
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//apply route
cscTester->EventRouting()->apply();
//mode start awg per trigger-1 trigger only needed cpp must control arm
cscTester->MultiWave()->Signal(digCh)->InputCtrl()->
selectStartInput(TQ_RISING_EDGE_BP);
..->arm(); //.... waiting for trigger pulse
Every trigger pulse from DPIN digitizes a single sample as shown in Figure 69.
Figure 69. Start Digitizer in Step Mode on Rising Edge
trigger
Effective sampling
Converter clock
//Event routing to the backplane
//create new trigger
cscTester->EventRouting()->
createRoute("my_route2",REGISTERED,DISALLOW_LOCAL);
//add source
cscTester->EventRouting()->Route("my_route2")->
setSource("trigger",EVTTYPE_DPIN96_COMP_HI);
//add destination-start digitizer
cscTester->EventRouting()->Route("my_route2")->
addDestination(digCh,EVTTYPE_MW_DIG_TRIG);
//appply route
cscTester->EventRouting()->apply();
//mode single sample per trigger-1trigger needed per sample cpp must arm
and start
cscTester->MultiWave()->Signal(digCh)->InputCtrl()->
selectStartInput(TQ_SOFTWARE);
cscTester->MultiWave()->Signal(digCh)->InputCtrl()->
selectStepTrigger(TQ_RISING_EDGE_BP);
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Note — When you are done using the triggers you should deselect them using the
following commands:
cscTester->MultiWave()->Signal(awgCh)->OutputCtrl()->
selectStartInput(TQ_SOFTWARE);
cscTester->MultiWave()->Signal(awgCh)->OutputCtrl()->
selectStepTrigger(TQ_DISABLE);
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Knowledge Check
1. What are the four basic measurements of linearity for a DAC?
2. What is the consequence of non-coherent sampling on the digitized waveform
spectrum?
3. Which API statement would you use to sample with the digitizer in steps from the
backplane on falling edge?
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Lab Exercise
DAC Tests Lab
This lab is creates a typical DAC test using MultiWave as DIG, the DD1096 instrument,
and the available DSP library.
1. Open the test program ./training_dacadc/lab with ITE.
Note — On digital side: pattern is running at 50 ns period, 121 cycles in 1024 samples, 20
periods to make a sample so Fs = 1 / (50 * 20) = 1.0 MHz ; Ft = Fs * M/1024 = 118 kHz.
On the analog side the same sampling frequency is used to digitize so bin 121 is
expected.
2. Add a function called DynamicDACTest including the following steps:
a. Set up the clock to have a sampling frequency on digitizer 20 times less than
digital pattern [selected to be 50 ns] so 1.0 MHz:
setupDigClock(digCh,CLOCK_1,fpll,divider_dig,SIGNAL_PATH_LF)
b. Connect the digitizer to match the loadboard configuration:
AwgDigConnect(digCh,SIGNAL_PATH_LF,MUX_SINGLE_P
c. Set up bypass as filter, the measure range large enough to cope with maximum
output of the DAC (use stil equation DAC_spec->DAC_cat_118k->range_meas):
DigSetup(digCh,SIGNAL_PATH_LF,BYPASS, range_meas, SINGLE_ENDED,
DIG_HF_TERMINATION_50, OSR ,FULLY_FILTERED);
d. Reserve the memory for the waveform:
•
CSCMultiWaveArbitraryWave digWave("lf_capture")
•
DigWaveSetup(digCh,digWave,LOW_FREQUENCY,1,capture_fft *2)
e. Route the trigger pin as source and the digitizer as destination in start mode
using: EventRouting_digital2digitizer("trigger",digCh,"CONT")
f.
startDig(digCh,digWave).
g. Setup levels on Vref and Vdd for AD5541 using:
setup_levels_DAC("AD5541_VDD", 5.0,"AD5541_VREF",amplitude_src)
h. Execute DACdynLevelsExec patternExec and the pattern with statements:
cscTester->seq()->setStartAddress and cscTester->Seq()->start()
i.
stopDigEOC(digCh,SIGNAL_PATH_LF,1.0);
j.
Upload data using DigUpload(digCh,digWave).
k. Process amplitude with ratioMeas DSP function.
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l.
Save the captured waveform a awav file.
m. Test results.
n. Disconnect, clean digitizer memory, and clean trigger routes using:
•
AwgDigConnect(digCh,SIGNAL_PATH_LF, MUX_DISCONNECT)
•
DigClean(digCh,digWave);
•
cscTester->EventRouting()->clearRoutes()
o. Power down device with power_down() function.
p. Compile, run and debug test.
Check Your Work
Review your answers and have the instructor sign off this module.
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Notes
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ADC Tests Using MultiWave AWG
Goal
Learn to use the MultiWave to perform typical ADC tests.
Objectives
After completing this unit, students should be able to:
•
Review typical ADC tests and methods
•
Understand the triggering concept to sync digital and analog
•
Write tests for ADC using MultiWave
In This Module
______
______
______
Instructor Presentation
Knowledge Check
Lab Exercise
1
5
90
Hour
Minutes
Minutes
Resources
Diamond Series Documentation Set
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Waveform Generation
This chapter concentrates on using the Diamond Series MultiWave AWG. Starting with a
high level view of what generation is all about, and then focus on how to perform test
using the MultiWave AWG.
This chapter also contains information on common tests that use the MultiWave AWG. In
addition, it includes a review of sampling theory concepts that are needed to realize the
best possible performance from the instrument.
The lab exercise at the end of this chapter provides the student with the opportunity to
use the various features of the MultiWave AWG, and to see how common tests are
accomplished.
Typical Waveform Source Architecture
Figure 70 depicts a typical waveform digitizer architecture. It consists of four blocks or
stages:
•
Waveform memory and clocking
•
Digital-to-analog conversion
•
Filtering
•
Scaling and level shifting
Figure 70. Generic Waveform Generation—Courtesy of Soft Test, Inc.
Gain
Adjust
Full Scale
Reference
DC Offset
–
+
Modulation
D/A Converter
–
+
Continuous Time
Purifying Filters
Waveform
Data Storage
Memory
Sample
Clock
194
Signal
Output
–
+
Differential
Output
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Waveform Generation
Analog Waveform Source Concepts
Waveform Memory and Clocking
The waveform data is stored in memory. In many cases it is frequency and amplitude
independent. The memory contains nothing more than a set of unitless magnitudes that
can be clocked at various speeds and amplified by certain amounts to get a variety of
waveforms with the same general shape.
Figure 71. Waveform Memory and Clocking
D/A Converter
Waveform
Data Storage
Memory
Sample
Clock
Digital-to-Analog Conversion
The memory data is clocked into the DAC, and an analog signal is produced. This signal
must be conditioned before sending it off to the DUT. It has a nominal amplitude based on
the internal specifications of the DAC. In addition, it maintains a zero-order hold, it keeps
one analog value steady until the succeeding clock cycle.
The DACs in waveform generators may have various speeds and resolutions, depending
on the target application. For example, audio requires low bandwidth but high resolution,
while video requires high-speed but low resolution. The Diamond Series MultiWave can
addresses both ends of the target applications with its dual path architecture.
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Output Filtering
Because the AWG DAC output is stepped, a reconstruction filter is often added to the
output. This filter smooths the steps from the waveform.
Figure 72. AWG Reconstruction Filter
0.5
y( n)
w( n)
− 0.5
0
0.01
n
Reconstruction
Filter
Ft
Fs
An effect known as sin(x)/x distortion can lessen the signal output power. Some AWGs
have a special sin(x)/x filter on the output. Others such as the MultiWave use a high
sampling ratio (many samples per cycle) to minimize this effect.
High resolution AWGs often have a bandpass filter to further clean up the output signal.
Figure 73. AWG Bandpass Filter
1.298
y( n )
1.5
1.5
1.5
1
1
0.5
0.5
0
y( n )
0.5
0.5
1
− 1.236 1.5
0
1
0
200
400
0
600
n
800
1000
999
− 1.5 1.5
0
0
200
400
600
n
800
1000
999
Purifying Filter
Ft
Scaling and Level Shifting
The signal is amplified to its desired output value. In addition, any required DC offset is
added.
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Waveform Generation
ADCs Description
There are several prevalent designs for ADCs, mostly trading off resolution and speed.
Sigma-delta converters are becoming the dominant architecture for lower speed
applications because of their low cost.
For high-speed applications, flash (or derivatives of the flash design) are the most
popular.
Figure 74. Speed Versus Resolution in Modern ADCs
Sigma-Delta
Resolution
SAR
Subranging
Flash
Bandwidth
Typical ADC Tests
An ADC is a device whose input is an analog signal. The tests performed on this device
might also be done on other types of analog ICs. These tests fall into one of two
categories:
•
Static tests
•
Dynamic tests
Both tests are important and indicate how well the device performs its intended
application. Certain applications may value one test type over another, both for technical
and cost considerations.
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Static Tests
Static testing of an ADC is more complicated than static DAC testing. For one thing, the
unknown quantity to find is an input value, not an output. In addition, the nature of analog
inputs suggests that this input value is not a single value, but a range of values that varies
due to noise. There are four basic linearity measures:
•
Gain
•
Offset
•
Integral non-linearity
•
Differential non-linearity
The typical technique for ADC static testing is the histogram technique. Linearity tests are
detailed later in this chapter.
Digital Output 0x00-0xFF
Figure 75. ADC Transfer Function
Analog Input 0-5 V
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Waveform Generation
Dynamic Tests
Dynamic tests look at the operation of the device under conditions that more closely
approximate the application. For most ADCs the signal sent into the device is a sine
wave. The most common dynamic tests are:
•
Signal-to-Noise Ratio (SNR)
•
Signal-to-Distortion (SDR)—Sometimes referred to as Total Harmonic Distortion
(THD).
•
Signal-to-Noise and Distortion (SNDR)—Sometimes referred to as Signal-to-Noise
and Distortion (SINAD).
The captured data for these tests is usually processed using frequency domain analysis,
utilizing a Fast Fourier Transform (FFT).
Figure 76. Dynamic Testing and Frequency Domain Analysis
Distorted Sine Signal
1
0
0.002
0.004
0.006
0.008
-1
Distorted Sine Signal viewed in the Frequency Domain
1
1000Hz
2000Hz
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ADC Testing Using an Analog Source
Linearity
There are several good texts covering the details of ADC static testing. This chapter
shows the typical calculations for these tests and the terminology used.
ADC Static Terminology
Figure 77. Transition Voltages
Transition Voltages
VT1
VT2
VT3
Figure 78. Code Width
Code Widths
VT1
200
VT2
VT3
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ADC Testing Using an Analog Source
Figure 79. Full Scale Transition Range and LSB Size
Example:
VZST = 28 mV
VFST = 5.01 V
FSTR = 4.982 V
FSTR
•
•
Same as average code width
Divide FSTR by (2 bits – 2)
(2 bits – 2) steps
Example:
FSTR = 4.982 V
# Bits = 10
LSBDUT = 4.875 mV
FSTR
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Full scale range (FSR) of an ADC is somewhat ambiguous since the device outputs a
valid code even if stimulated with a voltage outside of its range.
Figure 80. Full Scale Range
FSTR
FSR
Example:
FSTR = 4.982 V
# Bits = 10
LSBDUT = 4.875 mV
FSR = 4.982 + 2(0.004875 ) = 4.9917 V
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Figure 81. Offset and Gain Error Voltages
Ideal Zero
VZST
VZST -½ LSB
Example:
VZST = 28 mV
LSBDUT = 4.875 mV
Offset = 28 mv – ½(4.875 mV) = 25.5625 mV
FSTR
FSR
Example:
FSTR = 4.982 V
# Bits = 10
LSBDUT = 4.875 mV
FSRDUT = 4.982 + 2(0.004875 ) = 4.9917 V
FSRIDEAL = 5.0 V
Gain Error Voltage = 4.9917 V – 5.0 V = -8.3 mV
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Differential non-linearity (DNL) is a measure of the relative error in code widths
throughout the device. A missing code has a DNL of -1.
Figure 82. DNL and No Missing Codes
FF
FF
Missing Code
Code Width n
Code Width n + 1
CW Too Wide
00
00
Analog Vin
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Integral Non-Linearity
The Integral Non-Linearity (INL) test measures absolute deviation of the transfer function
from the ideal. The generally accepted method measures the deviation of the center of
code from its ideal position.
DNL i + DNL i – 1
INL i = INL i – 1 + --------------------------------------2
Another method uses the summation of DNL errors:
INL i = ΣDNL i
Figure 83. INL of an ADC
5.1
Actual Code
Centers
Y (Code)
Ideal Code
Centers
Z (Code)
-0.1
0
Code
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Histograms
The most common method for accomplishing linearity measurements in ADCs is to use
the histogram method. Instead of needing to know all of the specific transition voltages,
use a ramp made up of very small input steps, and count how many times each code
occurs (known as hits per code).
Figure 84. Histograms
8
Ideal Histogram
Hits Per Code
6
4
2
0
0
3
8
6
9
Code
12
15
12
15
Actual Histogram
Hits Per Code
6
4
2
0
0
3
6
9
Code
The DSP Library contains a complete set of functions for both ramp histograms and sine
histograms.
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Dynamic Tests
The dynamic tests for an ADC are very similar to those for a DAC, and use the same
calculations (shown below).
Signal-to-Noise Ratio:
⎛
⎞
⎜
⎟
⎜
⎟
⎜
⎟
Magnitude Ft
20 log ⎜ ---------------------------------------------------------⎟
⎜ ( Fs ) ⁄ 2
⎟
⎜
2⎟
( Magni tude Noise ) ⎟
⎜
⎝
⎠
∑
0
Signal-to-Distortion Ratio:
⎛
⎞
⎜
⎟
⎜
⎟
⎜
⎟
⎜
⎟
Magnitude Ft
20 log ⎜ ----------------------------------------------------------------------⎟
⎜ Fs
⎟
-----⎜ 2
⎟
⎜
2⎟
(
Magnitude
)
Harmonics ⎟
⎜
⎝
⎠
∑
0
Signal-to-Noise-and-Distortion Ratio:
⎛
⎞
⎜
⎟
⎜
⎟
⎜
⎟
⎜
⎟
Magnitude Ft
20 log ⎜ ------------------------------------------------------------------------------------⎟
F
⎜ -----s
⎟
⎜ 2
⎟
⎜
2⎟
( Magnitude Noise + Distortion ) ⎟
⎜
⎝
⎠
∑
0
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AWG Example Code Implementation
The following code example shows several of the AWG APIs in use.
Load the awav file:
DspWaveform *awgDspWave = new DspWaveform();
awgDspWave->readAwavFile("./waves/diffGainAWG.awav");
CSCMultiWaveArbitraryWave
awgWave("awg_diffGain");
Setup of the AWG waveform:
awgWave.setDspWaveform(awgDspWave);
awgWave.setPath(HIGH_FREQUENCY);
awgWave.setIncrement(1);
awgWave.setLoop(LOOP_FOREVER);
awgWave.setAmplitude( 1.0 V);
Load AWG memory:
cscTester->MultiWave()->Signal("Gen_1")->Memory()
->loadWaveform(&awgWave);
Sample clock setup
double fsample = (4.43e6/46.0)* 1024.0;
long divider = (long)(3.85e9/fsample);
fsample *= divider;
DDS selection and divider per channel
cscTester->MultiWave()->Signal(signal)->Clock()
->setClock(CLOCK_1,fsample, divider, true);
cscTester->MultiWave()->Signal(signal)->OutputCtrl()
->setHfClock(true);
AWG setup
cscTester->MultiWave()->Signal(signal)->ConnectionCtrl()
->connect(SIGNAL_PATH_HF,MUX_DIFFERENTIAL);
cscTester->MultiWave()->Signal(signal)->OutputCtrl()
->setHfFilter(F_12_MHZ); // BYPASS F_1P2_MHZ
cscTester->MultiWave()->Signal(signal)->OutputCtrl()
->setHfRange(1.0 V);
Turn On AWG
cscTester->MultiWave()->Signal(signal)->ArmCtrl()
->armAWG(&awgWave);
cscTester->MultiWave()->Signal(signal)->OutputCtrl()->start();
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Waveform Generation Using Internal Sinewave
The MultiWave has an internal sinewave with 1024 points defined. By setting the clock
and the increment properly virtually any frequency can be created without a awav file.
Example:
CSCMultiWaveSineWave sinWave("sin_wave");
sinWave.setPath(LOW_FREQUENCY);
sinWave.setIncrement(bin);
sinWave.setLoop(LOOP_FOREVER);
sinWave.setAmplitude( 1.0 V);
//you can change the frequency Ft by changing the bin (M/N=Ft/Fs)and
keeping others unchanged
//sinWave.setIncrement(bin+3);
//sinWave.setIncrement(bin+6);
//sinWave.setIncrement(bin+9);
Waveform Generation Using the rampWave
MultiWave has a ramp generator that can be used to generate ramp signals on-the-fly.
Example:
CSCMultiWaveRampWave rampWave("lf_ramp");
rampWave.setPath(HIGH_FREQUENCY);
rampWave.setMax(5.0);
rampWave.setMin(0.0);
rampWave.setLoop(LOOP_FOREVER);
rampWave.setSlewRatePositive(10.0);
rampWave.setSlewRateNegative(5);
rampWave.setStartDirection(CSCMultiWaveRampWave::DIRECTION_POSITIVE);
rampWave.setStartOffset(0);
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Trigger Implementation to Start AWG
The trigger implementation on Diamond Series allows the user to decide when to start
and stop the AWG and/or when to step AWG.
This flexibility is given by defining up to 8 routes made of source and destinations.
These routes include:
•
A route from digital world to address a typical AWG triggered start—Most of the mixed
signal devices need a digital sequence to setup the mode and access to the analog
cells so some samples will be taken without a need for them
•
A route from digital world to analog—To sample by step (case of ramp on a serial
DAC for example).
Trigger from DPIN triggers AWG start as shown in Figure 85.
Figure 85. Start AWG in Continuous Mode on Rising Edge
Trigger
Effective sampling
Converter clock
//Event routing to the backplane
//create new trigger
cscTester->EventRouting()->
createRoute("my_route1",REGISTERED,DISALLOW_LOCAL);
//add source
cscTester->EventRouting()->Route("my_route1")->
setSource("trigger",EVTTYPE_DPIN96_COMP_HI);
//add destination-start awg
cscTester->EventRouting()->Route("my_route1")->
addDestination(awgCh,EVTTYPE_MW_AWG_START);
//apply route
cscTester->EventRouting()->apply();
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//mode start awg per trigger-1 trigger only needed cpp must control arm
cscTester->MultiWave()->Signal(awgCh)->OutputCtrl()->
selectStartInput(TQ_RISING_EDGE_BP);
Every trigger pulse from DPIN generates a single sample as shown in Figure 86.
Figure 86. Start AWG in Step Mode on Rising Edge
Trigger
Effective sampling
Converter clock
//Event routing to the backplane
//create new trigger
cscTester->EventRouting()->
createRoute("my_route2",REGISTERED,DISALLOW_LOCAL);
//add source
cscTester->EventRouting()->Route("my_route2")->
setSource("trigger",EVTTYPE_DPIN96_COMP_HI);
//add destination-start awg
cscTester->EventRouting()->Route("my_route2")->
addDestination(awgCh,EVTTYPE_MW_AWG_TRIG);
//appply route
cscTester->EventRouting()->apply();
//mode single sample per trigger-1trigger needed per sample cpp must arm
and start
cscTester->MultiWave()->Signal(awgCh)->OutputCtrl()->
selectStartInput(TQ_SOFTWARE);
cscTester->MultiWave()->Signal(awgCh)->OutputCtrl()->
selectStepTrigger(TQ_RISING_EDGE_BP);
Note — When done using the triggers deselect them using the following commands:
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cscTester->MultiWave()->Signal(awgCh)->OutputCtrl()->
selectStartInput(TQ_SOFTWARE);
cscTester->MultiWave()->Signal(awgCh)->OutputCtrl()->
selectStepTrigger(TQ_DISABLE);
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Knowledge Check
1. What is the filter placed at the end of the conversion chain of an AWG called?
2. What type of ADC allows the fastest sampling among SAR, Flash, and sigma-delta?
3. Which API statement is used to start the AWG from a trigger backplane rising edge?
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Lab Exercise
Dynamic ADC Test Lab
In this lab, students will sample a sinewave with a ADC.
Note — Pattern is running at 900 ns period, 24 periods to acquire a sample so Fs = 1 /
(900e-9 * 24) = 49.296 kHz; Ft = Fsdig * M/1024 around 1 kHz so Mdig = 23 and effective
Ft = 1.0398582 kHz.
On the analog side the user will need to generate a 1.0398582 kHz wave with 1024
samples. They have to solve the equation Ft = Mana/1024*Fsana = Mdig/1024*Fsdig
So Mana * Fsana = Mdig * Fsdig -> Mdig = 23 and Fsdig is fixed.
For ease, choose the Fsana equal to Fsdig so Mana = Mdig = 23.
1. Add the DynamicADCTest function doing a 1 kHz signal on AWG LF and digitizing the
waveform at 900 ns period on the digital side.
a. Setup levels on Vref, Vss, and Vdd for MAX195 using:
setup_levels_ADCsetup_levels_ADC("MAX195_VDD",5.0,"MAX195_VSS",5.0,"MAX195_VREF_alt",cscExec->Spec("ADC_spec")>Category("ADC_cat_1k")->getExprValue("range_src",SPEC_TYP))
b. Set up the AWG to source 1 kHz with a Fs of 49.296 kHz on Low Frequency mode
(use the internal sinewave for it) by referring to period_spec equation:
•
CSCMultiWaveSineWave awgWave("lf_src");
•
AwgSineWaveSetup(awgCh,awgWave,LOW_FREQUENCY,23,LOOP_FOREV
ER,range_src/2*0.98,0.0); //98% fullscale
c. Set up AWG with lowpass F_1P4_KHz as filter, the source range can be as large
as Vref of the ADC:
AwgSetup(awgCh,SIGNAL_PATH_LF,F_1P4_KHZ,range_src/2,range_src/2)
d. Connect AWG using:
AwgDigConnect(awgCh,SIGNAL_PATH_LF,MUX_SINGLE_P)
Note — Refer to Appendix A, "Devices Data Sheets," on page 231 for the MAX195
datasheet. The setup is unipolar so range_src and offset_src have to be the same so
waveform is positive only
e. Route the trigger pin as source and the AWG as destination in start mode:
EventRouting_digital2awg("trigger",awgCh,"CONT")
f.
startAwg(awgCh,awgWave)
g. Enable DCM on pin MAX195_DOUT from ADCPat.label1 to ADCPat.label2.
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Trigger Implementation to Start AWG
h. Execute ADCdynLevelsExec patternExec and the pattern with statements:
cscTester->seq()->setStartAddress and cscTester->Seq()->start()
2. Count the number of captured data.
3. Retrieve the data and save as awav.
4. Reorder data knowing that 24 bits are retrieved and only bits 8 to 24 are in use and
LSB is coming out first.
5. Process amplitude, SNR, and THD with ratioMeas DSP function.
6. Test results.
Sample code below for Steps 2. through 6.
CSC_SERIAL_BLOCK_BEGIN
int sitenum = *cscIter, i, j
unsigned long int myData[numcapt];
cscTester->DCM()
->getCapturedDataBySite(sitenum,"MAX195_DOUT",0,numcapt,myData,DCM_HW);
double data[numcapt];
vector<double> my_data_double;
for(i=0;i<numcapt/24;i++)
data[i]=0.0;
for (i=0;i<numcapt;i+=24) {
for (j=8;j<24;j++) {
data[i/24] += myData[i+j] * pow(2.0,double(23-j));
}
}
for (i=0;i<numcapt/24;i++) {
my_data_double.push_back((double)data[i]);
}
for (i=0;i<numcapt/24;i++) {
my_data_double.push_back((double)data[i]);
}
DspWaveform *dspData
=
new DspWaveform(DspWaveform::wftRRect,"myWave",my_data_double,NULL);
char my_char[256];
sprintf(my_char,"./waves/ADC_capture_static_site%d.awav",sitenum);
dspData->writeAwavFile(my_char,true);
//DSP processing
double snr,thd,sinad,magn,fund,spur,maxSpur;
dspData->ratiosMeas( 5,NULL,&snr,&thd,&sinad,&magn,NULL);
//use test_var function to evaluate the results
test_var("Ampl ADC", 30000, 33000 ,magn, "", 200);
test_var("SNR", 60.00, 110.00 ,snr, "dB", 201);
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
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12 – ADC Tests Using MultiWave AWG
test_var("THD", 80.00, 110.00 ,thd, "dB", 202);
CSC_SERIAL_BLOCK_END
7. Stop AWG, disconnect, disable DCM memory, and clean trigger routes.
8. Power down device.
9. Compile, run, and debug test.
Hint — For debug different tools can be used such as STIL Tool (or Visualize) to change
the timing/levels and Pattern Tool to re-execute the sequence.
Static ADC Test
This lab creates typical ADC test using MultiWave as AWG, the DCM hardware and the
DSP library available in static (linearity tests)
1. Add a function called StaticADCTest doing a ramp 0 to Vref on AWG LF and digitizing
the waveform at 900 ns period on the digital side.
a. Setup levels on Vref, Vss, and Vdd for MAX195 using setup_levels_ADC
function.
b. Set up the AWG clock to a given frequency (choose the STIL equation
ADC_spec->ADC_cat_1k->Fs).
c. Set up AWG with BYPASS as filter, the source range can be as large as Vref of
the ADC (use STIL equation ADC_spec->ADC_cat_1k->range_src).
d. Connect AWG using AwgDigConnect function.
e. Route the trigger pin as source and the AWG as destination in step mode
EventRouting_digital2awg function.
f.
Start AWG.
g. Enable DCM on pin MAX195_DOUT from ADCStatPat.label1 to
ADCStatPat.label2.
h. Execute ADCStatLevelsExec patternExec and the pattern with statements
cscTester->seq()->setStartAddress and cscTester->Seq()->start().
2. Count the numbers of captured data.
3. Retrieve the data and save as awav.
4. Reorder data knowing that 24 bits are retrieved and only bits 8 to 24 are in use and
LSB is coming out first.
5. Save data as awav for further DSP processing.
6. Stop AWG, disable AWG step mode, disconnect, disable DCM memory, and clean
trigger routes.
7. Power down device.
8. Compile, run, and debug test.
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Trigger Implementation to Start AWG
Hint — For debug different tools can be used such as STIL tool (or visualize) to change
the timing/levels and Pattern Tool to re-execute the sequence.
Check Your Work
Review your answers and have the instructor sign off this module.
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
217
12 – ADC Tests Using MultiWave AWG
Notes
218
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13
Advanced Sampling
Goal
Understand advanced waveform capture techniques such as oversampling,
equivalent time sampling, and notch filtering.
Objectives
After completing this unit, students should be able to:
•
Learn about the oversampling on digitizer
•
Review the notch filter technique for testing audio devices
•
Understand the equivalent time sampling technique for high-speed applications
In This Module
______
______
______
Instructor Presentation
Lab
Knowledge Check
30
50
5
Minutes
Minutes
Minutes
Resources
Diamond Series Online Help
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
219
13 – Advanced Sampling
Advanced Waveform Capture Topics
Notch Filter for Audio Applications
To improve the fidelity of the SNR measurement, the signal can be measured through a
notch filter on the MultiWave digitizer.
The advantage of the notch filter is that it reduces the amplitude of a fixed frequency
(1 kHz on Multiwave) of a fixed aount (30 dB). This technique increases the effective
dynamic range of the instrument.
The magnitude of the signal’s fundamental needs to be measured with a normal filter first.
A second measurement is then made with the notch filter in the path to measure the noise
with an adapted range on the ADC.
The in-band noise spectrum is digitized by the MultiWave high-precision ADC, with the
signal fundamental notched out and the ADC’s voltage range zoomed-in to the amplitude
of the small-scale noise signal.
Figure 87. Spectrum With and Without Notch Filter
220
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Advanced Waveform Capture Topics
Oversampling
Video and baseband measurements achieve optimal fidelity using a built-in oversampling
technique. An anti-aliasing filter removes noise above the desired Nyquist frequency. The
signal is oversampled to reduce quantization noise. A 1/n decimator filters and
downsamples the data. The power meter calculates the magnitude of the fundamental.
The data is optionally sent to the processor for additional DSP
Lower resolution measurements do not require the oversampling technique.
Figure 88. Built-in Oversampling System
DUT
Signal In
LPF
HF
ADC
Decimator
Power
Meter
Digitized
Data Out
11011001
The oversampling technique provides a way to lower the theoretical noise floor and
improve the fidelity of the SNR measurement.
The signal-to-quantization noise ratio is:
SNRQ = 6.02n +1.76 dB
Where n = bits of resolution.
Figure 89. Signal to Noise Ratio Due to Quantization Error
Sampling
Q
u
a
n
t Quantized
i
z
Ideal
a
t
i
o
n
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
221
13 – Advanced Sampling
Quantization noise has a uniform distribution. It is spread evenly throughout the Nyquist
region. SNRQ is a constant amount based only on the number of bits in the ADC
converter.
Figure 90. NQ Distribution Versus Sampling Frequency
NQ
The area under
these curves is
constant: AFs/2
A
A/K
FS/2
KFS/2
f
The signal-to-quantization noise ratio is constant for a given ADC. The value at any one
frequency is reduced when the sampling frequency is increased, because the noise
energy is spread across more bins.
Figure 91. Using Oversampling to Reduce NQ
Mag
A
Atten
0
Fs/2
f
Mag
A
Fs /2
Quantization Noise
f
Fs/2
Digital LP Filter
f
Result
No Oversampling
Mag
Atten
0
Mag
A/K
Reduced
Noise
Magnitude
A/K
KFs/2 f
Quantization Noise
Fs/2
Digital LP Filter
f
Fs /2
f
Result
With Oversampling
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Advanced Waveform Capture Topics
Figure 92. Oversampling, Digital Filtering, and Decimation
DUT Signal In
LPF
HF
ADC
Analog
Anti-alias
Filter
Oversampling
ADC
Decimator
Power
Meter
Digital LP
Filter and
Down
Sampler
Magnitude
Measurement
of the
Fundamental
Digitized
Data Out
11011001
The signal of interest is in the baseband extending from 0 to FN/2 Hz. Oversampling is
normally done at integral multiples of the Nyquist rate, and usually a power of 2. Analog
anti-alias filtering prevents interference from noise above the baseband.
Figure 93. Oversampling Example
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
223
13 – Advanced Sampling
Decimation is done by low pass digital filtering the 4x oversampled signal and then
downsampling by 4. Downsampling by 4 means every 4th sample is retained. This
reduces the number of samples for later DSP calculations.
Figure 94. Decimation
Digital low pass filter
Atten
FN/2 FN
4
FOVS/2
f
FOVS
Downsampler
Baseband Signal
Mag
FN/2 FN
224
2FN
4FN
f
PN: 071-0961-00, January 2008
Equivalent Time Sampling or Undersampling
Equivalent Time Sampling or Undersampling
Equivalent time sampling (ETS) allows for capturing waveforms that have sampling
requirements above the maximum clock rate of the capture instrument, but still within the
bandwidth of the sampling circuit.
Consider a waveform with the following sampling parameters:
M = 71
N = 512
Ft = 14.992 MHz 1/Fs = 9.25 ns
Figure 95. A Waveform to Capture Using ETS
By concatenating several unit test periods (UTPs) together, it can be seen that each
desired sample point in the first UTP, has other equivalent, points in other UTPs.
Figure 96. Equivalent Points in Different UTPs
UTP #1
UTP #2
Equivalent Points
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
225
13 – Advanced Sampling
This is the key to undersampling, or equivalent time sampling. Sample once in each UTP
(or at any other cycle), and build a database of points that are the same as if captured in
real time (known as the reconstructed waveform).
Figure 97. One ETS Technique is to Skip an Entire UTP
UTP #n
Desired 1/Fs
UTP #n + 1
Actual Sample n + 1
Desired Sample n+1
Equivalent 1/Fs
Sample n
Figure 87 depicts equivalent time sampling by choosing various cycle-skipping
F ⋅F
Ft + k ⋅ Fs
t
s
algorithms. The general formula is: F sETS = -----------------------
Figure 98. Skip Only k Cycles
226
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Equivalent Time Sampling or Undersampling
Lab Exercise
Sampling Theory Lab
Suppose a waveform with the following sampling parameters:
•
Ft = 500 kHz
•
M = 21
•
N = 1024
•
Fs = 24.380952 MHz
Capturing this waveform using the LF path on the digitizer is a problem. Due to the fact
that Digitizer highest sample rate is 2.5 Msps. Since the digitizer LF Path has a high input
bandwidth use equivalent time sampling to achieve this waveform capture.
Method 1—Whole UTP Method
In this method the adjusted Fs is the desired Fs plus 1 UTP:
Calculate the adjusted Fs:____________________
Calculate the approximate capture time: ____________________
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
227
13 – Advanced Sampling
Method 2—Skip Minimum Cycles Method
F ⋅F
Ft + k ⋅ Fs
t
s
- where k is the
In the skip minimum cycles method use the formula F sETS = -----------------------
number of cycles to skip.
How many cycles must be skipped? _______________
Calculate the adjusted Fs:____________________
Calculate the approximate capture time: ____________________
Method 3—Minimum Sample Time Method
In the minimum sample time method capture at the digitizer full speed and use the
reorder function to obtain the original desired waveform.
Calculate the adjusted Fs:____________________
Calculate the approximate capture time: ____________________
How much time can the reorder function use in order to keep this as the most efficient
method for capture? _______________________
What Digitizer Mode should be selected for this particular set of sampling
parameters? __________
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Equivalent Time Sampling or Undersampling
Knowledge Check
1. Compare the SNR and SDR values using the Notch Filter to those without the filter.
Are they better or worse?
Why?
2. Why is the input bandwidth of the Digitizer so important when using equivalent time
sampling?
3. What happens if the Digitizer is triggered before the AWG output is stable?
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
229
13 – Advanced Sampling
Check Your Work
Review your answers and have the instructor sign off this module.
230
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A
Devices Data Sheets
LT1121 Data Sheet
LT1121/LT1121-3.3/LT1121-5
Micropower Low Dropout
Regulators with Shutdown
U
FEATURES
DESCRIPTIO
■
The LT®1121/LT1121-3.3/LT1121-5 are micropower low
dropout regulators with shutdown. These devices are
capable of supplying 150mA of output current with a
dropout voltage of 0.4V. Designed for use in batterypowered systems, the low quiescent current, 30RA operating and 16RA in shutdown, makes them an ideal choice.
The quiescent current is well-controlled; it does not rise in
dropout as it does with many other low dropout PNP
regulators.
■
■
■
■
■
■
■
■
■
■
■
■
■
0.4V Dropout Voltage
150mA Output Current
30RA Quiescent Current
No Protection Diodes Needed
Adjustable Output from 3.75V to 30V
3.3V and 5V Fixed Output Voltages
Controlled Quiescent Current in Dropout
Shutdown
16RA Quiescent Current in Shutdown
Stable with 0.33RF Output Capacitor
Reverse Battery Protection
No Reverse Current with Input Low
Thermal Limiting
Available in the 8-Lead SO, 8-Lead PDIP, 3-Lead
SOT-23 and 3-Lead TO-92 Packages
U
APPLICATIO S
■
■
■
Low Current Regulator
Regulator for Battery-Powered Systems
Post Regulator for Switching Supplies
Other features of the LT1121/LT1121-3.3/LT1121-5 include the ability to operate with very small output capacitors. They are stable with only 0.33RF on the output while
most older devices require between 1RF and 100RF for
stability. Small ceramic capacitors can be used, enhancing
manufacturability. Also the input may be connected to
ground or a reverse voltage without reverse current flow
from output to input. This makes the LT1121 series ideal
for backup power situations where the output is held high
and the input is at ground or reversed. Under these
conditions only 16RA will flow from the output pin to
ground.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
U
TYPICAL APPLICATIO
5V Battery-Powered Supply with Shutdown
Dropout Voltage
0.5
IN
OUT
1
LT1121-3.3
5V
5
3.3VOUT
150mA
+
SHDN
GND
3
VSHDN (PIN 5) OUTPUT
<0.25
OFF
>2.8
ON
NC
ON
0.4
1RF
SOLID TANTALUM
DROPOUT VOLTAGE (V)
8
0.3
0.2
0.1
LT1121 • TA01
0
0
20
40 60 80 100 120 140 160
OUTPUT CURRENT (mA)
LT1121 • TA02
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A – Devices Data Sheets
LT1121/LT1121-3.3/LT1121-5
W W
W
AXI U
U
ABSOLUTE
RATI GS (Note 1)
Input Voltage
LT1121 ............................................................. ±30V
LT1121HV ............................................. +36V, – 30V
Output Pin Reverse Current ................................. 10mA
Adjust Pin Current ............................................... 10mA
Shutdown Pin Input Voltage (Note 2) ........ 6.5V, – 0.6V
Shutdown Pin Input Current (Note 2) .................. 20mA
Output Short-Circuit Duration ......................... Indefinite
Operating Junction Temperature Range (Note 3)
LT1121C-X ........................................... 0°C to 125°C
LT1121I-X ....................................... – 40°C to 125°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
W
U
U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
OUT 1
8 IN
NC/ADJ* 2
7 NC**
GND 3
6 NC**
NC 4
5 SHDN
N8 PACKAGE
8-LEAD PDIP
S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 150°C, VJA ~ 120°C/ W (N8, S8)
TJMAX = 150°C, VJA ~ 70°C/ W (AS8)
* PIN 2 = NC FOR LT1121-3.3/LT1121-5
= ADJ FOR LT1121
** PINS 6 AND 7 ARE FLOATING (NO
INTERNAL CONNECTION) ON THE
STANDARD S8 PACKAGE.
PINS 6 AND 7 CONNECTED TO GROUND
ON THE A VERSION OF THE LT1121 (S8 ONLY).
CONNECTING PINS 6 AND 7 TO THE
GROUND PLANE WILL REDUCE THERMAL
RESISTANCE. SEE THERMAL RESISTANCE
TABLES IN THE APPLICATIONS INFORMATION
SECTION.
ORDER PART NUMBER
LT1121CN8
LT1121CN8-3.3
LT1121CN8-5
LT1121IN8
LT1121IN8-3.3
LT1121IN8-5
LT1121CS8
LT1121CS8-3.3
LT1121CS8-5
LT1121HVCS8
LT1121IS8
LT1121IS8-3.3
LT1121IS8-5
LT1121HVIS8
LT1121ACS8
LT1121ACS8-3.3
LT1121ACS8-5
LT1121AHVCS8
LT1121AIS8
LT1121AIS8-3.3
LT1121AIS8-5
LT1121AHVIS8
BOTTOM VIEW
FRONT VIEW
TAB IS
GND
3
OUTPUT
2
GND
1
VIN
IN
GND
OUT
ST PACKAGE
3-LEAD PLASTIC SOT-223
Z PACKAGE
3-LEAD PLASTIC TO-92
TJMAX = 150°C, VJA ~ 50°C/ W
TJMAX = 150°C, VJA ~ 150°C/ W
S8 PART
MARKING
ORDER PART
NUMBER
ST PART
MARKING
ORDER PART
NUMBER
121I3
121I5
121HVI
1121A
121A3
121A5
1121
121AHV
11213 121AI
11215 121AI3
1121HV 121AI5
1121I
21AHVI
LT1121CST-3.3
LT1121IST-3.3
LT1121CST-5
LT1121IST-5
11213
121IS3
11215
1121I5
LT1121CZ-3.3
LT121IZ-3.3
LT1121CZ-5
LT1121IZ-5
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
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LT1121/LT1121-3.3/LT1121-5
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the operating temperature
range, otherwise specifications are at TA = 25°C.
PARAMETER
CONDITIONS
Regulated Output Voltage
(Note 4)
LT1121-3.3
LT1121-5
LT1121 (Note 5)
Line Regulation
Load Regulation
TYP
MAX
UNITS
●
3.300
3.300
3.350
3.400
V
V
VIN = 5.5V, IOUT = 1mA, TJ = 25°C
6V < VIN < 20V, 1mA < IOUT < 150mA
●
4.925
4.850
5.000
5.000
5.075
5.150
V
V
VIN = 4.3V, IOUT = 1mA, TJ = 25°C
4.8V < VIN < 20V, 1mA < IOUT < 150mA
●
3.695
3.640
3.750
3.750
3.805
3.860
V
V
LT1121-3.3
)VIN = 4.8V to 20V, IOUT = 1mA
●
1.5
10
mV
LT1121-5
)VIN = 5.5V to 20V, IOUT = 1mA
●
1.5
10
mV
LT1121 (Note 5)
)VIN = 4.3V to 20V, IOUT = 1mA
●
1.5
10
mV
LT1121-3.3
)ILOAD = 1mA to 150mA, TJ = 25°C
)ILOAD = 1mA to 150mA
●
– 12
– 20
– 25
– 40
mV
mV
)ILOAD = 1mA to 150mA, TJ = 25°C
)ILOAD = 1mA to 150mA
●
– 17
– 28
– 35
– 50
mV
mV
)ILOAD = 1mA to 150mA, TJ = 25°C
)ILOAD = 1mA to 150mA
●
– 12
– 18
– 25
– 40
mV
mV
0.13
0.16
0.25
V
V
0.30
0.35
0.50
V
V
0.37
0.45
0.60
V
V
0.42
0.55
0.70
V
V
RA
LT1121-5
LT1121 (Note 5)
Dropout Voltage
(Note 6)
MIN
3.250
3.200
VIN = 3.8V, IOUT = 1mA, TJ = 25°C
4.3V < VIN < 20V, 1mA < IOUT < 150mA
ILOAD = 1mA, TJ = 25°C
ILOAD = 1mA
●
ILOAD = 50mA, TJ = 25°C
ILOAD = 50mA
●
ILOAD = 100mA, TJ = 25°C
ILOAD = 100mA
●
ILOAD = 150mA, TJ = 25°C
ILOAD = 150mA
●
Ground Pin Current
ILOAD = 0mA
●
30
50
(Note 7)
ILOAD = 1mA
●
90
120
RA
ILOAD = 10mA
●
350
500
RA
ILOAD = 50mA
●
1.5
2.5
mA
ILOAD = 100mA
●
4.0
7.0
mA
ILOAD = 150mA
●
7.0
14.0
mA
150
300
nA
1.2
0.75
2.8
V
V
Adjust Pin Bias Current (Notes 5, 8)
TJ = 25°C
Shutdown Threshold
VOUT = Off to On
VOUT = On to Off
●
●
Shutdown Pin Current (Note 9)
VSHDN = 0V
●
6
10
RA
Quiescent Current in Shutdown (Note 10)
VIN = 6V, VSHDN = 0V
●
16
22
RA
Ripple Rejection
VIN – VOUT = 1V (Avg), VRIPPLE = 0.5VP-P,
fRIPPLE = 120Hz, ILOAD = 0.1A
Current Limit
VIN – VOUT = 7V, TJ = 25°C
Input Reverse Leakage Current
VIN = –20V, VOUT = 0V
Reverse Output Current (Note 11)
LT1121-3.3
LT1121-5
LT1121 (Note 5)
50
58
200
●
VOUT = 3.3V, VIN = 0V
VOUT = 5V, VIN = 0V
VOUT = 3.8V, VIN = 0V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
0.25
16
16
16
dB
500
mA
1.0
mA
25
25
25
RA
RA
RA
Note 2: The shutdown pin input voltage rating is required for a low
impedance source. Internal protection devices connected to the shutdown
pin will turn on and clamp the pin to approximately 7V or – 0.6V. This
range allows the use of 5V logic devices to drive the pin directly. For high
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A – Devices Data Sheets
LT1121/LT1121-3.3/LT1121-5
ELECTRICAL CHARACTERISTICS
impedance sources or logic running on supply voltages greater than 5.5V,
the maximum current driven into the shutdown pin must be limited to less
than 20mA.
Note 3: For junction temperatures greater than 110°C, a minimum load of
1mA is recommended. For TJ > 110°C and IOUT < 1mA, output voltage
may increase by 1%.
Note 4: Operating conditions are limited by maximum junction
temperature. The regulated output voltage specification will not apply for
all possible combinations of input voltage and output current. When
operating at maximum input voltage, the output current range must be
limited. When operating at maximum output current the input voltage
range must be limited.
Note 5: The LT1121 (adjustable version) is tested and specified with the
adjust pin connected to the output pin.
Note 6: Dropout voltage is the minimum input/output voltage required to
maintain regulation at the specified output current. In dropout the output
voltage will be equal to: (VIN – VDROPOUT).
Note 7: Ground pin current is tested with VIN = VOUT (nominal) and a
current source load. This means that the device is tested while operating in
its dropout region. This is the worst case ground pin current. The ground
pin current will decrease slightly at higher input voltages.
Note 8: Adjust pin bias current flows into the adjust pin.
Note 9: Shutdown pin current at VSHDN = 0V flows out of the shutdown pin.
Note 10: Quiescent current in shutdown is equal to the sum total of the
shutdown pin current (6RA) and the ground pin current (9RA).
Note 11: Reverse output current is tested with the input pin grounded and
the output pin forced to the rated output voltage. This current flows into
the output pin and out of the ground pin.
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Guaranteed Dropout Voltage
0.6
0.6
50
ILOAD = 150mA
DROPOUT VOLTAGE (V)
0.5
0.4
TJ f 25°C
0.3
0.2
0.1
QUIESCENT CURRENT (RA)
0.7
TJ f 125°C
DROPOUT VOLTAGE (V)
Quiescent Current
Dropout Voltage
0.7
ILLOAD = 100mA
0.5
0.4
0.3
ILOAD = 50mA
0.2
ILOAD = 1mA
VIN = 6V
RLOAD = h
40
VSHDN = OPEN
30
20
VSHDN = 0V
10
0.1
= TEST POINTS
0
0
0
–50
40 60 80 100 120 140 160
OUTPUT CURRENT (mA)
20
50
25
0
75
TEMPERATURE (°C)
–25
100
1121 G27
120
TJ = 25°C
RLOAD = h
VSHDN = OPEN
60
40
20
80
VSHDN = OPEN
60
40
20
VSHDN = 0V
0
1
2
3 4 5 6 7
INPUT VOLTAGE (V)
8
9
10
1121 G04
80
VSHDN = OPEN
60
40
20
VSHDN = 0V
0
0
TJ = 25°C
RLOAD = h
VOUT = VADJ
100
QUIESCENT CURRENT (RA)
100
QUIESCENT CURRENT (RA)
100
125
LT1121
Quiescent Current
120
TJ = 25°C
RLOAD = h
80
100
1121 G11
LT1121-5
Quiescent Current
120
50
0
75
25
TEMPERATURE (°C)
1121 G14
LT1121-3.3
Quiescent Current
QUIESCENT CURRENT (RA)
0
–50 –25
125
VSHDN = 0V
0
0
1
2
3 4 5 6 7
INPUT VOLTAGE (V)
8
9
10
1121 G02
0
1
2
3 4 5 6 7
INPUT VOLTAGE (V)
8
9
10
1121 G03
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LT1121-3.3
Output Voltage
LT1121-5
Output Voltage
3.83
5.08
3.38
IOUT = 1mA
IOUT = 1mA
5.06
3.81
3.34
5.04
3.79
3.32
3.30
3.28
3.26
3.24
50
25
0
75
TEMPERATURE (°C)
–25
100
5.02
5.00
4.98
3.69
50
0
75
25
TEMPERATURE (°C)
–25
100
800
TJ = 25°C
GROUND PIN CURRENT (RA)
800
RLOAD = 330<
ILOAD = 10mA*
300
*FOR VOUT = 3.3V
200
RLOAD = 3.3k
ILOAD = 1mA*
100
600
500
RLOAD = 500<
ILOAD = 10mA*
400
300
*FOR VOUT = 5V
200
RLOAD = 5k
ILOAD = 1mA*
100
0
1
2
3 4 5 6 7
INPUT VOLTAGE (V)
8
9
1
2
3 4 5 6 7
INPUT VOLTAGE (V)
8
1121 G10
10
TJ = 25°C
RLOAD = 33<
ILOAD = 100mA*
4
3
RLOAD = 66<
ILOAD = 50mA*
2
1
1
2
300
*FOR VOUT = 3.75V
200
3 4 5 6 7
INPUT VOLTAGE (V)
9
10
1121 G09
1
2
3 4 5 6 7
INPUT VOLTAGE (V)
8
1121 G08
TJ = 25°C
9 VOUT = VADJ
6
RLOAD = 50<
ILOAD = 100mA*
5
4
3
RLOAD = 100<
ILOAD = 50mA*
2
1
2
3 4 5 6 7
INPUT VOLTAGE (V)
8
RLOAD = 25<
ILOAD = 150mA*
7
6
5
RLOAD = 38<
ILOAD = 100mA*
4
3
RLOAD = 75<
ILOAD = 50mA*
2
1
*FOR VOUT = 5V
0
10
10
RLOAD = 33<
ILOAD = 150mA*
7
9
LT1121
Ground Pin Current
8
0
8
RLOAD = 3.8k
ILOAD = 1mA*
0
10
TJ = 25°C
1
*FOR VOUT = 3.3V
0
GROUND PIN CURRENT (mA)
GROUND PIN CURRENT (mA)
6
5
9
9
RLOAD = 22<
ILOAD = 150mA*
7
RLOAD = 380<
ILOAD = 10mA*
400
LT1121-5
Ground Pin Current
9
8
500
1121 G06
LT1121-3.3
Ground Pin Current
10
600
0
0
10
RLOAD = 150<
ILOAD = 25mA*
100
0
0
0
TJ = 25°C
700 VOUT = VADJ
RLOAD = 200<
ILOAD = 25mA*
GROUND PIN CURRENT (mA)
GROUND PIN CURRENT (RA)
500
125
100
LT1121
Ground Pin Current
TJ = 25°C
700
RLOAD = 130<
ILOAD = 25mA*
50
25
0
75
TEMPERATURE (°C)
–25
1121 G24
LT1121-5
Ground Pin Current
700
400
3.67
–50
125
1121 G23
LT1121-3.3
Ground Pin Current
600
3.73
4.94
1121 G22
800
3.75
3.71
4.92
–50
125
IOUT = 1mA
3.77
4.96
GROUND PIN CURRENT (RA)
3.22
–50
ADJ PIN VOLTAGE (V)
3.36
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
LT1121
Adjust Pin Voltage
8
9
10
1121 G05
0
*FOR VOUT = 3.75V
0
1
2
3 4 5 6 7
INPUT VOLTAGE (V)
8
9
10
1121 G07
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LT1121/LT1121-3.3/LT1121-5
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TYPICAL PERFOR A CE CHARACTERISTICS
Shutdown Pin Threshold
(On-to-Off)
Ground Pin Current
2.0
VIN = 3.3V (LT1121-3.3)
VIN = 5V (LT1121-5)
12 V = 3.75V (LT1121)
IN
DEVICE IS OPERATING
10 IN DROPOUT
TJ = 25°C
6
TJ = –55°C
4
2
1.8
1.6
SHUTDOWN THRESHOLD (V)
TJ = 125°C
8
2.0
ILOAD = 1mA
1.8
SHUTDOWN THRESHOLD (V)
GROUND PIN CURRENT (mA)
14
Shutdown Pin Threshold
(Off-to-On)
1.4
1.2
1.0
0.8
0.6
0.4
0
20
0
–50
40 60 80 100 120 140 160
OUTPUT CURRENT (mA)
50
0
75
25
TEMPERATURE (°C)
–25
100
1121 G29
6
5
4
3
2
1
–25
50
25
0
75
TEMPERATURE (°C)
100
15
10
5
0
1
7
3
8
2
5
6
4
SHUTDOWN PIN VOLTAGE (V)
9
10
5
150
100
50
125
1121 G13
50
25
0
75
TEMPERATURE (°C)
100
125
400
350
VIN = 7V
350 VOUT = 0V
300
300
250
200
150
100
250
200
150
100
50
0
100
–25
1121 G25
VOUT = 0V
50
50
25
0
75
TEMPERATURE (°C)
200
Current Limit
CURRENT LIMIT (mA)
SHORT-CIRCUIT CURRENT (mA)
OUTPUT PIN CURRENT (RA)
400
15
125
250
1121 G28
30
100
300
Current Limit
20
50
0
75
25
TEMPERATURE (°C)
350
0
–50
0
125
VIN = 0V
VOUT = 5V (LT1121-5)
V
25 OUT = 3.3V (LT1121-3.3)
VOUT = 3.8V (LT1121)
–25
400
1121 G15
–25
0.4
LT1121
Adjust Pin Bias Current
20
Reverse Output Current
0
–50
0.6
1121 G17
ADJUST PIN BIAS CURRENT (nA)
7
0
–50
0.8
0
–50
125
25
VSHDN = 0V
8
ILOAD = 1mA
1.0
Shutdown Pin Input Current
SHUTDOWN PIN INPUT CURRENT (mA)
SHUTDOWN PIN CURRENT (RA)
9
1.2
1121 G16
Shutdown Pin Current
10
ILOAD = 150mA
1.4
0.2
0.2
0
1.6
0
1
4
2
5
3
INPUT VOLTAGE (V)
6
7
1121 G20
0
–50
–25
50
25
0
75
TEMPERATURE (°C)
100
125
1121 G19
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Reverse Output Current
Ripple Rejection
40
LT1121-3.3
30
60
58
56
54
52
LT1121-5
0
1
2
3 4 5 6 7 8
OUTPUT VOLTAGE (V)
9
50
40
30
0
–25
50
25
0
75
TEMPERATURE (°C)
COUT = 1RF
SOLID TANTALUM
)ILOAD = 1mA TO 150mA
OUTPUT VOLTAGE
DEVIATION (V)
–5
LT1121*
125
10
LT1121-3.3
–15
–20
100
1k
10k
FREQUENCY (Hz)
100k
1M
1121 G26
LT1121-5
Load Transient Response
Load Regulation
–10
100
1121 G18
1121 G01
0
60
10
50
–50
10
LT1121-5
Load Transient Response
VIN = 6V
0.2 CIN = 0.1RF
C
= 1RF
0.1 OUT
OUTPUT VOLTAGE
DEVIATION (V)
0
COUT = 47RF
SOLID TANTALUM
70
20
20
10
0
–0.1
–0.2
VIN = 6V
0.2 CIN = 0.1RF
COUT = 3.3RF
0.1
0
–0.1
–0.2
LT1121-5
–30
–35
* ADJ PIN TIED TO
OUTPUT PIN
–40
–50
–25
50
0
75
25
TEMPERATURE (°C)
100
125
1121 G21
LOAD CURRENT
(mA)
–25
LOAD CURRENT
(mA)
LOAD REGULATION (mV)
80
RIPPLE REJECTION (dB)
LT1121
(VOUT = VADJ)
50
IOUT = 100mA
90 VIN = 6V + 50mVRMS RIPPLE
VIN = VOUT (NOMINAL) + 1V
+ 0.5VP-P RIPPLE AT f = 120Hz
62
IOUT = 100mA
RIPPLE REJECTION (dB)
OUTPUT PIN CURRENT (RA)
TJ = 25°C
90 VIN = 0V
CURRENT FLOWS
80 INTO OUTPUT PIN
70
60
Ripple Rejection
100
64
100
150
100
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
TIME (ms)
1121 G30
150
100
50
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
TIME (ms)
1121 G31
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LT1121/LT1121-3.3/LT1121-5
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Input Pin: Power is supplied to the device through the
input pin. The input pin should be bypassed to ground if
the device is more than six inches away from the main
input filter capacitor. In general the output impedance of a
battery rises with frequency so it is usually adviseable to
include a bypass capacitor in battery-powered circuits. A
bypass capacitor in the range of 0.1RF to 1RF is sufficient.
The LT1121 is designed to withstand reverse voltages on
the input pin with respect to both ground and the output
pin. In the case of a reversed input, which can happen if a
battery is plugged in backwards, the LT1121 will act as if
there is a diode in series with its input. There will be no
reverse current flow into the LT1121 and no reverse
voltage will appear at the load. The device will protect both
itself and the load.
Output Pin: The output pin supplies power to the load. An
output capacitor is required to prevent oscillations. See
the Applications Information section for recommended
value of output capacitance and information on reverse
output characteristics.
Shutdown Pin: This pin is used to put the device into
shutdown. In shutdown the output of the device is turned
off. This pin is active low. The device will be shut down if
the shutdown pin is pulled low. The shutdown pin current
with the pin pulled to ground will be 6RA. The shutdown
pin is internally clamped to 7V and – 0.6V (one VBE). This
allows the shutdown pin to be driven directly by 5V logic
or by open collector logic with a pull-up resistor. The pullup resistor is only required to supply the leakage current
of the open collector gate, normally several microamperes. Pull-up current must be limited to a maximum of
20mA. A curve of shutdown pin input current as a function
of voltage appears in the Typical Performance Characteristics. If the shutdown pin is not used it can be left open
circuit. The device will be active, output on, if the shutdown
pin is not connected.
Adjust Pin: For the adjustable LT1121, the adjust pin is the
input to the error amplifier. This pin is internally clamped
to 6V and – 0.6V (one VBE). It has a bias current of 150nA
which flows into the pin. See Bias Current curve in the
Typical Performance Characteristics. The adjust pin reference voltage is 3.75V referenced to ground. The output
voltage range that can be produced by this device is 3.75V
to 30V.
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The LT1121 is a micropower low dropout regulator with
shutdown, capable of supplying up to 150mA of output
current at a dropout voltage of 0.4V. The device operates
with very low quiescent current (30RA). In shutdown the
quiescent current drops to only 16RA. In addition to the
low quiescent current the LT1121 incorporates several
protection features which make it ideal for use in batterypowered systems. The device is protected against both
reverse input voltages and reverse output voltages. In
battery backup applications where the output can be held
up by a backup battery when the input is pulled to ground,
the LT1121 acts like it has a diode in series with its output
and prevents reverse current flow.
Adjustable Operation
The adjustable device is specified with the adjust pin tied
to the output pin. This sets the output voltage to 3.75V.
Specifications for output voltage greater than 3.75V will be
proportional to the ratio of the desired output voltage to
3.75V (VOUT/3.75V). For example: load regulation for an
output current change of 1mA to 150mA is –12mV typical
at VOUT = 3.75V. At VOUT = 12V, load regulation would be:
(
) (
© 12V ¹
º • –12mV = –38mV
ª
« 3.75V »
)
Thermal Considerations
The adjustable version of the LT1121 has an output
voltage range of 3.75V to 30V. The output voltage is set by
the ratio of two external resistors as shown in Figure 1. The
device servos the output voltage to maintain the voltage at
the adjust pin at 3.75V. The current in R1 is then equal to
3.75V/R1. The current in R2 is equal to the sum of the
current in R1 and the adjust pin bias current. The adjust pin
bias current, 150nA at 25°C, flows through R2 into the
adjust pin. The output voltage can be calculated according
to the formula in Figure 1. The value of R1 should be less
than 400k to minimize errors in the output voltage caused
by the adjust pin bias current. Note that in shutdown the
output is turned off and the divider current will be zero.
Curves of Adjust Pin Voltage vs Temperature and Adjust
Pin Bias Current vs Temperature appear in the Typical
Performance Characteristics. The reference voltage at the
adjust pin has a slight positive temperature coefficient of
IN
VOUT
OUT
LT1121
R2
SHDN
ADJ
+
R1
GND
1121 • F01
(
approximately 15ppm/°C. The adjust pin bias current has
a negative temperature coefficient. These effects are small
and will tend to cancel each other.
)
(
)
VOUT = 3.75V 1 + R2 + IADJ • R2
R1
VADJ = 3.75V
IADJ = 150nA AT 25°C
OUTPUT RANGE = 3.75V TO 30V
Figure 1. Adjustable Operation
Power handling capability will be limited by maximum
rated junction temperature (125°C). Power dissipated by
the device will be made up of two components:
1. Output current multiplied by the input/output voltage
differential: IOUT • (VIN – VOUT), and
2. Ground pin current multiplied by the input voltage:
IGND • VIN.
The ground pin current can be found by examining the
Ground Pin Current curves in the Typical Performance
Characteristics. Power dissipation will be equal to the sum
of the two components listed above.
The LT1121 series regulators have internal thermal limiting designed to protect the device during overload conditions. For continuous normal load conditions the maximum junction temperature rating of 125°C must not be
exceeded. It is important to give careful consideration to
all sources of thermal resistance from junction to ambient.
Additional heat sources mounted nearby must also be
considered.
Heat sinking, for surface mount devices, is accomplished
by using the heat spreading capabilities of the PC board
and its copper traces. Copper board stiffeners and plated
through holes can also be used to spread the heat generated by power devices. Tables 1 through 5 list thermal
resistances for each package. Measured values of thermal
resistance for several different board sizes and copper
areas are listed for each package. All measurements were
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taken in still air, on 3/32" FR-4 board with 1oz copper. All
NC leads were connected to the ground plane.
Table 1. N8 Package*
COPPER AREA
TOPSIDE
BACKSIDE
THERMAL RESISTANCE
BOARD AREA (JUNCTION-TO-AMBIENT)
2500 sq mm
2500 sq. mm
2500 sq. mm
80°C/W
1000 sq mm
2500 sq. mm
2500 sq. mm
80°C/W
225 sq mm
2500 sq. mm
2500 sq. mm
85°C/W
1000 sq mm
1000 sq. mm
1000 sq. mm
91°C/W
Table 5. TO-92 Package
THERMAL
RESISTANCE
Package alone
220°C/W
Package soldered into PC board with plated
through holes only
175°C/W
Package soldered into PC board with 1/4 sq. inch of
copper trace per lead
145°C/W
Package soldered into PC board with plated through holes
in board, no extra copper trace, and a clip-on type
heat sink:
Thermalloy type 2224B
Aavid type 5754
160°C/W
135°C/W
* Device is mounted on topside. Leads are through hole and are soldered
to both sides of board.
Calculating Junction Temperature
Table 2. S8 Package
COPPER AREA
TOPSIDE*
BACKSIDE
THERMAL RESISTANCE
BOARD AREA (JUNCTION-TO-AMBIENT)
2500 sq. mm 2500 sq. mm
2500 sq. mm
1000 sq. mm 2500 sq. mm
2500 sq. mm
120°C/W
120°C/W
225 sq. mm
2500 sq. mm
2500 sq. mm
125°C/W
100 sq. mm
1000 sq. mm
1000 sq. mm
131°C/W
* Device is mounted on topside.
COPPER AREA
BACKSIDE
BOARD AREA
2500 sq. mm
1000 sq. mm 2500 sq. mm
2500 sq. mm
60°C/W
225 sq. mm
2500 sq. mm
2500 sq. mm
68°C/W
100 sq. mm
60°C/W
2500 sq. mm
2500 sq. mm
74°C/W
* Pins 3, 6, and 7 are ground.
** Device is mounted on topside.
2500 sq. mm 2500 sq. mm
THERMAL RESISTANCE
BOARD AREA (JUNCTION-TO-AMBIENT)
2500 sq. mm
50°C/W
1000 sq. mm 2500 sq. mm
2500 sq. mm
50°C/W
225 sq. mm
2500 sq. mm
2500 sq. mm
58°C/W
100 sq. mm
2500 sq. mm
2500 sq. mm
64°C/W
BACKSIDE
1000 sq. mm 1000 sq. mm
1000 sq. mm
57°C/W
1000 sq. mm
1000 sq. mm
60°C/W
0
* Tab of device attached to topside copper
P = 100mA • (7V – 3.3V) + (5mA • 7V)
= 0.405W
If we use an SOT-223 package, then the thermal resistance
will be in the range of 50°C/W to 65°C/W depending on
copper area. So the junction temperature rise above
ambient will be less than or equal to:
0.405W • 60°C/W = 24°C
Table 4. SOT-223 Package
(Thermal Resistance Junction-to-Tab 20°C/W)
TOPSIDE*
IOUT MAX • (VIN MAX – VOUT) + (IGND • VIN)
so,
2500 sq. mm 2500 sq. mm
COPPER AREA
Power dissipated by the device will be equal to:
where, IOUT MAX = 100mA
VIN MAX = 7V
IGND at (IOUT = 100mA, VIN = 7V) = 5mA
Table 3. AS8 Package*
TOPSIDE**
Example: given an output voltage of 3.3V, an input voltage
range of 4.5V to 7V, an output current range of 0mA to
100mA, and a maximum ambient temperature of 50°C,
what will the maximum junction temperature be?
The maximum junction temperature will then be equal to
the maximum junction temperature rise above ambient
plus the maximum ambient temperature or:
TJMAX = 50°C + 24°C = 74°C
Output Capacitance and Transient Performance
The LT1121 is designed to be stable with a wide range of
output capacitors. The minimum recommended value is
1RF with an ESR of 3< or less. For applications where
space is very limited, capacitors as low as 0.33RF can be
used if combined with a small series resistor. Assuming
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Table 6. Suggested Series Resistor Values
SUGGESTED SERIES
OUTPUT CAPACITANCE
RESISTOR
0.33RF
2<
0.47RF
1<
0.68RF
1<
>1RF
None Needed
Protection Features
The LT1121 incorporates several protection features which
make it ideal for use in battery-powered circuits. In addition to the normal protection features associated with
monolithic regulators, such as current limiting and thermal limiting, the device is protected against reverse input
voltages, reverse output voltages, and reverse voltages
from output to input.
Current limit protection and thermal overload protection
are intended to protect the device against current overload
conditions at the output of the device. For normal operation, the junction temperature should not exceed 125°C.
The input of the device will withstand reverse voltages of
30V. Current flow into the device will be limited to less than
1mA (typically less than 100RA) and no negative voltage
will appear at the output. The device will protect both itself
and the load. This provides protection against batteries
that can be plugged in backwards.
For fixed voltage versions of the device, the output can be
pulled below ground without damaging the device. If the
input is open circuit or grounded the output can be pulled
below ground by 20V. The output will act like an open
circuit, no current will flow out of the pin. If the input is
powered by a voltage source, the output will source the
short-circuit current of the device and will protect itself by
thermal limiting. For the adjustable version of the device,
the output pin is internally clamped at one diode drop
below ground. Reverse current for the adjustable device
must be limited to 5mA.
In circuits where a backup battery is required, several
different input/output conditions can occur. The output
voltage may be held up while the input is either pulled to
ground, pulled to some intermediate voltage, or is left
open circuit. Current flow back into the output will vary
depending on the conditions. Many battery-powered circuits incorporate some form of power management. The
following information will help optimize battery life. Table
7 summarizes the following information.
The reverse output current will follow the curve in Figure
2 when the input pin is pulled to ground. This current flows
through the output pin to ground. The state of the shutdown pin will have no effect on output current when the
input pin is pulled to ground.
In some applications it may be necessary to leave the input
to the LT1121 unconnected when the output is held high.
This can happen when the LT1121 is powered from a
rectified AC source. If the AC source is removed, then the
input of the LT1121 is effectively left floating. The reverse
output current also follows the curve in Figure 2 if the input
pin is left open. The state of the shutdown pin will have no
effect on the reverse output current when the input pin is
floating.
100
OUTPUT PIN CURRENT (RA)
that the ESR of the capacitor is low (ceramic) the suggested series resistor is shown in Table 6. The LT1121 is
a micropower device and output transient response will be
a function of output capacitance. See the Transient Response curves in the Typical Performance Characteristics.
Larger values of output capacitance will decrease the peak
deviations and provide improved output transient response. Bypass capacitors, used to decouple individual
components powered by the LT1121, will increase the
effective value of the output capacitor.
TJ = 25°C
90 VIN < VOUT
CURRENT FLOWS
80
INTO OUTPUT PIN
70 TO GROUND
LT1121
(VOUT = VADJ)
60
50
40
LT1121-3.3
30
20
LT1121-5
10
0
0
1
2
3 4 5 6 7 8
OUTPUT VOLTAGE (V)
9
10
1121• F02
Figure 2. Reverse Output Current
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LT1121/LT1121-3.3/LT1121-5
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5
VOUT = 3.3V (LT1121-3.3)
VOUT = 5V (LT1121-5)
4
INPUT CURRENT (RA)
When the input of the LT1121 is forced to a voltage below
its nominal output voltage and its output is held high, the
reverse output current will still follow the curve in Figure
2. This condition can occur if the input of the LT1121 is
connected to a discharged (low voltage) battery and the
output is held up by either a backup battery or by a second
regulator circuit. When the input pin is forced below the
output pin or the output pin is pulled above the input pin,
the input current will typically drop to less than 2RA (see
Figure 3). The state of the shutdown pin will have no effect
on the reverse output current when the output is pulled
above the input.
3
2
1
0
0
1
3
2
INPUT VOLTAGE (V)
4
5
1121 F03
Figure 3. Input Current
Table 7. Fault Conditions
INPUT PIN
SHDN PIN
OUTPUT PIN
< VOUT (Nominal)
Open (Hi)
Forced to VOUT (Nominal)
Reverse Output Current ~ 15RA (See Figure 2)
Input Current ~ 1RA (See Figure 3)
< VOUT (Nominal)
Grounded
Forced to VOUT (Nominal)
Reverse Output Current ~ 15RA (See Figure 2)
Input Current ~ 1RA (See Figure 3)
Open
Open (Hi)
Forced to VOUT (Nominal)
Reverse Output Current ~ 15RA (See Figure 2)
Open
Grounded
Forced to VOUT (Nominal)
Reverse Output Current ~ 15RA (See Figure 2)
f 0.8V
Open (Hi)
f 0V
Output Current = 0
f 0.8V
Grounded
f 0V
Output Current = 0
> 1.5V
Open (Hi)
f 0V
Output Current = Short-Circuit Current
– 30V < VIN < 30V
Grounded
f 0V
Output Current = 0
1121fe
12
242
PN: 071-0961-00, January 2008
LT1121/LT1121-3.3/LT1121-5
U
PACKAGE DESCRIPTIO
N8 Package
8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
.400*
(10.160)
MAX
8
7
6
5
1
2
3
4
.255 ± .015*
(6.477 ± 0.381)
.300 – .325
(7.620 – 8.255)
.065
(1.651)
TYP
.008 – .015
(0.203 – 0.381)
(
+.035
.325 –.015
+0.889
8.255
–0.381
.130 ± .005
(3.302 ± 0.127)
.045 – .065
(1.143 – 1.651)
)
.120
(3.048) .020
MIN (0.508)
MIN
.018 ± .003
.100
(2.54)
BSC
(0.457 ± 0.076)
N8 1002
NOTE:
1. DIMENSIONS ARE
INCHES
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
.189 – .197
(4.801 – 5.004)
NOTE 3
.045 ±.005
.050 BSC
8
.245
MIN
7
6
5
.160 ±.005
.150 – .157
(3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
.030 ±.005
TYP
1
RECOMMENDED SOLDER PAD LAYOUT
.010 – .020
× 45°
(0.254 – 0.508)
.008 – .010
(0.203 – 0.254)
2
.053 – .069
(1.346 – 1.752)
0°– 8° TYP
.016 – .050
(0.406 – 1.270)
.014 – .019
(0.355 – 0.483)
TYP
INCHES
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
NOTE:
1. DIMENSIONS IN
3
4
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
SO8 0303
1121fe
13
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
243
A – Devices Data Sheets
LT1121/LT1121-3.3/LT1121-5
U
PACKAGE DESCRIPTIO
ST Package
3-Lead Plastic SOT-223
(LTC DWG # 05-08-1630)
.248 – .264
(6.30 – 6.71)
.129 MAX
.114 – .124
(2.90 – 3.15)
.059 MAX
.264 – .287
(6.70 – 7.30)
.248 BSC
.130 – .146
(3.30 – 3.71)
.039 MAX
.059 MAX
.181 MAX
.033 – .041
(0.84 – 1.04)
.0905
(2.30)
BSC
.090
BSC
RECOMMENDED SOLDER PAD LAYOUT
10° – 16°
.010 – .014
(0.25 – 0.36)
10°
MAX
.071
(1.80)
MAX
10° – 16°
.024 – .033
(0.60 – 0.84)
.181
(4.60)
BSC
.012
(0.31)
MIN
.0008 – .0040
(0.0203 – 0.1016)
ST3 (SOT-233) 0502
1121fe
14
244
PN: 071-0961-00, January 2008
LT1121/LT1121-3.3/LT1121-5
U
PACKAGE DESCRIPTIO
Z Package
3-Lead Plastic TO-92 (Similar to TO-226)
(LTC DWG # 05-08-1410)
.180 ± .005
(4.572 ± 0.127)
.060 ± .005
(1.524± 0.127)
DIA
.90
(2.286)
NOM
.180 ± .005
(4.572 ± 0.127)
.500
(12.70)
MIN
.050 UNCONTROLLED
(1.270) LEAD DIMENSION
MAX
.016 ± .003
(0.406 ± 0.076)
.050
(1.27)
BSC
5°
NOM
.015 ± .002
(0.381 ± 0.051)
Z3 (TO-92) 0801
.060 ± .010
(1.524 ± 0.254)
3
2
.098 +.016/–.04
(2.5 +0.4/–0.1)
2 PLCS
TO-92 TAPE AND REEL
REFER TO TAPE AND REEL SECTION OF
LTC DATA BOOK FOR ADDITIONAL INFORMATION
.140 ± .010
(3.556 ± 0.127)
1
10° NOM
1121fe
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
15
245
A – Devices Data Sheets
LT1121/LT1121-3.3/LT1121-5
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1120
125mA Low Dropout Regulator with 20RA IQ
Includes 2.5V Reference and Comparator
LT1129
700mA Micropower Low Dropout Regulator
50RA Quiescent Current
LT1175
500mA Negative Low Dropout Micropower Regulator
45RA IQ, 0.26V Dropout Voltage, SOT-223 Package
LT1521
300mA Low Dropout Micropower Regulator with Shutdown
15RA IQ, Reverse Battery Protection
LT1529
3A Low Dropout Regulator with 50RA IQ
500mV Dropout Voltage
LT1611
Inverting 1.4MHz Switching Regulator
5V to – 5V at 150mA, Low Output Noise, SOT-23 Package
LT1613
1.4MHz Single-Cell Micropower DC/DC Converter
SOT-23 Package, Internally Compensated
LTC1627
High Efficiency Synchronous Step-Down Switching Regulator
Burst ModeTM Operation, Monolithic, 100% Duty Cycle
LT1682
Doubler Charge Pump with Low Noise Linear Regulator
Low Output Noise: 60RVRMS (100kHz BW)
LT1762 Series
150mA, Low Noise, LDO Micropower Regulator
25RA Quiescent Current, 20RVRMS Noise
LT1763 Series
500mA, Low Noise, LDO Micropower Regulator
30RA Quiescent Current, 20RVRMS Noise
LT1764 Series
3A Fast Transient Response LDO
300mV Dropout, 40RVRMS Noise
LT1962 Series
300mA, Low Noise, LDO Micropower Regulator
30RA Quiescent Current, 20RVRMS Noise
LT1963 Series
1.5A Fast Transient Response LDO
300mV Dropout, 40RVRMS Noise
Burst Mode is a trademark of Linear Technology Corporation.
1121fe
16
246
Linear Technology Corporation
LT 0407 REV E • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
© LINEAR TECHNOLOGY CORPORATION 1994
PN: 071-0961-00, January 2008
AD5541 Data Sheet
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
247
A – Devices Data Sheets
(VDD = 5 V ⴞ 10%, VREF = 2.5 V, AGND = DGND = 0 V. All specifications
A
MIN to TMAX, unless otherwise noted.)
AD5541/AD5542–SPECIFICATIONS T = T
Parameter
Min
STATIC PERFORMANCE
Resolution
Relative Accuracy, INL
Typ
Max
16
Differential Nonlinearity
± 0.5
± 0.5
± 0.5
± 0.5
Gain Error
–1.5
Gain Error Temperature Coefficient
Zero Code Error
± 0.1
0.3
± 1.0
± 2.0
± 4.0
± 1.0
± 1.5
±5
±7
± 0.05
Zero Code Temperature Coefficient
AD5542
Bipolar Resistor Matching
1.000
± 0.0015 ± 0.0076
±1
±5
±7
± 0.2
Bipolar Zero Offset Error
Bipolar Zero Temperature Coefficient
OUTPUT CHARACTERISTICS
Output Voltage Range
0
–VREF
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Impulse
Digital Feedthrough
DAC Output Impedance
Power Supply Rejection Ratio
DAC REFERENCE INPUT
Reference Input Range
Reference Input Resistance2
LOGIC INPUTS
Input Current
VINL, Input Low Voltage
VINH, Input High Voltage
Input Capacitance3
Hysteresis Voltage3
VREF – 1 LSB
VREF – 1 LSB
1
25
10
10
6.25
± 1.0
2.0
9
7.5
VDD
±1
0.8
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
ppm/°C
LSB
LSB
ppm/°C
Unipolar Operation
AD5542 Bipolar Operation
to 1/2 LSB of FS, CL = 10 pF
CL = 10 pF, Measured from 0% to 63%
1 LSB Change Around the Major Carry
All 1s Loaded to DAC, VREF = 2.5 V
Tolerance Typically 20%
ΔVDD ± 10%
V
kΩ
kΩ
Unipolar Operation
AD5542, Bipolar Operation
MHz
mV p-p
dB
pF
pF
0.3
1.5
5.50
1.1
6.05
TA = 25°C
V
V
μs
V/μs
nV-s
nV-s
kΩ
LSB
1.3
1
92
75
120
4.50
L, C Grades
B, J Grades
A Grade
Guaranteed Monotonic
J Grade
TA = 25°C
RFB/RINV, Typically RFB = RINV = 28 kΩ
Ratio Error
TA = 25°C
0.4
10
Test Condition
Ω/Ω
%
LSB
LSB
ppm/°C
μA
V
V
pF
V
2.4
REFERENCE
Reference –3 dB Bandwidth
Reference Feedthrough
Signal-to-Noise Ratio
Reference Input Capacitance
POWER REQUIREMENTS
VDD
IDD
Power Dissipation
±1
±2
Unit
All 1s Loaded
All 0s Loaded, VREF = 1 V p-p at 100 kHz
Code 0000 Hex
Code FFFF Hex
V
mA
mW
NOTES
1
Temperature ranges are as follows: A, B, C Versions: –40°C to +85°C. J, L Versions: 0°C to 70°C.
2
Reference input resistance is code-dependent, minimum at 8555 hex.
3
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–
248
REV. A
PN: 071-0961-00, January 2008
AD5541/AD5542
(VDD = 5 V ⴞ 5%, VREF = 2.5 V, AGND = DGND = 0 V. All specifications TA = TMIN to TMAX, unless
TIMING CHARACTERISTICS1, 2 otherwise noted.)
Parameter
Limit at TMIN, TMAX
All Versions
Unit
Description
fSCLK
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
25
40
20
20
15
15
35
20
15
0
30
30
30
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCLK Cycle Frequency
SCLK Cycle Time
SCLK High Time
SCLK Low Time
CS Low to SCLK High Setup
CS High to SCLK High Setup
SCLK High to CS Low Hold Time
SCLK High to CS High Hold Time
Data Setup Time
Data Hold Time
LDAC Pulsewidth
CS High to LDAC Low Setup
CS High Time Between Active Periods
NOTES
1
Guaranteed by design. Not production tested.
2
Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5 ns (10% to
90% of VDD) and timed from a voltage level of (V IL + VIH)/2.
Specifications subject to change without notice.
t1
SCLK
t2
t6
t3
t5
t7
t4
CS
t 12
t8
t9
DIN
DB15
DB0
t 11
t 10
LDAC*
*AD5542 ONLY. MAY BE TIED PERMANENTLY LOW IF REQUIRED.
Figure 1. Timing Diagram
REV. A
–3–
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
249
A – Devices Data Sheets
AD5541/AD5542
ABSOLUTE MAXIMUM RATINGS*
Maximum Junction Temperature, (TJ max) . . . . . . . . . 150°C
Package Power Dissipation . . . . . . . . . . . . . (TJ max – TA)/θJA
Thermal Impedance θJA
SOIC (SO-8) . . . . . . . . . . . . . . . . . . . . . . . . . . 149.5°C/W
SOIC (R-14) . . . . . . . . . . . . . . . . . . . . . . . . . . 104.5°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
(TA = 25°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
Digital Input Voltage to DGND . . . . . –0.3 V to VDD + 0.3 V
VOUT to AGND . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
AGND, AGNDF, AGNDS to DGND . . . . . –0.3 V to +0.3 V
Input Current to Any Pin Except Supplies . . . . . . . . ± 10 mA
Operating Temperature Range
Industrial (A, B, C Versions) . . . . . . . . . . . –40°C to +85°C
Commercial (J, L Versions) . . . . . . . . . . . . . . . 0°C to 70°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model
INL
DNL
Temperature Range
Package Description
Package Option
AD5541CR
AD5541LR
AD5541BR
AD5541JR
AD5541AR
± 1 LSB
± 1 LSB
± 2 LSB
± 2 LSB
± 4 LSB
± 1 LSB
± 1 LSB
± 1 LSB
± 1.5 LSB
± 1 LSB
–40°C to +85°C
0°C to 70°C
–40°C to +85°C
0°C to 70°C
–40°C to +85°C
8-Lead Small Outline IC
8-Lead Small Outline IC
8-Lead Small Outline IC
8-Lead Small Outline IC
8-Lead Small Outline IC
SO-8
SO-8
SO-8
SO-8
SO-8
AD5542CR
AD5542LR
AD5542BR
AD5542JR
AD5542AR
± 1 LSB
± 1 LSB
± 2 LSB
± 2 LSB
± 4 LSB
± 1 LSB
± 1 LSB
± 1 LSB
± 1.5 LSB
± 1 LSB
–40°C to +85°C
0°C to 70°C
–40°C to +85°C
0°C to 70°C
–40°C to +85°C
14-Lead Small Outline IC
14-Lead Small Outline IC
14-Lead Small Outline IC
14-Lead Small Outline IC
14-Lead Small Outline IC
R-14
R-14
R-14
R-14
R-14
Die Size = 80 × 139 = 11,120 sq mil; Number of Transistors = 1,230.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5541/AD5542 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
–4–
250
WARNING!
ESD SENSITIVE DEVICE
REV. A
PN: 071-0961-00, January 2008
AD5541/AD5542
AD5541 PIN FUNCTION DESCRIPTIONS
Mnemonic
Pin No.
Description
VOUT
AGND
REF
1
2
3
CS
SCLK
4
5
DIN
6
DGND
VDD
7
8
Analog Output Voltage from the DAC.
Ground Reference Point for Analog Circuitry.
This is the voltage reference input for the DAC. Connect to external 2.5 V reference.
Reference can range from 2 V to VDD.
This is a logic input signal. The chip select signal is used to frame the serial data input.
Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle
must be between 40% and 60%.
Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on
the rising edge of SCLK.
Digital Ground. Ground reference for digital circuitry.
Analog Supply Voltage, 5 V ± 10%.
AD5541 PIN CONFIGURATION
SOIC
VOUT 1
8
AD5542 PIN CONFIGURATION
SOIC
VDD
CS 4
5
14 VDD
RFB 1
7 DGND
AD5541
TOP VIEW
REF 3 (Not to Scale) 6 DIN
AGND 2
13 INV
VOUT 2
12 DGND
AGNDF 3
AD5542
TOP VIEW 11 LDAC
REFS 5 (Not to Scale) 10 DIN
SCLK
AGNDS 4
REFF 6
9
NC
CS 7
8
SCLK
NC = NO CONNECT
AD5542 PIN FUNCTION DESCRIPTIONS
Mnemonic
Pin No.
Description
RFB
VOUT
AGNDF
AGNDS
REFS
1
2
3
4
5
REFF
6
CS
SCLK
7
8
NC
DIN
9
10
LDAC
11
DGND
INV
12
13
VDD
14
Feedback Resistor. In bipolar mode connect this pin to external op amp output.
Analog Output Voltage from the DAC.
Ground Reference Point for Analog Circuitry (Force).
Ground Reference Point for Analog Circuitry (Sense).
This is the voltage reference input (sense) for the DAC. Connect to external 2.5 V reference.
Reference can range from 2 V to VDD.
This is the voltage reference input (force) for the DAC. Connect to external 2.5 V reference.
Reference can range from 2 V to VDD.
This is a logic input signal. The chip select signal is used to frame the serial data input.
Clock input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle
must be between 40% and 60%.
No Connect.
Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on
the rising edge of SCLK.
LDAC Input. When this input is taken low, the DAC register is simultaneously updated with
the contents of the input register.
Digital Ground. Ground reference for digital circuitry.
Connected to the Internal Scaling Resistors of the DAC. Connect INV pin to external op amps
inverting input in bipolar mode.
Analog Supply Voltage, 5 V ± 10%.
REV. A
–5–
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
251
A – Devices Data Sheets
AD5541/AD5542
TERMINOLOGY
Relative Accuracy
For the DAC, relative accuracy or integral nonlinearity (INL)
is a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer function.
A typical INL versus code plot can be seen in Figure 2.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ± 1 LSB maximum
ensures monotonicity. Figure 3 illustrates a typical DNL versus
code plot.
Gain Error
Gain error is the difference between the actual and ideal analog
output range, expressed as a percent of the full-scale range.
It is the deviation in slope of the DAC transfer characteristic
from ideal.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s
and is measured when the digital input code is changed by 1 LSB
at the major carry transition. A plot of the glitch impulse is shown
in Figure 15.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital inputs of the DAC,
but is measured when the DAC output is not updated. CS is
held high, while the CLK and DIN signals are toggled. It is
specified in nV-s and is measured with a full-scale code change
on the data bus, i.e., from all 0s to all 1s and vice versa. A typical plot of digital feedthrough is shown in Figure 14.
Power Supply Rejection Ratio
This is a measure of the change in gain error with changes in
temperature. It is expressed in ppm/°C.
This specification indicates how the output of the DAC is affected
by changes in the power supply voltage. Power-supply rejection
ratio is quoted in terms of % change in output per % change in
VDD for full-scale output of the DAC. VDD is varied by ± 10%.
Zero Code Error
Reference Feedthrough
Zero code error is a measure of the output error when zero code
is loaded to the DAC register.
This is a measure of the feedthrough from the VREF input to the
DAC output when the DAC is loaded with all 0s. A 100 kHz,
1 V p-p is applied to VREF. Reference feedthrough is expressed
in mV p-p.
Gain Error Temperature Coefficient
Zero Code Temperature Coefficient
This is a measure of the change in zero code error with a change
in temperature. It is expressed in mV/°C.
–6–
252
REV. A
PN: 071-0961-00, January 2008
Typical Performance Characteristics– AD5541/AD5542
0.50
VDD = 5V
VREF = 2.5V
0.25
DIFFERENTIAL NONLINEARITY – LSB
INTEGRAL NONLINEARITY – LSB
0.50
0
–0.25
–0.50
VDD = 5V
VREF = 2.5V
0.25
0
–0.25
–0.50
–0.75
0
8192
16384 24576 32768 40960 49152 57344 65536
CODE
16384 24576 32768 40960 49152 57344 65536
CODE
0.75
0.25
VDD = 5V
VREF = 2.5V
DIFFERENTIAL NONLINEARITY – LSB
INTEGRAL NONLINEARITY – LSB
8192
Figure 5. Differential Nonlinearity vs. Code
Figure 2. Integral Nonlinearity vs. Code
0
–0.25
–0.50
–0.75
–1.00
–60
0
–40
–20
0
20
40
60
80
100
120
VDD = 5V
VREF = 2.5V
0.50
0.25
0
–0.25
–0.50
–60
140
–40
–20
20
40
60
80
100
120
140
Figure 6. Differential Nonlinearity vs. Temperature
Figure 3. Integral Nonlinearity vs. Temperature
0.75
0.50
VDD = 5V
TA = 25ⴗC
VREF = 2.5V
TA = 25ⴗC
0.50
LINEARITY ERROR – LSB
0.25
LINEARITY ERROR – LSB
0
TEMPERATURE – ⴗC
TEMPERATURE – ⴗC
DNL
0
–0.25
DNL
0.25
0
INL
–0.25
–0.50
INL
–0.75
–0.50
2
3
4
5
SUPPLY VOLTAGE – V
6
0
7
2
3
4
REFERENCE VOLTAGE – V
5
6
Figure 7. Linearity Error vs. Reference Voltage
Figure 4. Linearity Error vs. Supply Voltage
REV. A
1
–7–
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
253
A – Devices Data Sheets
AD5541/AD5542
0.75
0
VDD = 5V
VREF = 2.5V
ZERO-CODE ERROR – LSB
GAIN ERROR – LSB
VDD = 5V
VREF = 2.5V
–0.25
–0.50
–0.75
–60
–40
–20
0
20
40
60
80
100
120
0.50
0.25
0
–60
140
–40
–20
20
0
TEMPERATURE – ⴗC
Figure 8. Gain Error vs. Temperature
60
80
100
120
140
Figure 11. Zero-Code Error vs. Temperature
450
250
VDD = 5V
VLOGIC = 5V
VREF = 2.5V
TA = 25ⴗC
400
SUPPLY CURRENT – ␮A
SUPPLY CURRENT – ␮A
40
TEMPERATURE – ⴗC
200
350
REFERENCE
VOLTAGE
VDD = 5V
300
SUPPLY
VOLTAGE
VREF = 2.5V
250
200
150
–40
0
–20
20
40
60
80
100
150
120
0
1
2
TEMPERATURE – ⴗC
Figure 9. Supply Current vs. Temperature
5555H
6
VDD = 5V
VREF = 2.5V
TA = 25ⴗC
8555H
REFERENCE CURRENT – ␮A
SUPPLY CURRENT – ␮A
5
300
VDD = 5V
VREF = 2.5V
TA = 25ⴗC
350
300
250
200
250
0555H
BIPOLAR MODE
200
150
UNIPOLAR MODE
100
50
0
1
3
2
DIGITAL INPUT VOLTAGE – V
4
5
0
Figure 10. Supply Current vs. Digital Input Voltage
8192
16384 24576 32768 40960 49152
CODE
57344
65536
Figure 13. Reference Current vs. Code
–8–
254
4
Figure 12. Supply Current vs Reference Voltage or Supply
Voltage
400
150
3
VOLTAGE – V
REV. A
PN: 071-0961-00, January 2008
AD5541/AD5542
VREF = 2.5V
VDD = 5V
TA = 25ⴗC
100
90
CLOCK (5V/DIV)
2µs/DIV
100
90
CS (5V/DIV)
10pF
50pF
100pF
VOUT (50mV/DIV)
VREF = 2.5V
VDD = 5V
TA = 25ⴗC
10
10
200pF
0%
0%
VOUT (0.5V/DIV)
2␮s/DIV
Figure 16. Large Signal Settling Time
Figure 14. Digital Feedthrough
VREF = 2.5V
VDD = 5V
TA = 25ⴗC
100
90
VREF = 2.5V
VDD = 5V
TA = 25ⴗC
100
90
VOUT (1V/DIV)
CS (5V/DIV)
VOUT (0.1V/DIV)
VOUT (50mV/DIV)
GAIN = –216
1LSB = 8.2mV
10
10
0%
0%
0.5␮s/DIV
2µs/DIV
Figure 17. Small Signal Settling Time
Figure 15. Digital-to-Analog Glitch Impulse
GENERAL DESCRIPTION
The AD5541/AD5542 are single, 16-bit, serial input, voltage
output DACs. They operate from a single supply ranging from
2.7 V to 5 V and consume typically 300 mA with a supply of
5 V. Data is written to these devices in a 16-bit word format, via
a 3- or 4-wire serial interface. To ensure a known power-up state,
these parts were designed with a power-on reset function. In unipolar mode, the output is reset to 0 V, while in bipolar mode, the
AD5542 output is set to –VREF. Kelvin sense connections for
the reference and analog ground are included on the AD5542.
Digital-to-Analog Section
The DAC architecture consists of two matched DAC sections.
A simplified circuit diagram is shown in Figure 18. The DAC
architecture of the AD5541/AD5542 is segmented. The four
MSBs of the 16-bit data word are decoded to drive 15 switches,
E1 to E15. Each of these switches connects one of 15 matched
resistors to either AGND or VREF. The remaining 12 bits of the
data word drive switches S0 to S11 of a 12-bit voltage mode
R-2R ladder network.
R
R
VOUT
2R
2R
2R
2R
2R
2R
2R
S0
S1
S11
E1
E2
E15
VREF
12-BIT R-2R LADDER
FOUR MSB's DECODED INTO
15 EQUAL SEGMENTS
Figure 18. DAC Architecture
REV. A
With this type of DAC configuration, the output impedance
is independent of code, while the input impedance seen by
the reference is heavily code dependent. The output voltage
is dependent on the reference voltage as shown in the following equation.
VOUT =
VREF × D
2N
where D is the decimal data word loaded to the DAC register
and N is the resolution of the DAC. For a reference of 2.5 V,
the equation simplifies to the following.
VOUT =
2.5 × D
65, 536
giving a VOUT of 1.25 V with midscale loaded, and 2.5 V with
full-scale loaded to the DAC.
The LSB size is VREF/65,536.
Serial Interface
The AD5541 and AD5542 are controlled by a versatile 3-wire
serial interface, which operates at clock rates up to 25 MHz and
is compatible with SPI, QSPI, MICROWIRE, and DSP interface
standards. The timing diagram can be seen in Figure 1. Input
data is framed by the chip select input, CS. After a high-to-low
transition on CS, data is shifted synchronously and latched into
the input register on the rising edge of the serial clock, SCLK.
Data is loaded MSB first in 16-bit words. After 16 data bits
have been loaded into the serial input register, a low-to-high
transition on CS transfers the contents of the shift register to the
DAC. Data can only be loaded to the part while CS is low.
–9–
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
255
A – Devices Data Sheets
AD5541/AD5542
The AD5542 has an LDAC function that allows the DAC latch
to be updated asynchronously by bringing LDAC low after CS
goes high. LDAC should be maintained high while data is written
to the shift register. Alternatively, LDAC may be tied permanently
low to update the DAC synchronously. With LDAC tied permanently low, the rising edge of CS will load the data to the DAC.
+2.5V
0.1␮F
0.1␮F
RFB
SERIAL
INTERFACE
VDD
0.1␮F
0.1␮F
SERIAL
INTERFACE
10␮F
VDD
REF(REFF*)
CS
REFS*
AD820/
OP196
AD5541/AD5542
DIN
OUT
SCLK
LDAC*
DGND
AGND
UNIPOLAR
OUTPUT
RFB
* AD5542 ONLY
DGND
VREF × (65,535/65,536)
VREF × (32,768/65,536) = 1/2 VREF
VREF × (1/65,536)
0V
Figure 20. Bipolar Output (AD5542 Only)
Table II. Bipolar Code Table
DAC Latch Contents
MSB
LSB
Analog Output
1111 1111 1111 1111
1000 0000 0000 0001
1000 0000 0000 0000
0111 1111 1111 1111
0000 0000 0000 0000
+VREF × (32,767/32,768)
+VREF × (1/32,768)
0V
–VREF × (1/32,768)
–VREF × (32,768/32,768) = –VREF
VOUT – BIP =
[(V
OUT –UNI
where
VOUT–UNI
D
VREF
VGE
VZSE
INL
D
216
)
)
1 + 2 + RD / A
(
)]
Output Amplifier Selection
For bipolar mode, a precision amplifier should be used, supplied
from a dual power supply. This will provide the ± VREF output.
In a single-supply application, selection of a suitable op amp
may be more difficult as the output swing of the amplifier does
not usually include the negative rail, in this case AGND. This
can result in some degradation of the specified performance
unless the application does not use codes near zero.
× (VREF + VGE ) + VZSE + INL
= Unipolar Mode Worst-Case Output
= Code Loaded to DAC
= Reference Voltage Applied to Part
= Gain Error in Volts
= Zero Scale Error in Volts
= Integral Nonlinearity in Volts
Bipolar Output Operation
With the aid of an external op amp, the AD5542 may be configured to provide a bipolar voltage output. A typical circuit of
such operation is shown in Figure 20. The matched bipolar offset resistors RFB and RINV are connected to an external op amp to
achieve this bipolar output swing, typically RFB = RINV = 28 kΩ.
Table II shows the transfer function for this output operating
mode. Also provided on the AD5542 are a set of Kelvin connections to the analog ground inputs.
The selected op amp needs to have very low-offset voltage, (the
DAC LSB is 38 μV with a 2.5 V reference), to eliminate the
need for output offset trims. Input bias current should also be
very low as the bias current multiplied by the DAC output
impedance (approximately 6K) will add to the zero code error.
Rail-to-rail input and output performance is required. For fast
settling, the slew rate of the op amp should not impede the
settling time of the DAC. Output impedance of the DAC is
constant and code-independent, but in order to minimize gain
errors, the input impedance of the output amplifier should be
as high as possible. The amplifier should also have a 3 dB bandwidth of 1 MHz or greater. The amplifier adds another time
constant to the system, hence increasing the settling time of the
output. A higher 3 dB amplifier bandwidth results in a shorter
effective settling time of the combined DAC and amplifier.
Force Sense Amplifier Selection
These amplifiers will be single-supply, low-noise amplifiers. A
low-output impedance at high frequencies is preferred as they
need to be able to handle dynamic currents of up to ± 20 mA.
–10–
256
)(
(
+ VOS 2 + RD – VREF 1 + RD
where
VOS = External Op Amp Input Offset Voltage
RD = RFB and RIN Resistor Matching Error
A = Op Amp Open-Loop Gain
Assuming a perfect reference, the worst case output voltage may
be calculated from the following equation.
Unipolar Mode Worst-Case Output
VOUT –UNI =
–5V
EXTERNAL
OP AMP
AGNDF AGNDS
Table I. Unipolar Code Table
1111 1111 1111 1111
1000 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0000
BIPOLAR
OUTPUT
OUT
AD5541/AD5542
LDAC
Figure 19. Unipolar Output
Analog Output
INV
Assuming a perfect reference, the worst-case bipolar output
voltage may be calculated from the following equation.
Bipolar Mode Worst-Case Output
EXTERNAL
OP AMP
DAC Latch Contents
MSB
LSB
+5V
REFS
RINV
DIN
These DACs are capable of driving unbuffered loads of 60 kΩ.
Unbuffered operation results in low-supply current, typically
300 μA, and a low-offset error. The AD5541 provides a unipolar
output swing ranging from 0 V to VREF. The AD5542 can be
configured to output both unipolar and bipolar voltages. Figure
19 shows a typical unipolar output voltage circuit. The code
table for this mode of operation is shown in Table I.
SCLK
+2.5V
REFF
CS
Unipolar Output Operation
+5V
10␮F
+5V
REV. A
PN: 071-0961-00, January 2008
AD5541/AD5542
Reference and Ground
AD5541/AD5542 to 68HC11 Interface
As the input impedance is code-dependent, the reference pin
should be driven from a low-impedance source. The AD5541/
AD5542 operates with a voltage reference ranging from 2 V to
VDD. References below 2 V will result in reduced accuracy.
The DAC’s full-scale output voltage is determined by the
reference. Tables I and II outline the analog output voltage
or particular digital codes. For optimum performance, Kelvin
sense connections are provided on the AD5542.
Figure 22 shows a serial interface between the AD5541/AD5542
and the 68HC11 microcontroller. SCK of the 68HC11 drives
the SCLK of the DAC, while the MOSI output drives the
serial data lines SDIN. CS signal is driven from one of the
port lines. The 68HC11 is configured for master mode; MSTR
= 1, CPOL = 0, and CPHA = 0. Data appearing on the MOSI
output is valid on the rising edge of SCK.
If the application doesn’t require separate force and sense lines,
they should be tied together close to the package to minimize
voltage drops between the package leads and the internal die.
68HC11/
68L11*
Power-On Reset
PC6
LDAC**
PC7
CS
MOSI
SCK
These parts have a power-on reset function to ensure the output
is at a known state upon power-up. On power-up, the DAC
register contains all zeros, until data is loaded from the serial
register. However, the serial register is not cleared on power-up,
so its contents are undefined. When loading data initially to the
DAC, 16 bits or more should be loaded to prevent erroneous
data appearing on the output. If more than 16 bits are loaded,
the last 16 are kept, and if less than 16 are loaded, bits will remain
from the previous word. If the AD5541/AD5542 needs to be
interfaced with data shorter than 16 bits, the data should be
padded with zeros at the LSBs.
DIN
AD5541/
AD5542*
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY.
**AD5542 ONLY
Figure 22. AD5541/AD5542 to 68HC11/68L11 Interface
AD5541/AD5542 to MICROWIRE Interface
Figure 23 shows an interface between the AD5541/AD5542 and
any MICROWIRE-compatible device. Serial data is shifted out
on the falling edge of the serial clock and into the AD5541/
AD5542 on the rising edge of the serial clock. No glue logic is
required as the DAC clocks data into the input shift register on
the rising edge.
Power Supply and Reference Bypassing
For accurate high-resolution performance, it is recommended that
the reference and supply pins be bypassed with a 10 μF tantalum
capacitor in parallel with a 0.1 μF ceramic capacitor.
MICROWIRE*
AD5541/AD5542–ADSP-2101/ADSP-2103 Interface
Figure 21 shows a serial interface between the AD5541/AD5542
and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103
should be set to operate in the SPORT transmit alternate framing
mode. The ADSP-2101/ADSP-2103 is programmed through the
SPORT control register and should be configured as follows:
Internal Clock Operation, Active Low Framing, 16-Bit Word
Length. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. As the data is clocked out
on each rising edge of the serial clock, an inverter is required
between the DSP and the DAC, because the AD5541/AD5542
clocks data in on the falling edge of the SCLK.
Figure 23. AD5541/AD5542 to MICROWIRE Interface
AD5541/AD5542 to 80C51/80L51 Interface
A serial interface between the AD5541/AD5542 and the 80C51/
80L51 microcontroller is shown in Figure 24. TxD of the
microcontroller drives the SCLK of the AD5541/AD5542, while
RxD drives the serial data line of the DAC. P3.3 is a bit programmable pin on the serial port which is used to drive CS.
The 80C51/80L51 provides the LSB first, while the AD5541/
AD5542 expects the MSB of the 16-bit word first. Care should
be taken to ensure the transmit routine takes this into account.
When data is to be transmitted to the DAC, P3.3 is taken low.
Data on RxD is valid on the falling edge of TxD, so the clock must
be inverted as the DAC clocks data into the input shift register on the rising edge of the serial clock. The 80C51/80L51
transmits its data in 8-bit bytes with only eight falling clock
edges occurring in the transmit cycle. As the DAC requires a
16-bit word, P3.3 must be left low after the first eight bits are
transferred, and brought high after the second byte is transferred. LDAC on the AD5542 may also be controlled by
the 80C51/80L51 serial port output by using another bit
programmable pin, P3.4.
CS
DT
DIN
AD5541/
AD5542*
80C51/
80L51*
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY.
**AD5542 ONLY
P3.4
LDAC**
P3.3
CS
RxD
DIN
TxD
SCLK
AD5541/
AD5542*
*ADDITIONAL PINS OMITTED FOR CLARITY.
**AD5542 ONLY
Figure 21. AD5541/AD5542 to ADSP-2101/ADSP-2103
Interface
REV. A
AD5541/
AD5542*
LDAC**
TFS
SCLK
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY.
Microprocessor interfacing to the AD5541/AD5542 is via a
serial bus that uses standard protocol compatible with DSP
processors and microcontrollers. The communications channel
requires a 3-wire interface consisting of a clock signal, a data
signal and a synchronization signal. The AD5541/AD5542
requires a 16-bit data word with data valid on the rising edge of
SCLK. The DAC update may be done automatically when all
the data is clocked in or it may be done under control of LDAC
(AD5542 only).
FO
CS
DIN
SCLK
MICROPROCESSOR INTERFACING
ADSP-2101/
ADSP-2103*
CS
SO
Figure 24. AD5541/AD5542 to 80C51/80L51 Interface
–11–
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
257
A – Devices Data Sheets
AD5541/AD5542
Decoding Multiple AD5541/AD5542s
The digital inputs of the AD5541/AD5542 are Schmitttriggered, so they can accept slow transitions on the digital input
lines. This makes these parts ideal for industrial applications
where it may be necessary that the DAC is isolated from the
controller via optocouplers. Figure 25 illustrates such an interface.
5V
REGULATOR
10␮F
POWER
The CS pin of the AD5541/AD5542 can be used to select one
of a number of DACs. All devices receive the same serial clock
and serial data, but only one device will receive the CS signal at
any one time. The DAC addressed will be determined by the
decoder. There will be some digital feedthrough from the digital
input lines. Using a burst clock will minimize the effects of digital feedthrough on the analog signal channels. Figure 26 shows a
typical circuit.
0.1␮F
AD5541/AD5542
SCLK
C3713–8–10/99
APPLICATIONS
Optocoupler interface
CS
VDD
DIN
10k⍀
SCLK
DIN
VDD
VOUT
SCLK
VDD
SCLK
ENABLE
VDD
AD5541/AD5542
AD5541/AD5542
EN
CS
CODED
ADDRESS
DECODER
DIN
10k⍀
SCLK
CS
CS
VOUT
VOUT
DGND
AD5541/AD5542
VDD
CS
DIN
10k⍀
VOUT
SCLK
DIN
DIN
GND
AD5541/AD5542
CS
DIN
Figure 25. AD5541/AD5542 in an Optocoupler Interface
VOUT
SCLK
Figure 26. Addressing Multiple AD5541/AD5542s
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead SO
(SO-8)
14-Lead SO
(R-14)
0.1574 (4.00)
0.1497 (3.80)
8
5
1
4
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
PIN 1
PIN 1
0.0196 (0.50)
ⴛ 45ⴗ
0.0099 (0.25)
0.0500 (1.27)
BSC
0.0098 (0.25)
0.0040 (0.10)
SEATING
PLANE
8
1
7
0.050 (1.27)
BSC
0.0688 (1.75)
0.0532 (1.35)
0.0688 (1.75)
0.0532 (1.35)
0.0192 (0.49)
0.0138 (0.35)
8ⴗ
0.0098 (0.25) 0ⴗ 0.0500 (1.27)
0.0160 (0.41)
0.0075 (0.19)
0.0098 (0.25)
0.0040 (0.10)
–12–
258
14
0.2440 (6.20)
0.2284 (5.80)
0.0196 (0.50)
ⴛ 45ⴗ
0.0099 (0.25)
PRINTED IN U.S.A.
0.3444 (8.75)
0.3367 (8.55)
0.1968 (5.00)
0.1890 (4.80)
8ⴗ
0.0192 (0.49) SEATING 0.0099 (0.25) 0ⴗ 0.0500 (1.27)
0.0138 (0.35) PLANE
0.0160 (0.41)
0.0075 (0.19)
REV. A
PN: 071-0961-00, January 2008
MAX195 Data Sheet
19-0377; Rev 1; 12/97
KIT
ATION
EVALU
BLE
A
IL
A
V
A
16-Bit, 85ksps ADC with 10µA Shutdown
The MAX195, with an external reference (up to +5V),
offers a unipolar (0V to VREF) or bipolar (-VREF to VREF)
pin-selectable input range. Separate analog and digital
supplies minimize digital-noise coupling.
The chip select (CS) input controls the three-state serialdata output. The output can be read either during conversion as the bits are determined, or following conversion at
up to 5Mbps using the serial clock (SCLK). The end-ofconversion (EOC) output can be used to interrupt a
processor, or can be connected directly to the convert
input (CONV) for continuous, full-speed conversions.
The MAX195 is available in 16-pin DIP, wide SO, and
ceramic sidebraze packages.
________________________Applications
Portable Instruments
Audio
Industrial Controls
Robotics
Multiple Transducer Measurements
Medical Signal Acquisition
Vibrations Analysis
Digital Signal Processing
__________________Pin Configuration
____________________________Features
♦ 16 Bits, No Missing Codes
♦ 90dB SINAD
♦ 9.4µs Conversion Time
♦ 10µA (max) Shutdown Mode
♦ Built-In Track/Hold
♦ AC and DC Specified
♦ Unipolar (0V to VREF) and Bipolar (-VREF to VREF)
Input Range
♦ Three-State Serial-Data Output
♦ Small 16-Pin DIP, SO, and Ceramic SB Packages
______________Ordering Information
PART
TEMP. RANGE
MAX195BCPE
0°C to +70°C
MAX195BCWE
MAX195ACDE
MAX195BC/D
MAX195BEPE
MAX195BEWE
MAX195AEDE
MAX195AMDE
MAX195BMDE
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
-55°C to +125°C
PIN-PACKAGE
16 Plastic DIP
16 Wide SO
16 Ceramic SB
Dice*
16 Plastic DIP
16 Wide SO
16 Ceramic SB
16 Ceramic SB**
16 Ceramic SB**
* Dice are specified at TA = +25°C, DC parameters only.
** Contact factory for availability and processing to MIL-STD-883.
________________Functional Diagram
AIN
REF
13
MAIN DAC
12
Σ
TOP VIEW
BP/UP/SHDN 1
16 VDDA
CLK 2
15 VSSA
SCLK 3
VDDD 4
CALIBRATION
DACs
14 AGND
MAX195
CLK
SCLK
DGND 6
11 VSSD
CONV
10 RESET
9
CONV
VDDD
DGND
VSSD
VDDA
AGND
VSSA
MAX195
2
12 REF
CS 8
COMPARATOR
4
6
11
16
14
15
SAR
13 AIN
DOUT 5
EOC 7
MAX195
_______________General Description
The MAX195 is a 16-bit successive-approximation analog-to-digital converter (ADC) that combines high
speed, high accuracy, low power consumption, and a
10µA shutdown mode. Internal calibration circuitry corrects linearity and offset errors to maintain the full rated
performance over the operating temperature range without external adjustments. The capacitive-DAC architecture provides an inherent 85ksps track/hold function.
BP/UP/SHDN
CS
RESET
3
5
9
1
8
10
CONTROL LOGIC
DOUT
THREE-STATE BUFFER
7
EOC
DIP/Wide SO/Ceramic SB
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
259
A – Devices Data Sheets
MAX195
16-Bit, 85ksps ADC with 10µA Shutdown
ABSOLUTE MAXIMUM RATINGS
VDDD to DGND .....................................................................+7V
VDDA to AGND......................................................................+7V
VSSD to DGND.........................................................+0.3V to -6V
VSSA to AGND .........................................................+0.3V to -6V
VDDD to VDDA, VSSD to VSSA ..........................................±0.3V
AIN, REF ....................................(VSSA - 0.3V) to (VDDA + 0.3V)
AGND to DGND ..................................................................±0.3V
Digital Inputs to DGND...............................-0.3V, (VDDA + 0.3V)
Digital Outputs to DGND............................-0.3V, (VDDA + 0.3V)
Continuous Power Dissipation (TA = +70°C)
Plastic DIP (derate 10.53mW/°C above +70°C) ............842mW
Wide SO (derate 9.52mW/°C above +70°C)..................762mW
Ceramic SB (derate 10.53mW/°C above +70°C)...........842mW
Operating Temperature Ranges
MAX195_C_E ........................................................0°C to +70°C
MAX195_E_E .....................................................-40°C to +85°C
MAX195_MDE..................................................-55°C to +125°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10sec) .............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDDD = VDDA = +5V, VSSD = VSSA = -5V, fCLK = 1.7MHz, VREF = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical
values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ACCURACY (Note 1)
Resolution
Differential Nonlinearity
Integral Nonlinearity
RES
DNL
INL
Unipolar/Bipolar Offset Error
16
Bits
MAX195A
±1
MAX195B
±2
MAX195A
±0.003
MAX195B
±0.004
MAX195A, VREF = 4.75V
±3
MAX195B, VREF = 4.75V
±4
Unipolar/Bipolar Offset Tempco
0.4
VREF = 4.75V
±0.0075
Bipolar Full-Scale Error
VREF = 4.75V
±0.018
0.1
Power-Supply Rejection
Ratio (VDDA and VSSA only)
VDDA = 4.75V to 5.25V, VREF = 4.75V
65
VSSA = -5.25V to -4.75V, VREF = 4.75V
65
%FSR
LSB
ppm/°C
Unipolar Full-Scale Error
Full-Scale Tempco
LSB
%FSR
%FSR
ppm/°C
dB
ANALOG INPUT
Unipolar
Input Range
Bipolar
Input Capacitance
0
VREF
-VREF
VREF
Unipolar
250
Bipolar
125
V
pF
DYNAMIC PERFORMANCE (fs = 85kHz, bipolar range AIN = -5V to +5V, 1kHz) (Note 1)
Signal-to-Noise plus Distortion
Ratio (Note 2)
Total Harmonic Distortion (up to
the 5th harmonic) (Note 2)
SINAD
TA = +25°C
THD
TA = +25°C
Peak Spurious Noise (Note 2)
90
-97
TA = +25°C
16 (tCLK)
dB
-90
dB
-90
dB
Conversion Time
tCONV
Clock Frequency
(Notes 3, 4)
fCLK
1.7
MHz
Serial Clock Frequency
fSCLK
5
MHz
2
260
87
9.4
µs
_______________________________________________________________________________________
PN: 071-0961-00, January 2008
16-Bit, 85ksps ADC with 10µA Shutdown
MAX195
ELECTRICAL CHARACTERISTICS (continued)
(VDDD = VDDA = +5V, VSSD = VSSA = -5V, fCLK = 1.7MHz, VREF = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical
values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS (CLK, CS, CONV, RESET, SCLK, BP/UP/SHDN)
CLK, CS, CONV, RESET, SCLK
Input High Voltage
VIH
VDDD = 5.25V
CLK, CS, CONV, RESET, SCLK
Input Low Voltage
VIL
VDDD = 4.75V
2.4
V
CLK, CS, CONV, RESET, SCLK
Input Capacitance (Note 3)
CLK, CS, CONV, RESET, SCLK
Input Current
Digital inputs = 0 or 5V
BP/UP/SHDN
Input High Voltage
VIH
BP/UP/SHDN
Input Low Voltage
VIL
BP/UP/SHDN
Input Current, High
IIH
BP/UP/SHDN = VDDD
BP/UP/SHDN
Input Current, Low
IIL
BP/UP/SHDN = 0V
BP/UP/SHDN
Mid Input Voltage
VIM
BP/UP/SHDN Voltage,
Floating
VFLT
BP/UP/SHDN Max Allowed
Leakage, Mid Input
0.8
V
10
pF
±10
µA
VDDD - 0.5
0.5
V
4.0
µA
-4.0
1.5
µA
VDDD - 1.5
2.75
BP/UP/SHDN = open
BP/UP/SHDN = open
V
-100
V
V
+100
nA
0.4
V
±10
µA
10
pF
DIGITAL OUTPUTS (DOUT, EOC)
Output Low Voltage
VOL
VDDD = 4.75V, ISINK = 1.6mA
Output High Voltage
VOH
VDDD = 4.75V, ISOURCE = 1mA
DOUT Leakage Current
ILKG
DOUT = 0 or 5V
VDDD - 0.5
V
Output Capacitance (Note 2)
POWER REQUIREMENTS
VDDD
4.75
5.25
V
VSSD
-5.25
-4.75
V
V
VDDA
By supply-rejection test
4.75
5.25
VSSA
By supply-rejection test
-5.25
-4.75
V
VDDD Supply Current
IDDD
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V
2.5
4
mA
VSSD Supply Current
ISSD
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V
0.9
2
mA
VDDA Supply Current
IDDA
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V
3.8
5
mA
VSSA Supply Current
ISSA
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V
3.8
5
mA
_______________________________________________________________________________________
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
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A – Devices Data Sheets
MAX195
16-Bit, 85ksps ADC with 10µA Shutdown
ELECTRICAL CHARACTERISTICS (continued)
(VDDD = VDDA = +5V, VSSD = VSSA = -5V, fCLK = 1.7MHz, VREF = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical
values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
80
mW
POWER REQUIREMENTS (cont.)
Power Dissipation
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V
VDDD Shutdown Supply Current
(Note 5)
IDDD
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V,
BP/UP/SHDN = 0V
1.6
5
µA
VSSD Shutdown Supply Current
ISSD
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V,
BP/UP/SHDN = 0V
0.1
5
µA
VDDA Shutdown Supply Current
IDDA
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V,
BP/UP/SHDN = 0V
0.1
5
µA
VSSA Shutdown Supply Current
ISSA
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V,
BP/UP/SHDN = 0V
0.1
5
µA
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Accuracy and dynamic performance tests performed after calibration.
Guaranteed by design, not tested.
Tested with 50% duty cycle. Duty cycles from 25% to 75% at 1.7MHz are acceptable.
See External Clock section.
Measured in shutdown mode with CLK and SCLK low.
TIMING CHARACTERISTICS
(VDDD = VDDA = +5V, VSSD = VSSA = -5V, unless otherwise noted.)
PARAMETER
SYMBOL CONDITIONS
TA = +25°C
TYP
TA = 0°C to
+70°C
MIN
MAX
TA = -40°C to
+85°C
MIN
MAX
TA = -55°C to
+125°C
MIN
MAX
UNITS
CONV Pulse Width
tCW
CONV to CLK Falling
Synchronization (Note 2)
tCC1
10
10
10
ns
CONV to CLK Rising
Synchronization (Note 2)
tCC2
40
40
40
ns
20
30
35
ns
Data Access Time
tDV
CL = 50pF
80
80
90
ns
Bus Relinquish Time
tDH
CL = 10pF
40
40
40
ns
CLK to EOC High
tCEH
CL = 50pF
300
300
350
ns
CLK to EOC Low
tCEL
CL = 50pF
300
300
350
ns
CLK to DOUT Valid
tCD
CL = 50pF
100
350
100
375
100
400
ns
SCLK to DOUT Valid
tSD
CL = 50pF
20
140
20
160
20
160
ns
CS to SCLK Setup Time
tCSS
75
75
75
ns
CS to SCLK Hold Time
tCSH
-10
-10
-10
ns
Acquisition Time
tAQ
2.4
2.4
2.4
µs
Calibration Time
tCAL
8.2
8.2
8.2
ms
14,000 x tCLK
RESET to CLK Setup Time
tRCS
-40
-40
-40
ns
RESET to CLK Hold Time
tRCH
120
120
120
ns
Start-Up Time (Note 6)
tSU
Exiting
shutdown
50
µs
Note 6: Settling time required after deasserting shutdown to achieve less than 0.1LSB additional error.
4
262
_______________________________________________________________________________________
PN: 071-0961-00, January 2008
16-Bit, 85ksps ADC with 10µA Shutdown
PIN
1
NAME
FUNCTION
Bipolar/Unipolar/Shutdown Input. Three-state input selects bipolar or unipolar input range, or shutdown.
BP/UP/SHDN
0V = shutdown, +5V = unipolar, floating = bipolar.
2
CLK
3
SCLK
Conversion Clock Input
Serial Clock Input is used to shift data out between conversions. May be asynchronous to CLK.
4
VDDD
+5V Digital Power Supply
5
DOUT
Serial Data Output, MSB first
6
DGND
Digital Ground
7
EOC
8
CS
9
CONV
Convert-Start Input—active low. Conversion begins on the falling edge after CONV goes low if the input
signal has been acquired; otherwise, on the falling clock edge after acquisition.
10
RESET
Reset Input. Pulling RESET low places the ADC in an inactive state. Rising edge resets control logic and
begins calibration.
11
VSSD
-5V Digital Power Supply
12
REF
Reference Input, 0 to 5V
13
AIN
Analog Input, 0 to VREF unipolar or ±VREF bipolar range
14
AGND
Analog Ground
15
VSSA
-5V Analog Power Supply
16
VDDA
+5V Analog Power Supply
MAX195
______________________________________________________________Pin Description
End-of-Conversion/Calibration Output—normally low. Rises one clock cycle after the beginning of conversion
or calibration and falls one clock cycle after the end of either. May be used as an output framing signal.
Chip-Select Input—active low. Enables the serial interface and the three-state data output (DOUT).
_______________Detailed Description
The MAX195 uses a successive-approximation register
(SAR) to convert an analog input to a 16-bit digital
code, which outputs as a serial data stream. The data
bits can be read either during the conversion, at the
CLK clock rate, or between conversions asynchronous
with CLK at the SCLK rate (up to 5Mbps).
The MAX195 includes a capacitive digital-to-analog
converter (DAC) that provides an inherent track/hold
input. The interface and control logic are designed for
easy connection to most microprocessors (µPs), limiting
the need for external components. In addition to the
SAR and DAC, the MAX195 includes a serial interface, a
sampling comparator used by the SAR, ten calibration
DACs, and control logic for calibration and conversion.
The DAC consists of an array of 16 capacitors with
binary weighted values plus one “dummy LSB” capacitor (Figure 1). During input acquisition in unipolar
mode, the array’s common terminal is connected to
AGND and all free terminals are connected to the input
signal (AIN). After acquisition, the common terminal is
disconnected from AGND and the free terminals are
disconnected from AIN, trapping a charge proportional
to the input voltage on the capacitor array.
The free terminal of the MSB (largest) capacitor is connected to the reference (REF), which pulls the common
terminal (connected to the comparator) positive.
Simultaneously, the free terminals of all other capacitors in the array are connected to AGND, which drives
the comparator input negative. If the analog input is
near VREF, connecting the MSB’s free terminal to REF
only pulls the comparator input slightly positive.
However, connecting the remaining capacitor’s free terminals to ground drives the comparator input well
below ground, so the comparator input is negative, the
comparator output is low, and the MSB is set high. If
the analog input is near ground, the comparator output
is high and the MSB is low.
Following this, the next largest capacitor is disconnected from AGND and connected to REF, and the comparator determines the next bit. This continues until all
bits have been determined. For a bipolar input range,
the MSB capacitor is connected to REF rather than AIN
during input acquisition, which results in an input range
of VREF to -VREF.
_______________________________________________________________________________________
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
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263
A – Devices Data Sheets
MAX195
16-Bit, 85ksps ADC with 10µA Shutdown
MSB
LSB
32,768C
16,384C
4C
2C
DUMMY
C
C
AIN
REF
AGND
Figure 1. Capacitor DAC Functional Diagram
tCAL
CLK
tRCH
tRCS
RESET
EOC
CALIBRATION
BEGINS
CALIBRATION
ENDS
MAX195
OPERATION HALTS
Figure 2. Initiating Calibration
Calibration
In an ideal DAC, each of the capacitors associated with
the data bits would be exactly twice the value of the
next smaller capacitor. In practice, this results in a
range of values too wide to be realized in an economically feasible size. The capacitor array actually consists
of two arrays, which are capacitively coupled to reduce
the LSB array’s effective value. The capacitors in the
MSB array are production trimmed to reduce errors.
Small variations in the LSB capacitors contribute
insignificant errors to the 16-bit result.
Unfortunately, trimming alone does not yield 16-bit performance or compensate for changes in performance
due to changes in temperature, supply voltage, and
other parameters. For this reason, the MAX195 includes
a calibration DAC for each capacitor in the MSB array.
These DACs are capacitively coupled to the main DAC
6
264
output and offset the main DAC’s output according to
the value on their digital inputs. During calibration, the
correct digital code to compensate for the error in each
MSB capacitor is determined and stored. Thereafter,
the stored code is input to the appropriate calibration
DAC whenever the corresponding bit in the main DAC
is high, compensating for errors in the associated
capacitor.
The MAX195 calibrates automatically on power-up. To
reduce the effects of noise, each calibration experiment
is performed many times and the results are averaged.
Calibration requires about 14,000 clock cycles, or
8.2ms at the highest clock (CLK) speed (1.7MHz). In
addition to the power-up calibration, bringing RESET
low halts MAX195 operation, and bringing it high again
initiates a calibration (Figure 2).
_______________________________________________________________________________________
PN: 071-0961-00, January 2008
16-Bit, 85ksps ADC with 10µA Shutdown
MAX195
tCC1
tCC2
CLK
tCEL
tCEH
EOC
*
CONV
tCW
TRACK/HOLD
tAQ
CONVERSION
ENDS
CONVERSION
BEGINS
* THE FALLING EDGE OF CONV MUST OCCUR IN THIS REGION
Figure 3. Initiating Conversions—At least 3 CLK cycles since end of previous conversion.
If the power supplies do not settle within the MAX195’s
power-on delay (500ns minimum), power-up calibration
may begin with supply voltages that differ from the final
values and the converter may not be properly calibrated. If so, recalibrate the converter (pulse RESET low)
before use. For best DC accuracy, calibrate the
MAX195 any time there is a significant change in supply voltages, temperature, reference voltage, or clock
characteristics (see External Clock section) because
these parameters affect the DC offset. If linearity is the
only concern, much larger changes in these parameters can be tolerated.
Because the calibration data is stored digitally, there is
no need either to perform frequent conversions to maintain accuracy or to recalibrate if the MAX195 has been
held in shutdown for long periods. However, recalibration is recommended if it is likely that ambient temperature or supply voltages have significantly changed
since the previous calibration.
Digital Interface
The digital interface pins consist of BP/UP/SHDN, CLK,
SCLK, EOC, CS, CONV, and RESET.
BP/UP/SHDN is a three-level input. Leave it floating to
configure the MAX195’s analog input in bipolar mode
(AIN = -VREF to VREF) or connect it high for a unipolar
input (AIN = 0V to VREF). Bringing BP/UP/SHDN low
places the MAX195 in its 10µA shutdown mode.
A logic low on RESET halts MAX195 operation. The rising edge of RESET initiates calibration as described in
the Calibration section above.
Begin a conversion by bringing CONV low. After conversion begins, additional convert start pulses are
ignored. The convert signal must be synchronized with
CLK. The falling edge of CONV must occur during the
period shown in Figures 3 and 4. When CLK is not
directly controlled by your processor, two methods of
ensuring synchronization are to drive CONV from EOC
(continuous conversions) or to gate the conversion-start
signal with the conversion clock so that CONV can go
low only while CLK is low (Figure 5). Ensure that the
maximum propagation delay through the gate is less
than 40ns.
The MAX195 automatically ensures four CLK periods
for track/hold acquisition. If, when CONV is asserted, at
least three clock (CLK) cycles have passed since the
end of the previous conversion, a conversion will begin
on CLK’s next falling edge and EOC will go high on the
following falling CLK edge (Figure 3). If, when convert
is asserted, less than three clock cycles have passed,
a conversion will begin on the fourth falling clock edge
_______________________________________________________________________________________
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
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265
A – Devices Data Sheets
MAX195
16-Bit, 85ksps ADC with 10µA Shutdown
tCC1
tCC2
CLK
tCEL
tCEH
EOC
*
CONV
tCW
tAQ
TRACK/HOLD
CONVERSION
ENDS
CONVERSION
BEGINS
* THE FALLING EDGE OF CONV MUST OCCUR IN THIS REGION
Figure 4. Initiating Conversions—Less than 3 CLK cycles since end of previous conversion.
after the end of the previous conversion and EOC will
go high on the following CLK falling edge (Figure 4).
External Clock
The conversion clock (CLK) should have a duty cycle
between 25% and 75% at 1.7MHz (the maximum clock
frequency). For lower frequency clocks, ensure the minimum high and low times exceed 150ns. The minimum
clock rate for accurate conversion is 125Hz for temperatures up to +70°C or 1kHz at +125°C due to leakage
of the sampling capacitor array. In addition, CLK
should not remain high longer than 50ms at temperatures up to +70°C or 500µs at +125°C. If CLK is held
high longer than this, RESET must be pulsed low to initiate a recalibration because it is possible that state
information stored in internal dynamic memory may be
lost. The MAX195’s clock can be stopped indefinitely if
it is held low.
If the frequency, duty cycle, or other aspects of the
clock signal’s shape change, the offset created by coupling between CLK and the analog inputs (AIN and
REF) changes. Recalibration corrects for this offset and
restores DC accuracy.
Output Data
The conversion result, clocked out MSB first, is available on DOUT only when CS is held low. Otherwise,
DOUT is in a high-impedance state. There are two ways
to read the data on DOUT. To read the data bits as they
are determined (at the CLK clock rate), hold CS low
during the conversion. To read results between conversions, hold CS low and clock SCLK at up to 5MHz.
If you read the serial data bits as they are determined,
EOC frames the data bits (Figure 6). Conversion begins
with the first falling CLK edge, after CONV goes low
and the input signal has been acquired. Data bits are
shifted out of DOUT on subsequent falling CLK edges.
Clock data in on CLK’s rising edge or, if the clock
speed is greater than 1MHz, on the following falling
edge of CLK to meet the maximum CLK-to-DOUT timing specification. See the Operating Modes and
SPI™/QSPI™ Interfaces section for additional information. Reading the serial data during the conversion
results in the maximum conversion throughput,
because a new conversion can begin immediately after
the input acquisition period following the previous conversion.
SPI/QSPI are trademarks of Motorola Corp.
8
266
_______________________________________________________________________________________
PN: 071-0961-00, January 2008
16-Bit, 85ksps ADC with 10µA Shutdown
MAX195
START
MAX195
CONV
CLK
START
CLK
CONV
SEE DIGITAL INTERFACE SECTION
Figure 5. Gating CONV to Synchronize with CLK
CS
CONV
tCW
CLK
(CASE 1)
CLK
(CASE 2)
tCEH
tCEL
EOC
tCD
tDV
DOUT
B15 FROM PREVIOUS
CONVERSION
B15
B14
B13
B12
B2
B1
MSB
B0
LSB
CONVERSION
BEGINS
B15
tDH
CONVERSION
ENDS
CASE 1: CLK IDLES LOW, DATA LATCHED ON RISING EDGE (CPOL = 0, CPHA = 0)
CASE 2: CLK IDLES LOW, DATA LATCHED ON FALLING EDGE (CPOL = 0, CPHA = 1)
NOTE: ARROWS ON CLK TRANSITIONS INDICATE LATCHING EDGE
Figure 6. Output Data Format, Reading Data During Conversion (Mode 1)
If you read the data bits between conversions, you can:
1) count CLK cycles until the end of the conversion, or
2) poll EOC to determine when the conversion is
finished, or
3) generate an interrupt on EOC’s falling edge.
Note that the MSB conversion result appears at DOUT
after CS goes low, but before the first SCLK pulse.
Each subsequent SCLK pulse shifts out the next conversion bit. The 15th SCLK pulse shifts out the LSB.
Additional clock pulses shift out zeros.
_______________________________________________________________________________________
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A – Devices Data Sheets
MAX195
16-Bit, 85ksps ADC with 10µA Shutdown
tCONV
EOC
tCSS
CS
tCSH
SCLK
(CASE 1)
SCLK
(CASE 2)
SCLK
(CASE 3)
B15
DOUT
B14
B13
B12
B11
MSB
tDV
B3
B2
B1
B0
LSB
tSD
tDH
CASE 1: SCLK IDLES LOW, DATA LATCHED ON RISING EDGE (CPOL = 0, CPHA = 0)
CASE 2: SCLK IDLES LOW, DATA LATCHED ON FALLING EDGE (CPOL = 0, CPHA = 1)
CASE 3: SCLK IDLES HIGH, DATA LATCHED ON FALLING EDGE (CPOL = 1, CPHA = 0)
NOTE: ARROWS ON SCLK TRANSITIONS INDICATE LATCHING EDGE
Figure 7. Output Data Format, Reading Data Between Conversions (Mode 2)
+5V
-5V
0.1μF
10μF
1
2
CONVERSION
CLOCK
3
4
5
6
7
8
0.1μF
BP/UP/
SHDN
VDDA
CLK
VSSA
SCLK MAX195 AGND
VDDD
AIN
DOUT
REF
DGND
VSSD
EOC
RESET
CS
CONV
10μF
16
15
14
13
ANALOG
INPUT
12
11
REFERENCE
(0V TO VDDA)
10
9
Figure 8. MAX195 in the Simplest Operating Configuration
10
268
Data is clocked out on SCLK’s falling edge. Clock
data in on SCLK’s rising edge or, for clock speeds
above 2.5MHz, on the following falling edge to meet
the maximum SCLK-to-DOUT timing specification
(Figure 7). The maximum SCLK speed is 5MHz. See
the Operating Modes and SPI/QSPI Interfaces section
for additional information. When the conversion clock
is near its maximum (1.7MHz), reading the data after
each conversion (during the acquisition time) results
in lower throughput (about 70ksps max) than reading
the data during conversions, because it takes longer
than the minimum input acquisition time (four cycles
at 1.7MHz) to clock 16 data bits at 5Mbps. After the
data has been clocked in, leave some time (about
1µs) for any coupled noise on AIN to settle before
beginning the next conversion.
Whichever method is chosen for reading the data, conversions can be individually initiated by bringing CONV
low, or they can occur continuously by connecting EOC
to CONV. Figure 8 shows the MAX195 in its simplest
operational configuration.
______________________________________________________________________________________
PN: 071-0961-00, January 2008
16-Bit, 85ksps ADC with 10µA Shutdown
MAX195
Table 1. Low-ESR Capacitor Suppliers
COMPANY
CAPACITOR
FACTORY FAX [COUNTRY CODE]
USA TELEPHONE
Sprague
595D series,
592D series
1-603-224-1430
603-224-1961
AVX
TPS series
1-207-283-1941
800-282-4975
Sanyo
OS-CON series,
MVGX series
81-7-2070-1174
619-661-6835
Nichicon
PL series
1-708-843-2798
708-843-7500
+5V
BRIDGE
INSTRUMENTATION
AMPLIFIER
VDDA
AIN
MAX195
REF
47μF
LOW ESR
0.1μF
CERAMIC
AGND
Figure 9. Ratiometric Measurement Without an Accurate Reference
__________Applications Information
Reference
The MAX195 reference voltage range is 0V to VDDA.
When choosing the reference voltage, the MAX195’s
equivalent input noise (40µV RMS in unipolar mode,
80µVRMS in bipolar mode) should be considered. Also, if
VREF exceeds VDDA, errors will occur due to the internal
protection diodes that will begin to conduct, so use caution when using a reference near VDDA (unless VREF
and VDDA are virtually identical). V REF must never
exceed its absolute maximum rating (VDDA + 0.3V).
The MAX195 needs a good reference to achieve its
rated performance. The most important requirement is
that the reference must present a low impedance to the
REF input. This is often achieved by buffering the reference through an op amp and bypassing the REF input
with a large (1µF to 47µF), low-ESR capacitor in parallel
with a 0.1µF ceramic capacitor. Low-ESR capacitors
are available from the manufacturers listed in Table 1.
The reference must drive the main conversion DAC
capacitors as well as the capacitors in the calibration
DACs, all of which may be switching between GND and
REF at the conversion clock frequency. The total
capacitive load presented can exceed 1000pF and,
unlike the analog input (AIN), REF is sampled continuously throughout the conversion.
The first step in choosing a reference circuit is to
decide what kind of performance is required. This often
suggests compromises made in the interests of cost
and size. It is possible that a system may not require an
accurate reference at all. If a system makes a ratiometric measurement such as Figure 9’s bridge circuit, any
relatively noise-free voltage that presents a low impedance at the REF input will serve as a reference. The
+5V analog supply suffices if you use a large, lowimpedance bypass capacitor to keep REF stable during switching of the capacitor arrays. Do not place a
resistance between the +5V supply and the bypass
capacitor, because it will cause linearity errors due to
the dynamic REF input current, which typically ranges
from 300µA to 400µA.
Figure 10 shows a more typical scheme that provides
good AC accuracy. The MAX874’s initial accuracy can
______________________________________________________________________________________
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
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A – Devices Data Sheets
MAX195
16-Bit, 85ksps ADC with 10µA Shutdown
+15V
+5V
0.1μF
2
0.1μF
1k
VIN
16
VDDA
2k
COMP
2
6
0.1μF
7
1000pF
MAX874
VOUT
1N914
8
4.096V
3
12
MAX427
REF
10Ω
47μF
LOW ESR
4
0.1μF
GND
MAX195
10Ω
6
0.1μF
1N914
VSSA
AGND
15
14
0.1μF
4
-15V
-5V
Figure 10. Typical Reference Circuit for AC Accuracy
VIN ≥ 8V
2
IN
MAX6241
OUT
12
6
MAX195
REF
2.2μF
3
1μF
TRIM
NR
5
GND
4
10k
2.2μF
0.1μF
AGND
14
Figure 11. High-Accuracy Reference
be improved by trimming, but the drift is too great to
provide good stability over temperature. The MAX427
buffer provides the necessary drive current to stabilize
the REF input quickly after capacitance changes.
The reference inaccuracies contribute additional fullscale error. A reference with less than 1⁄216 total error
(15 parts per million) over the operating temperature
range is required to limit the additional error to less
than 1LSB. The MAX6241 achieves a drift specification
12
270
of 1ppm/°C (typ). This allows reasonable temperature
changes with less than 1LSB error. While the
MAX6241’s initial-accuracy specification (0.02%)
results in an offset error of about ±14LSB, the reference
voltage can be trimmed or the offset can be corrected
in software if absolute DC accuracy is essential. Figure
11’s circuit provides outstanding temperature stability
and also provides excellent DC accuracy if the initial
error is corrected.
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16-Bit, 85ksps ADC with 10µA Shutdown
MAX195
+5V
+15V
VDDA
MAX195
10Ω
AIN
INPUT
SIGNAL
1N914
DIODE
CLAMPS
VSSA
-15V
-5V
Figure 12. Analog Input Protection for Overvoltage or Improper Supply Sequence
REF and AIN Input Protection
The REF and AIN signals should not exceed the
MAX195 supply rails. If this can occur, diode clamp the
signal to the supply rails. Use silicon diodes and a 10Ω
current-limiting resistor (Figures 10 and 12) or Schottky
diodes without the resistor.
When using the current-limiting resistor, place the resistor between the appropriate input (AIN or REF) and any
bypass capacitor. While this results in AC transients at
the input due to dynamic input currents, the transients
settle quickly and do not affect conversion results.
Improperly placing the bypass capacitor directly at the
input forms an RC lowpass filter with the current-limiting
resistor, which averages the dynamic input current and
causes linearity errors.
Analog Input
The MAX195 uses a capacitive DAC that provides an
inherent track/hold function. The input impedance is
typically 30Ω in series with 250pF in unipolar mode and
50Ω in series with 125pF in bipolar mode.
Input Range
The analog input range can be either unipolar (0V to
VREF) or bipolar (-VREF to VREF), depending on the
state of the BP/UP/SHDN pin (see Digital Interface section). The reference range is 0V to VDDA. When choosing the reference voltage, the equivalent MAX195 input
noise (40µVRMS in unipolar mode, 80µVRMS in bipolar
mode) should be considered.
Input Acquisition and Settling
Four conversion-clock periods are allocated for acquiring the input signal. At the highest conversion rate, four
clock periods is 2.4µs. If more than three clock cycles
have occurred since the end of the previous conversion, conversion begins on the next falling clock edge
after CONV goes low. Otherwise, bringing CONV low
begins a conversion on the fourth falling clock edge
after the previous conversion. This scheme ensures the
minimum input acquisition time is four clock periods.
Most applications require an input buffer amplifier. If
the input signal is multiplexed, the input channel should
be switched near the beginning of a conversion, rather
than near the end of or after a conversion (Figure 13).
This allows time for the input buffer amplifier to respond
to a large step change in input signal. The input amplifier must have a high enough slew rate to complete the
required output voltage change before the beginning of
the acquisition time.
At the beginning of acquisition, the capacitive DAC is
connected to the amplifier output, causing some output
disturbance. Ensure that the sampled voltage has settled to within the required limits before the end of the
acquisition time. If the frequency of interest is low, AIN
can be bypassed with a large enough capacitor to
charge the capacitive DAC with very little change in
voltage (Figure 14). However, for AC use, AIN must be
driven by a wideband buffer (at least 10MHz), which
must be stable with the DAC’s capacitive load (in parallel with any AIN bypass capacitor used) and also must
settle quickly (Figure 15 or 16).
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A – Devices Data Sheets
MAX195
16-Bit, 85ksps ADC with 10µA Shutdown
IN1
IN2
A0
A1
MAX195
4-TO-1
MUX
IN3
AIN
OUT
IN4
EOC
CLK
CONVERSION
ACQUISITION
EOC
A0
A1
CHANGE MUX INPUT HERE
Figure 13. Change multiplexer input near beginning of conversion to allow time for slewing and settling.
1k
+5V
+15V
0.1μF
2
1000pF
1N914
7
10Ω
6
IN
AIN
3 MAX400
100Ω
4
1N914
0.1μF
-15V
1.0μF
-5V
Figure 14. MAX400 Drives AIN for Low-Frequency Use
14
272
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16-Bit, 85ksps ADC with 10µA Shutdown
ing. Also, to reduce linearity errors due to finite amplifier
gain, use an amplifier circuit with sufficient loop gain at
the frequencies of interest (Figures 14, 15, 16).
DC Accuracy
If DC accuracy is important, choose a buffer with an
offset much less than the MAX195’s maximum offset
(±3LSB = ±366µV for a ±4V input range), or whose
offset can be trimmed while maintaining good stability
over the required temperature range.
MAX195
Digital Noise
Digital noise can easily be coupled to AIN and REF. The
conversion clock (CLK) and other digital signals that are
active during input acquisition contribute noise to the conversion result. If the noise signal is synchronous to the
sampling interval, an effective input offset is produced.
Asynchronous signals produce random noise on the input,
whose high-frequency components may be aliased into
the frequency band of interest. Minimize noise by presenting a low impedance (at the frequencies contained in the
noise signal) at the inputs. This requires bypassing AIN to
AGND, or buffering the input with an amplifier that has a
small-signal bandwidth of several megahertz, or preferably both. AIN has a bandwidth of about 16MHz.
Recommended Circuits
Figure 14 shows a good circuit for DC and low-frequency use. The MAX400 has very low offset (10µV) and
drift (0.2µV/°C), and low voltage noise (10nV/√Hz) as
well. However, its gain-bandwidth product (GBW) is
much too low to drive AIN directly, so the analog input
is bypassed to present a low impedance at high frequencies. The large bypass capacitor is isolated from
the amplifier output by a 100Ω resistor, which provides
additional noise filtering. Since the ±15V supplies
exceed the AIN range, add protection diodes at AIN
(see REF and AIN Input Protection section).
Figure 15 shows a wide-bandwidth amplifier (MAX427)
driving a wideband video buffer, which is capable of
driving AIN and a small bypass capacitor (for noise
reduction) directly. The video buffer is inside the
MAX427’s feedback loop, providing good DC accuracy, while the buffer’s low output impedance and highcurrent capability provide good AC performance. AIN is
diode-clamped to the ±5V rails to prevent overvoltage.
The MAX427’s 15µV maximum offset voltage, 0.8µV/°C
maximum drift, and less than 5nV/√Hz noise specifications make this an excellent choice for AC/DC use.
Offsets resulting from synchronous noise (such as the
conversion clock) are canceled by the MAX195’s calibration scheme. However, because the magnitude of
the offset produced by a synchronous signal depends
on the signal’s shape, recalibration may be appropriate
if the shape or relative timing of the clock or other digital signals change, as might occur if more than one
clock signal or frequency is used.
Distortion
Avoid degrading dynamic performance by choosing an
amplifier with distortion much less than the MAX195’s
THD (-97dB, or 0.0014%) at frequencies of interest. If
the chosen amplifier has insufficient common-mode
rejection, which results in degraded THD performance,
use the inverting configuration (positive input grounded) to eliminate errors from this source. Low temperature-coefficient, gain-setting resistors reduce linearity
errors caused by resistance changes due to self-heat-
1k
0.1μF
2
100pF
0.1μF
7
1N914
1
2
6
IN
+5V
+15V
+15V
3 MAX427
1k
ELANTEC
EL2003
10Ω
7
AIN
4
4
0.1μF
-15V
1N914
0.0033μF
0.1μF
-15V
-5V
Figure 15. AIN Buffer for AC/DC Use
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A – Devices Data Sheets
MAX195
16-Bit, 85ksps ADC with 10µA Shutdown
If ±15V supplies are unavailable, Figure 16’s circuit
works very well with the ±5V analog supplies used by
the MAX195. The MAX410 has a minimum ±3.5V common-mode input range, with a similar output voltage
swing, which allows use of a reference voltage up to
3.5V. The offset voltage (250µV) is about 2LSB. The
drift (1µV/°C), unity-gain bandwidth (28MHz), and low
voltage noise (2.4nV/√Hz) are appropriate for 16-bit
performance.
510Ω
+5V
0.1μF
2
7
22Ω
6
IN
AIN
3 MAX410
4
0.01μF
0.1μF
-5V
Figure 16. ±5V Buffer for AC/DC Use Has ±3.5V Swing
QSPI
PCS0
CS
CONV
SCK
MISO
CLK MAX195
DOUT
SCLK
GPT
*OC3
*IC1
*OC2
BP/UP/SHDN
EOC
RESET
* THE USE OF THESE SIGNALS ADDS FLEXIBILITY AND FUNCTIONALITY
BUT IS NOT REQUIRED TO IMPLEMENT THE INTERFACE.
Figure 17. MAX195 Connection to QSPI Processor Clocking
Data Out During Conversions
16
274
Operating Modes and SPI/QSPI Interfaces
The two basic interface modes are defined according
to whether serial data is received during the conversion
(clocked with CLK, SCLK unused) or in bursts between
conversions (clocked with SCLK). Each mode is presented interfaced to a QSPI processor, but is also compatible with SPI.
Mode 1 (Simultaneous
Conversion and Data Transfer)
In this mode, each data bit is read from the MAX195
during the conversion as it is determined. SCLK is
grounded and CLK is used as both the conversion
clock and the serial data clock. Figure 17 shows a
QSPI processor connected to the MAX195 for use in
this mode and Figure 18 is the associated timing diagram.
In addition to the standard QSPI interface signals, general I/O lines are used to monitor EOC and to drive
BP/UP/SHDN and RESET. The two general output pins
may not be necessary for a given application and, if I/O
lines are unavailable, the EOC connection can be omitted as well.
The EOC signal is monitored during calibration to
determine when calibration is finished and before
beginning a conversion to ensure the MAX195 is not in
mid-conversion, but it is possible for a system to ignore
EOC completely. On power-up or after pulsing RESET
low, the µP must provide 14,000 CLK cycles to complete the calibration sequence (Figure 2). One way to
do this is to toggle CLK and monitor EOC until it goes
low, but it is possible to simply count 14,000 CLK
cycles to complete the calibration. Similarly, it is
unnecessary to check the status of EOC before beginning a conversion if you are sure the last conversion is
complete. This can be done by ensuring that every
conversion consists of at least 20 CLK cycles.
Data is clocked out of the MAX195 on CLK’s falling
edge and can be clocked into the µP on the rising
edge or the following falling edge. If you clock data in
on the rising edge (SPI/QSPI with CPOL = 0 and CPHA
= 0; standard MicroWire™: Hitachi H8), the maximum
CLK rate is given by:
⎛
⎞
1
fCLK(max) = 1/ 2 ⎜
⎟
⎝ t CD + t SD ⎠
where tCD is the MAX195’s CLK-to-DOUT valid delay
and tSD is the data setup time for your µP.
MicroWire is a trademark of National Semiconductor Corp.
______________________________________________________________________________________
PN: 071-0961-00, January 2008
16-Bit, 85ksps ADC with 10µA Shutdown
MAX195
CS, CONV
CLK
EOC
B15 FROM PREVIOUS
CONVERSION
DOUT
B15
tDV
B14
B2
B1
B0
B15
tDH
tCD
DATA LATCHED:
Figure 18. Timing Diagram for Circuit of Figure 17 (Mode 1)
If clocking data in on the falling edge (CPOL = 0,
CPHA = 1), the maximum CLK rate is given by:
1
fCLK(max) =
t CD + t SD
QSPI
PCS0
GPT
Do not exceed the maximum CLK frequency given in
the Electrical Characteristics table. To clock data in on
the falling edge, your processor hold time must not
exceed tCD minimum (100ns).
While QSPI can provide the required 20 CLK cycles as
two continuous 10-bit transfers, SPI is limited to 8-bit
transfers. This means that with SPI, a conversion must
consist of three 8-bit transfers. Ensure that the pauses
between 8-bit operations at your selected clock rate
are short enough to maintain a 20ms or shorter conversion time, or the leakage of the capacitive DAC may
cause errors.
Complete source code for the Motorola 68HC16 and
the MAX195 evaluation kit (EV kit) using this mode is
available with the MAX195 EV kit.
CS
SCK
SCLK
MISO
DOUT
OC3
MAX195
BP/UP/SHDN
IC1
EOC
OC2
RESET
CONV
IC3
CLK
74HC32
1.7MHz
1.3μs
START
Figure 19. MAX195 Connection to QSPI Processor Clocking
Data Out with SCLK Between Conversions
Mode 2 (Asynchronous Data Transfer)
This mode uses a conversion clock (CLK) and a serial
clock (SCLK). The serial data is clocked out between
conversions, which reduces the maximum throughput
for high CLK rates, but may be more convenient for
some applications. Figure 19 is a block diagram with a
QSPI processor (Motorola 68HC16) connected to the
MAX195. Figure 20 shows the associated timing diagram. Figure 21 gives an assembly language listing for
this arrangement.
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A – Devices Data Sheets
MAX195
16-Bit, 85ksps ADC with 10µA Shutdown
588ns
CLK
START
EOC
CS
239ns
4.19MHz
SCLK
B15
DOUT
1.3μs
CONVERSION TIME
9.4μs
17μs*
B14 B13
B3 B2
5.1μs
B1
B0
4μs
* INTERRUPT LATENCY OF THE PROCESSOR
Figure 20. Timing Diagram for Circuit of Figure 19 (Mode 2)
An OR gate is used to synchronize the “start” signal to
the asynchronous CLK, as described in the External
Clock section. As with Mode 1, the QSPI processor must
run CLK during calibration and either count CLK cycles
or, as is done here, monitor EOC to determine when calibration is complete. Also, EOC is polled by the µP to
determine when a conversion result is available. When
EOC goes low, data is clocked out at the highest QSPI
data rate (4.19Mbps). After the data is transferred, a
new conversion can be initiated whenever desired.
The timing specification for SCLK-to-DOUT valid (tSD)
imposes some constraints on the serial interface. At
SCLK rates up to 2.5Mbps, data is clocked out of the
MAX195 by a falling edge of SCLK and may be
clocked into the µP by the next rising edge (CPOL = 0,
CPHA = 0). For data rates greater than 2.5Mbps (or for
lower rates, if desired) it is necessary to clock data out
of the MAX195 on SCLK’s falling edge and to clock it
into the µP on SCLK’s next falling edge (CPOL = 0,
CPHA = 1). Also, your processor hold time must not
exceed tSD minimum (20ns). As with CLK in mode 1,
maximum SCLK rates may not be possible with some
interface specifications that are subsets of SPI.
18
276
Supplies, Layout, Grounding
and Bypassing
For best system performance, use printed circuit
boards with separate analog and digital ground planes.
Wire-wrap boards are not recommended. The two
ground planes should be tied together at the lowimpedance power-supply source and at the MAX195
(Figure 22.) If the analog and digital supplies come
from the same source, isolate the digital supply from
the analog supply with a low-value resistor (10Ω).
Constraints on sequencing the four power supplies are
as follows.
• Apply VDDA before VDDD.
• Apply VSSA before VSSD.
• Apply AIN and REF after VDDA and VSSA are present.
• The power supplies should settle within the
MAX195’s power-on delay (minimum 500ns) or you
should recalibrate the converter (pulse RESET low)
before use.
______________________________________________________________________________________
PN: 071-0961-00, January 2008
16-Bit, 85ksps ADC with 10µA Shutdown
MAX195
Figure 21. MAX195 Code Listing for 68HC16 Module and Circuit of Figure 19
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A – Devices Data Sheets
MAX195
16-Bit, 85ksps ADC with 10µA Shutdown
Figure 21. MAX195 Code Listing for 68HC16 Module and Circuit of Figure 19 (continued)
20
278
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16-Bit, 85ksps ADC with 10µA Shutdown
MAX195
Figure 21. MAX195 Code Listing for 68HC16 Module and Circuit of Figure 19 (continued)
Be sure that digital return currents do not pass through
the analog ground and that return-current paths are low
impedance. A 5mA current flowing through a PC board
ground trace impedance of only 0.05Ω creates an error
voltage of about 250µV, or about 2LSBs error with a
±4V full-scale system.
The board layout should ensure as much as possible
that digital and analog signal lines are kept separate.
Do not run analog and digital (especially clock) lines
parallel to one another. If you must cross one with the
other, do so at right angles.
The ADC’s high-speed comparator is sensitive to highfrequency noise on the VDDA and VSSA power supplies. Bypass these supplies to the analog ground
plane with 0.1µF in parallel with 1µF or 10µF low-ESR
capacitors. Keep capacitor leads short for best supplynoise rejection.
Shutdown
The MAX195 may be shut down by pulling BP/UP/
SHDN low. In addition to lowering power dissipation to
10µW (100µW max) when the device is not in use, you
can save considerable power by shutting the converter
down for short periods between conversions. There is
no need to perform a reset (calibration) after the converter has been shut down unless the time in shutdown
is long enough that the supply voltages or ambient temperature may have changed.
The time required for the converter to “wake up” and
settle depends heavily on the amount of additional error
acceptable. For 0.5LSB additional error, 3.2µs is sufficient settling time and also allows enough time for reacquisition of the analog input signal. 50µs settling is
required for less than 0.1LSB error. Figure 23 is a
graph of theoretical power consumption vs. conversions per second for the MAX195 that assumes the
conversion clock is 1.7MHz and the converter is shut
down as much as possible between conversions.
Stop CLK before shutting down the MAX195. CLK must
be stopped without generating short clock pulses. Short
CLK pulses (less than 150ns), or shutting down the
MAX195 without stopping CLK, may adversely affect the
MAX195’s internal calibration data. In applications
where CLK is free-running and asynchronous, use the
circuit of Figure 24 to stop CLK cleanly.
To minimize the time required to settle and perform a
conversion, shut the converter down only after a conversion is finished and the desired mode (unipolar or
bipolar) has been set. This ensures that the sampling
capacitor array is properly connected to the input signal. If shut down in mid-conversion, when awakened,
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279
A – Devices Data Sheets
MAX195
16-Bit, 85ksps ADC with 10µA Shutdown
10Ω
VDDD
0.1μF
MAX195
0.1μF
10μF
DGND
AGND
10μF
5V
0.1μF
10μF
POWER DISSIPATION (mW)
5V
MAX195-FIG23
100
50μs WAKE-UP DELAY
0.01LSB ERROR
VDDA
10μF
10
20μs WAKE-UP DELAY
0.25LSB ERROR
1
0.1
3.2μs WAKE-UP DELAY
0.5LSB ERROR
0.1μF
VSSA
0.01
1
VSSD
10
100
1000
10,000 100,000
CONVERSIONS PER SECOND
10Ω
Figure 22. Supply Bypassing and Grounding
Figure 23. Power Dissipation vs. Conversions/sec When
Shutting the MAX195 Down Between Conversions
the MAX195 finishes the old conversion, allows four
clock (CLK) cycles for input acquisition, then begins
the new conversion.
The theoretical minimum ADC noise is caused by quantization error and is a direct result of the ADC’s resolution: SNR = (6.02N + 1.76)dB, where N is the number
of bits of resolution. A perfect 16-bit ADC can, therefore, do no better than 98dB. An FFT plot of the output
shows the output level in various spectral bands. Figure
25 shows the result of sampling a pure 1kHz sinusoid at
85ksps with the MAX195.
By transposing the equation that converts resolution to
SNR, we can, from the measured SNR, determine the
effective resolution or the “effective number of bits” the
ADC provides: N = (SNR - 1.76) / 6.02. Substituting
SINAD for SNR in this formula results in a better measure of the ADC’s usefulness. Figure 26 shows the
effective number of bits as a function of the MAX195’s
input frequency calculated from the SINAD.
If your intended sample rate is much lower than the
MAX195’s maximum of 85ksps, you can improve your
noise performance by taking more samples than necessary (oversampling) and averaging them in software.
Figure 27 is a histogram showing 16,384 samples for
the MAX195 without averaging, with an ideal “noiseless
conversion,” and with a running average of five samples. The standard deviation is 0.621LSB without averaging and 0.382LSB with the running average. If fewer
data points are needed, normal averaging (e.g., five
data points averaged to produce one data point) can be
used instead of a running average, with similar results.
_____________Dynamic Performance
High-speed sampling capability, 85ksps throughput,
and wide dynamic range make the MAX195 ideal for
AC applications and signal processing. To support
these and other related applications, Fast Fourier
Transform (FFT) test techniques are used to guarantee
the ADC’s dynamic frequency response, distortion, and
noise at the rated throughput. Specifically, this involves
applying a low-distortion sine wave to the ADC input
and recording the digital conversion results for a
specified time. The data is then analyzed using an FFT
algorithm, which determines its spectral content.
Conversion errors are then seen as spectral elements
other than the fundamental input frequency.
Signal-to-Noise Ratio and
Effective Number of Bits
Signal-to-Noise Ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency to
the RMS amplitude of all other ADC output signals. The
output band is limited to frequencies above DC and
below one-half the ADC sample rate. This usually (but
not always) includes distortion as well as noise components. For this reason, the ratio is sometimes referred to
as Signal-to-Noise + Distortion (SINAD).
22
280
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16-Bit, 85ksps ADC with 10µA Shutdown
MAX195
1/2 74HC73
MAX195
J
CLOCK SHUTDOWN
Q
CLK
K
+5V
BP/UP/SHDN
CK
2 x CLK
CK
(2 x CLK)
Q
(CLK)
J
(CLOCK SHUTDOWN)
Figure 24. Circuit to Stop Free-Running Asynchronous CLK
Even better than oversampling and averaging is oversampling and digital filtering. Averaging is just a rough
(but computationally simple) type of digital filter. Finite
impulse response (and other) digital filter algorithms are
readily available, and are useful even with slow processors if the data rate is low or the data does not need to
be processed in real-time. When using averaging, be
sure to average an odd number of samples to avoid
small offset errors caused by asymmetrical rounding.
SIGNAL AMPLITUDE (dB)
-10
fIN = 1kHz
fS = 85kHz
TA = +25°C
-30
-50
-70
-90
-110
-130
-150
0
5
10
15
20
25
FREQUENCY (kHz)
Figure 25. MAX195 FFT Plot
30
35
40
Whether simple averaging or more complex digital filtering is used, the effect of oversampling is to spread
the noise across a wider bandwidth. Digital filtering or
averaging then eliminates the portion of this noise that
lies above the filter’s passband, leaving less noise in
the passband than if oversampling was not used. An
additional benefit of oversampling is that it simplifies
the design or choice of an anti-aliasing pre-filter for the
input. You can use a filter with a more gradual rolloff,
because the sample rate is much higher than the frequency of interest.
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A – Devices Data Sheets
fS = 85kHz
TA = +25°C
15
100
MAX195-26
16
MAX195-28
MAX195
16-Bit, 85ksps ADC with 10µA Shutdown
fS = 85kHz
TA = +25°C
95
SINAD (dB)
EFFECTIVE BITS
90
14
13
12
85
80
75
70
11
65
10
0.1
60
1
10
100
0.1
FREQUENCY (kHz)
16
IDEAL
CONVERSION
14
VREF = +4.5V
VAIN = +2.25V
UNIPOLAR MODE
85ksps
MAX195 FG27
OCCURRENCES OF OUTPUT CODE (THOUSANDS)
100
This is expressed as follows:
18
12
10
8
6
NO AVERAGING
RUNNING
AVERAGE OF
5 SAMPLES
4
2
0
8021 8022 8023 8024 8025 8026 8027
OUTPUT CODE (HEXADECIMAL)
Figure 27. Histogram of 16,384 Conversions Shows Effects of
Noise and Averaging
Total Harmonic Distortion
If a pure sine wave is input to an ADC, AC integral nonlinearity (INL) of an ADC’s transfer function results in
harmonics of the input frequency being present in the
sampled output data.
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all the harmonics (in the frequency band above
DC and below one-half the sample rate, but not including the DC component) to the RMS amplitude of the
fundamental frequency.
282
10
Figure 28. Signal-to-Noise + Distortion vs. Frequency
Figure 26. Effective Bits vs. Input Frequency
24
1
FREQUENCY (kHz)
THD = 20log
⎛ V22 + V32 + V4 2 + ...+ V 2 ⎞
N ⎠
⎝
V1
where V1 is the fundamental RMS amplitude, and V 2
through VN are the amplitudes of the 2nd through Nth
harmonics. The THD specification in the Electrical
Characteristics includes the 2nd through 5th harmonics. In the MAX195, this distortion is caused primarily
by the changes in on-resistance of the AIN sampling
switches with changing input voltage. These resistance changes, together with the DAC’s capacitance
(which can also vary with input voltage), cause a
varying time delay for AC signals, which causes significant distortion at moderately high frequencies
(Figure 28).
Spurious-Free Dynamic Range
Spurious-free dynamic range is the ratio of the fundamental RMS amplitude to the amplitude of the next
largest spectral component (in the frequency band
above DC and below one-half the sample rate).
Usually, this peak occurs at some harmonic of the input
frequency. However, if the ADC is exceptionally linear,
it may occur only at a random peak in the ADC’s noise
floor.
Transfer Function
Figures 29 and 30 show the MAX195’s transfer functions. In unipolar mode, the output data is in binary format and in bipolar mode it is offset binary.
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16-Bit, 85ksps ADC with 10µA Shutdown
11 . . . 111
11 . . . 110
11 . . . 101
11 . . . 100
11 . . . 011
11 . . . 010
BP/UP/SHDN
VSSA
CLK
VDDA
SCLK
AGND
00 . . . 110
00 . . . 101
00 . . . 100
00 . . . 011
00 . . . 010
00 . . . 001
00 . . . 000
MAX195
___________________Chip Topography
AIN
REF
VREF - (1LSB)
0V
0.273"
(6.93mm)
VDDD
Figure 29. MAX195 Unipolar Transfer Function
DOUT
11 . . . 111
11 . . . 110
11 . . . 101
DGND
VSSD
EOC
10 . . . 010
10 . . . 001
10 . . . 000
01 . . . 111
01 . . . 110
CS
CONV
RESET
0.144"
(3.66mm)
TRANSISTOR COUNT: 7966
SUBSTRATE CONNECTED TO VDDA
00 . . . 010
00 . . . 001
00 . . . 000
-VREF
0V
VREF - (1LSB)
Figure 30. MAX195 Bipolar Transfer Function
______________________________________________________________________________________
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
25
283
A – Devices Data Sheets
________________________________________________________Package Information
PDIPN.EPS
MAX195
16-Bit, 85ksps ADC with 10µA Shutdown
26
284
______________________________________________________________________________________
PN: 071-0961-00, January 2008
16-Bit, 85ksps ADC with 10µA Shutdown
SOICW.EPS
______________________________________________________________________________________
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
MAX195
___________________________________________Package Information (continued)
27
285
A – Devices Data Sheets
___________________________________________Package Information (continued)
SBN.EPS
MAX195
16-Bit, 85ksps ADC with 10µA Shutdown
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
28 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 1998 Maxim Integrated Products
286
Printed USA
is a registered trademark of Maxim Integrated Products.
PN: 071-0961-00, January 2008
B
Loadboard Schematic Extracts
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
287
B – Loadboard Schematic Extracts
288
PN: 071-0961-00, January 2008
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
289
B – Loadboard Schematic Extracts
Notes
290
PN: 071-0961-00, January 2008
C
VHDM Connector Pinouts
Figure 99. DD1096-16 VHDM Connector Pinout
DUT B Connector
Pin
A
B
GND
1
N/C
GND
N/C
GND
2
CH 90
CH 78
CH 79
5
CH 72
CH 73
GND
6
CH 66
CH 67
GND
7
CH 60
CH 61
GND
8
CH 54
CH 55
GND
9
CH 48
CH 49
GND
10
SCOPE TP4
N/C
A
B
C
CH 65
GND
CH 58
GND
CH 51
GND
SCOPE TP3
CH 64
CH 57
CH 50
CH 71
GND
GND
GND
GND
CH 70
CH 63
CH 56
CH 77
GND
GND
GND
GND
CH 76
CH 69
CH 62
CH 83
GND
GND
GND
GND
CH 82
CH 75
CH 68
CH 89
GND
GND
GND
GND
CH 88
CH 81
CH 74
CH 95
GND
GND
GND
GND
CH 94
CH 87
CH 80
GND SENSE F
GND
GND
GND
GND
N/C
CH 93
CH 86
F
GND
GND
GND
GND
GND
N/C
CH 92
CH 85
E
GND
GND
GND
GND
4
N/C
CH 91
CH 84
D
GND
GND
GND
3
C
CH 59
GND
CH 52
GND
GND SENSE D
CH 53
GND
GND SENSE E
LB SENSE
E
F
DUT A Connector
Pin
GND
1
SCOPE TP1
GND
SCOPE TP2
GND
2
CH 42
3
CH 43
CH 36
CH 30
CH 31
5
CH 24
CH 25
GND
6
CH 18
CH 19
GND
7
CH 12
CH 13
GND
8
CH 6
CH 7
GND
9
CH 0
CH 1
GND
10
N/C
N/C
CH 10
CH 3
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
CH 11
GND
CH 4
GND
N/C
CH 17
GND
GND
GND
N/C
CH 16
CH 9
CH 2
CH 23
GND
GND
GND
GND
CH 22
CH 15
CH 8
CH 29
GND
GND
GND
GND
CH 28
CH 21
CH 14
CH 35
GND
GND
GND
GND
CH 34
CH 27
CH 20
CH 41
GND
GND
GND
GND
CH 40
CH 33
CH 26
CH 47
GND
GND
GND
GND
CH 46
CH 39
CH 32
GND SENSE C
GND
GND
GND
GND
N/C
CH 45
CH 38
GND
GND
GND
GND
GND
N/C
CH 44
CH 37
GND
GND
GND
GND
4
N/C
GND
GND
D
GND
CH 5
GND
GND SENSE A
GND SENSE B
291
C – VHDM Connector Pinouts
Figure 100. DPS16 VHDM Connector Pinout
DUT B Connector
Pin
A
B
GND
1
N/C
GND
N/C
GND
2
VSENSE- 15
VSENSE- 13
IDDQ SW 13
5
VSENSE- 12
IDDQ SW 12
GND
6
VSENSE- 11
IDDQ SW 11
GND
7
VSENSE- 10
IDDQ SW 10
GND
8
VSENSE- 9
IDDQ SW 9
GND
9
VSENSE- 8
IDDQ SW 8
GND
10
N/C
N/C
A
B
C
OUTPUT 10
GND
OUTPUT 9
GND
OUTPUT 8
GND
N/C
OUTPUT 10
OUTPUT 9
VSENSE+ 8
OUTPUT 11
GND
GND
GND
GND
OUTPUT 11
OUTPUT 10
VSENSE+ 9
OUTPUT 12
GND
GND
GND
GND
OUTPUT 12
OUTPUT 11
VSENSE+ 10
OUTPUT 13
GND
GND
GND
GND
OUTPUT 13
OUTPUT 12
VSENSE+ 11
OUTPUT 14
GND
GND
GND
GND
OUTPUT 14
OUTPUT 13
VSENSE+ 12
OUTPUT 15
GND
GND
GND
GND
OUTPUT 15
OUTPUT 14
VSENSE+ 13
N/C
GND
GND
GND
GND
N/C
OUTPUT 15
VSENSE+ 14
F
GND
GND
GND
GND
GND
N/C
VSENSE+ 15
IDDQ SW 14
E
GND
GND
GND
GND
4
N/C
IDDQ SW 15
VSENSE- 14
D
GND
GND
GND
3
C
OUTPUT 9
GND
OUTPUT 8
GND
N/C
OUTPUT 8
GND
N/C
N/C
DUT A Connector
Pin
GND
1
N/C
GND
N/C
GND
2
VSENSE- 7
3
IDDQ SW 7
VSENSE- 6
VSENSE- 5
IDDQ SW 5
5
VSENSE- 4
IDDQ SW 4
GND
6
VSENSE- 3
IDDQ SW 3
GND
7
VSENSE- 2
IDDQ SW 2
GND
8
VSENSE- 1
IDDQ SW 1
GND
9
VSENSE- 0
IDDQ SW 0
GND
10
292
N/C
N/C
N/C
N/C
OUTPUT 2
OUTPUT 1
OUTPUT 1
OUTPUT 0
OUTPUT 1
GND
OUTPUT 0
GND
N/C
OUTPUT 2
GND
GND
GND
OUTPUT 3
GND
GND
GND
VSENSE+ 0
GND
OUTPUT 3
OUTPUT 2
VSENSE+ 1
OUTPUT 4
GND
GND
GND
GND
OUTPUT 4
OUTPUT 3
VSENSE+ 2
OUTPUT 5
GND
GND
GND
GND
OUTPUT 5
OUTPUT 4
VSENSE+ 3
OUTPUT 6
GND
GND
GND
GND
OUTPUT 6
OUTPUT 5
VSENSE+ 4
OUTPUT 7
GND
GND
GND
GND
OUTPUT 7
OUTPUT 6
VSENSE+ 5
N/C
GND
GND
GND
GND
N/C
OUTPUT 7
VSENSE+ 6
F
GND
GND
GND
GND
GND
N/C
VSENSE+ 7
IDDQ SW 6
E
GND
GND
GND
GND
4
N/C
GND
GND
D
GND
OUTPUT 0
GND
N/C
N/C
PN: 071-0961-00, January 2008
Figure 101. VIS16 VHDM Connector Pinout
DUT B Connector
Pin
A
B
C
AGND
1
N/C
LO_S_CH15
GUARD_CH15
3
LO_S_CH14
4
LO_S_CH13
LO_S_CH12
GUARD_CH12
HI_F_CH14
HI_F_CH13
HI_S_CH12
HI_F_CH14
LO_F_CH13
HI_F_CH13
LO_F_CH12
HI_F_CH12
LO_F_CH11
HI_F_CH15
LO_F_CH14
LO_F_CH13
LO_F_CH12
LO_F_CH11
HI_F_CH15
HI_F_CH14
HI_S_CH13
N/C
LO_F_CH15
LO_F_CH14
LO_F_CH13
LO_F_CH12
LO_F_CH11
HI_F_CH15
HI_S_CH14
GUARD_CH13
N/C
LO_F_CH15
LO_F_CH14
LO_F_CH13
LO_F_CH12
5
HI_S_CH15
GUARD_CH14
LO_F_CH13
AGND
N/C
LO_F_CH15
LO_F_CH14
F
AGND
N/C
LO_F_CH15
LO_F_CH14
E
AGND
N/C
LO_F_CH15
2
D
AGND
HI_F_CH13
LO_F_CH12
HI_F_CH12
LO_F_CH11
HI_F_CH12
LO_F_CH11
6
LO_S_CH11
GUARD_CH11
HI_S_CH11
HI_F_CH11
HI_F_CH11
HI_F_CH11
LO_F_CH10
LO_F_CH10
LO_F_CH10
LO_F_CH10
LO_F_CH10
7
LO_S_CH10
GUARD_CH10
LO_F_CH9
8
LO_S_CH9
GUARD_CH9
LO_F_CH8
9
LO_S_CH8
HI_F_CH10
LO_F_CH9
HI_S_CH9
LO_F_CH8
GUARD_CH8
AGND
10
HI_S_CH10
LO_F_CH9
HI_F_CH9
LO_F_CH8
HI_S_CH8
AGND
HI_F_CH10
LO_F_CH9
HI_F_CH9
LO_F_CH8
HI_F_CH8
AGND
CALS_SL
CALS_FL
N/C
CAL_LO_GRD
A
B
C
HI_F_CH10
LO_F_CH9
HI_F_CH9
LO_F_CH8
HI_F_CH8
AGND
CALS_SH
HI_F_CH8
AGND
CALS_FH
CAL_HI_GRD
N/C
DUT A Connector
Pin
AGND
1
N/C
2
LO_S_CH7
GUARD_CH6
AGND
N/C
LO_F_CH7
HI_S_CH7
LO_F_CH6
N/C
LO_F_CH7
HI_F_CH7
LO_F_CH6
N/C
LO_F_CH7
HI_F_CH7
LO_F_CH6
LO_S_CH6
4
LO_F_CH5
LO_F_CH5
LO_F_CH5
LO_F_CH5
LO_F_CH5
LO_S_CH5
GUARD_CH5
HI_S_CH5
HI_F_CH5
HI_F_CH5
HI_F_CH5
5
LO_S_CH4
LO_F_CH3
6
LO_S_CH3
LO_S_CH2
8
LO_S_CH1
GUARD_CH1
LO_F_CH0
9
LO_S_CH0
10
COVER_LOW
Notes:
HI_F_CH3
HI_F_CH2
HI_F_CH1
HI_S_CH0
HI_F_CH1
HI_F_CH0
P3V3
HI_F_CH1
LO_F_CH0
HI_F_CH0
DGND
SDA0
HI_F_CH2
LO_F_CH1
LO_F_CH0
DGND
HI_F_CH3
LO_F_CH2
LO_F_CH1
LO_F_CH0
HI_F_CH4
LO_F_CH3
LO_F_CH2
HI_F_CH2
HI_S_CH1
LO_F_CH4
LO_F_CH3
LO_F_CH1
HI_F_CH6
HI_F_CH4
HI_F_CH3
HI_S_CH2
DGND
COVER_HIGH
N/C
LO_F_CH4
LO_F_CH2
LO_F_CH0
GUARD_CH0
DGND
HI_S_CH3
LO_F_CH1
HI_F_CH6
HI_F_CH4
LO_F_CH3
LO_F_CH2
GUARD_CH2
LO_F_CH1
LO_F_CH4
HI_S_CH4
LO_F_CH3
GUARD_CH3
LO_F_CH2
7
LO_F_CH4
GUARD_CH4
HI_F_CH6
HI_F_CH7
LO_F_CH6
3
LO_F_CH4
HI_S_CH6
F
AGND
N/C
LO_F_CH7
GUARD_CH7
LO_F_CH6
E
AGND
N/C
LO_F_CH7
D
AGND
HI_F_CH0
DGND
SCL0
N/C
1. COVER_LOW must be tied to ground
2. COVER_HIGH must be tied to P3V3 (3.3 V)
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
293
C – VHDM Connector Pinouts
Figure 102. DIBU VHDM Connector Pinout
DUT B Connector
Pin
A
B
IGND
1
SCOPE_TP2
SCOPE_TP3
N/C
IGND
2
CBIT_0
CBIT_6
CBIT_1
CBIT_7
CBIT_2
CBIT_8
CBIT_3
CBIT_9
CBIT_4
8
9
CBIT_10
CBIT_16
IGND
CBIT_5
CBIT_11
IGND
IGND
DP_CLKDUT
DP_CLKDUT#
IGND
IGND
N/C
N/C
IGND
10
CBIT_15
IGND
IGND
7
CBIT_14
IGND
IGND
6
CBIT_13
IGND
IGND
5
CBIT_12
IGND
IGND
4
IGND
IGND
IGND
3
C
IGND
CBIT_17
IGND
N/C
IGND
N/C
CAL_FL
N/C
GRD_L
A
B
C
D
IGND
IGND
SPI_DUT_SCK
N/C
IGND
IGND
SPI_DUT_MOSI
HI_F_CH7
IGND
IGND
SPI_DUT_MISO
HI_F_CH6
IGND
IGND
E
F
IGND
CBIT18
CBIT_24
N/C
IGND
CBIT_19
HI_F_CH7
CBIT_25
IGND
CBIT_20
HI_F_CH6
CBIT_26
IGND
SPI_DUT_CS
HI_F_CH5
CBIT_21
IGND
IGND
IGND
HI_F_CH4
CBIT_22
SPI_DUT_IO_PWR
IGND
IGND
IGND
HI_F_CH3
CBIT_23
I2C_DUT_IO_PWR
IGND
IGND
IGND
HI_F_CH2
I2C_DUT_SCL
I2CIDPROM_SCL
IGND
IGND
IGND
HI_F_CH1
I2C_DUT_SDA
I2CIDPROM_SDA
IGND
IGND
IGND
HI_F_CH0
I2CIDPROM_P3V3
IGND
IGND
CAL_SH
N/C
HI_F_CH5
CBIT_27
HI_F_CH4
CBIT_28
HI_F_CH3
CBIT_29
HI_F_CH2
CBIT_30
HI_F_CH1
CBIT_31
N/C
IGND
CAL_FH
GRD_H
N/C
DUT C Connector
Pin
IGND
1
CBIT_32
IGND
CBIT_42
N/C
IGND
2
CBIT_33
3
CBIT_43
CBIT_34
CBIT_35
CBIT_45
5
CBIT_36
CBIT_46
IGND
6
CBIT_37
CBIT_47
IGND
7
CBIT_38
CBIT_48
IGND
8
CBIT_39
CBIT_49
IGND
9
CBIT_40
CBIT_50
IGND
10
294
CBIT_41
CBIT_51
N/C
N/C
HI_F_CH0
N/C
HI_F_CH1
CBIT_61
IGND
CBIT_52
IGND
N/C
HI_F_CH2
CBIT_60
IGND
IGND
IGND
IGND
N/C
P5V0_U_RLY
HI_F_CH1
IGND
HI_F_CH3
CBIT_59
IGND
IGND
IGND
IGND
N/C
P5V0_U_RLY
HI_F_CH2
IGND
HI_F_CH4
CBIT_58
IGND
IGND
IGND
IGND
N/C
P5V0_U_RLY
HI_F_CH3
IGND
HI_F_CH5
CBIT_57
IGND
IGND
IGND
IGND
N/C
P5V0_U_RLY
HI_F_CH4
IGND
HI_F_CH6
CBIT_56
IGND
IGND
IGND
IGND
N/C
HI_F_CH5
P12V0_U
IGND
HI_F_CH7
CBIT_55
IGND
IGND
IGND
IGND
N/C
HI_F_CH6
P12V0_U
IGND
CBIT_54
N/C
IGND
IGND
IGND
IGND
N/C
HI_F_CH7
N/C
IGND
F
IGND
IGND
IGND
IGND
IGND
N/C
IGND
CBIT_44
E
IGND
IGND
IGND
IGND
4
IGND
IGND
IGND
D
IGND
CBIT_62
IGND
CBIT_53
CBIT_63
N/C
PN: 071-0961-00, January 2008
DUT A Connector
Pin
A
B
IGND
1
SCOPE_TP0
IGND
SCOPE_TP1
N/C
IGND
2
3
N/C
IGND
IGND
CAL_REFCLK400 CAL_REFCLK400#
4
N/C
5
GPIO 0
N/C
GPIO 3
P5V0_U
N5V0_U
Notes:
N5V0_U
N/C
P5V0_U_RLY
N/C
P24V0_U
IGND
P5V0_U_RLY
HI_F_CH1
IGND
P5V0_U
P24V0_U
IGND
HI_F_CH0
P5V0_U
IGND
N5V0_U
P24V0_U
IGND
IGND
IGND
N/C
IGND
P5V0_U_RLY
N/C
P5V0_U
IGND
IGND
IGND
IGND
10
N/C
GPIO 7
N/C
P5V0_U_RLY
HI_F_CH4
IGND
IGND
IGND
9
IGND
IGND
GPIO 6
IGND
HI_F_CH5
P12V0_U
N/C
GPIO 5
IGND
8
IGND
IGND
IGND
GPIO2
IGND
IGND
IGND
E
F
IGND
IGND
IGND
N/C
DP_REFCLK10
DP_REFCLK10#
N/C
IGND
IGND
IGND
HI_F_CH7
N/C
N/C
HI_F_CH7
N/C
IGND
IGND
IGND
HI_F_CH6
P12V0_U
N/C
DIB_PRESENT#
HI_F_CH6
N/C
GPIO 4
CPIO 1
N/C
IGND
IGND
7
IGND
N/C
D
IGND
IGND
IGND
6
C
P5V0_U
IGND
N5V0_U
N5V0_U
IGND
LB_GNDSNS_IN
HI_F_CH5
IGND
HI_F_CH4
N/C
IGND
P24V0_U_RTN
HI_F_CH3
IGND
P24V0_U_RTN
HI_F_CH2
IGND
P24V0_U_RTN
HI_F_CH1
IGND
P5V0_U
IGND
N5V0_U
N/C
1. DIB_PRESENT# must be tied to ground for the power supplies to work
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
295
C – VHDM Connector Pinouts
Figure 103. Mixed Signal Digitizer and AWG VHDM Connector Pinout
DUT B Connector
Pin
A
B
GND
1
N/C
GND
N/C
GND
2
N/C
N/C
IO PIN 6
5
N/C
UPIN 6
GND
6
N/C
UPIN 5
GND
7
N/C
IOPIN 5
GND
8
N/C
IOPIN 4
GND
9
N/C
UPIN 4
GND
10
N/C
N/C
N/C
N/C
N/C
N/C
N/C
ANALOG BUS P
A
B
C
N/C
GND
GND
GND
N/C
GND
GND
GND
GND
N/C
N/C
N/C
N/C
GND
GND
GND
GND
N/C
N/C
N/C
N/C
GND
GND
GND
GND
N/C
N/C
N/C
N/C
GND
GND
GND
GND
N/C
N/C
N/C
N/C
GND
GND
GND
GND
N/C
N/C
N/C
G SENSE EXT 6
GND
GND
GND
GND
G SENSE EXT 7
N/C
N/C
F
GND
GND
GND
GND
GND
N/C
N/C
IO PIN 7
E
GND
GND
GND
GND
4
N/C
UPIN 7
N/C
D
GND
GND
GND
3
C
N/C
GND
N/C
GND
ANALOG BUS M
N/C
GND
G SENSE EXT 4
G SENSE EXT 5
E
F
DUT A Connector
Pin
GND
1
N/C
GND
N/C
GND
2
N/C
3
UPIN 3
N/C
N/C
5
IOPIN 2
N/C
N/C
UPIN 1
7
N/C
IOPIN 1
GND
8
N/C
IOPIN 0
GND
9
N/C
UPIN 0
GND
10
296
N/C
N/C
N/C
N/C
N/C
GND
N/C
GND
N/C
N/C
GND
GND
GND
N/C
N/C
N/C
N/C
N/C
GND
GND
GND
GND
N/C
N/C
N/C
N/C
GND
GND
GND
GND
N/C
N/C
N/C
N/C
GND
GND
GND
GND
N/C
N/C
N/C
N/C
GND
GND
GND
GND
N/C
N/C
N/C
N/C
GND
GND
GND
GND
GND
N/C
N/C
UPIN 2
N/C
GND
GND
GND
GND
6
N/C
GND
G SENSE EXT 3 G SENSE EXT 2
GND
GND
N/C
GND
GND
GND
HS OUT M
N/C
IOPIN 3
GND
GND
GND
GND
4
HS OUT P
GND
GND
D
GND
N/C
GND
G SENSE EXT 0
G SENSE EXT 1
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Figure 104. MultiWave VHDM Pinout
DUT B Connector
Pin
A
B
AGND
1
2
GIGA_SMP_CLK _N_CH2
AGND
AGND
GIGA_SMP_CLK_P_CH2
AGND
AGND
ADC_CH3_P_S
AGND
3
4
AGND
AGND
ADC_CH3_P
AGND
AGND
DAC_CH3_P_S
AGND
DAC_CH3_P
6
7
8
9
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
DAC_CH3_N
SPI _RESET
3. 3V / 2A
A
B
C
ADC_CH3_GND_S
AGND
AGND
DAC_CH3_GND_S
AGND
AGND
DAC_CH3_VCOMM
AGND
AGND
AGND
ADC_CH2_N_S
AGND
AGND
ADC_CH2_N
AGND
AGND
DAC_CH2_N_S
AGND
AGND
DAC_CH2_N
AGND
E X T_TRIGGE R _CH3
AGND
AGND
AGND
AGND
AGND
AGND
AGND
F
AGND
GIGA_SMP_CLK_P_CH3
ADC_CH3_N
AGND
AGND
DAC_CH3_N_S
AGND
AGND
AGND
DAC_CH2_P_S
AGND
AGND
DAC_CH2_P
AGND
10
GIGA_SMP_CLK _N_CH3
AGND
AGND
ADC_CH3_N_S
AGND
ADC_CH2_P_S
AGND
AGND
ADC_CH2_P
E
AGND
AGND
AGND
AGND
D
AGND
AGND
AGND
5
C
AGND
ADC_CH2_GND_S
AGND
AGND
DAC_CH2_GND_S
AGND
AGND
DAC_CH2_VCOMM
AGND
AGND
AGND
SPI _SCLK
E X T_TRIGGE R _CH2
AGND
DGND
AGND
SPI_SDI
SPI_SDO
DUT A Connector
Pin
AGND
1
GIGA_SMP_CLK _N_CH0
AGND
GIGA_SMP_CLK_P_CH0
AGND
2
3
4
5
6
7
8
9
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
DAC_CH1_P_S
AGND
AGND
DAC_CH1_P
AGND
AGND
ADC_CH0_P_S
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
DAC_CH0_P
AGND
AGND
E X T_TRIGGE R _CH1
AGND
AGND
N/ C
GIGA_SMP_CLK _N_CH1
AGND
AGND
DAC_CH1_N_S
AGND
AGND
DAC_CH1_N
AGND
AGND
ADC_CH0_N_S
AGND
AGND
AGND
AGND
ADC_CH1_GND_S
AGND
AGND
DAC_CH1_GND_S
AGND
AGND
DAC_CH1_VCOMM
AGND
AGND
E X T_TRIGGE R _CH0
AGND
AGND
ADC_CH0_GND_S
AGND
ADC_CH0_N
AGND
AGND
DAC_CH0_N_S
AGND
AGND
AGND
DAC_CH0_N
AGND
DAC_CH0_GND_S
AGND
AGND
DA C_CH0_V COMM
AGND
AGND
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
AGND
GIGA_SMP_CLK_P_CH1
ADC_CH1_N_S
AGND
AGND
ADC_CH1_N
SDA0
F
AGND
AGND
AGND
3. 3V / 2A
E
AGND
AGND
ADC_CH0_P
AGND
AGND
DAC_CH0_P_S
AGND
AGND
AGND
10
AGND
AGND
ADC_CH1_P_S
AGND
AGND
ADC_CH1_P
D
AGND
DGND
AGND
SCL0
N/ C
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C – VHDM Connector Pinouts
Notes
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D
Loadboard Design Rules for MultiWave
The MultiWave instrument provides 4 analog generator and 4 analog capture channels.
Each channel can be dynamically switched within a test program to use high resolution
(audio) or high-frequency (video) mode. Each channel can be either used in single ended
or differential operation. Additionally every instrument channel connects to a high
precision Kelvin PPMU for precise DC force and measurement capabilities.
AWG Channels
Each AWG source channel of the MultiWave instrument offers the following impedance
options:
•
50 Ω source impedance in high-frequency mode
•
<2 Ω source impedance in high-resolution mode
In high-resolution source mode, sense connections are available to optimize the
accuracy of the signals generated at the DUT.
Digitizer Channels
Each digitizer channel of the MultiWave instrument offers the following impedance
options:
•
50 Ω single-ended input impedance in high-frequency mode
•
100 Ω differential input impedance in high-frequency mode
•
High input impedance in high-frequency mode (Ibias <15 µA)
•
High input impedance in high-resolution mode (Ibias <1 µA)
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D – Loadboard Design Rules for MultiWave
PMU Channels
A per-pin precision Kelvin PMU is available on the MultiWave instrument for each AWG
and digitizer channel. The PMU is used for high precision DUT voltage and current
forcing and measuring.
Eight parallel PMU cores (4 AWG Ch. + 4 Dig Ch.) are integrated on each MultiWave unit.
The PMU access of the positive and negative node of each channel is multiplexed.
Each PMU channel offers the following connection modes:
•
SINGLE_P—xxx_CHx_P connected to PMU (non Kelvin mode)
•
SINGLE_N—xxx_CHx_N connected to PMU (non Kelvin mode)
•
KELVIN_P—xxx_CH_P/xxx_CH_P_S connected to PMU, Kelvin mode, force and
sense needs to be shorted on the loadboard close to the DUT
•
KELVIN_N—xxx_CH_N/xxx_CH_N_S connected to PMU, Kelvin mode, force and
sense needs to be shorted on the loadboard close to the DUT
x
is the channel number 0..3 (4 ADC channels and 4 DAC channels per unit)
xxx
can be either ADC or DAC channel
AGND/DGND Connection
Connections between DUT_GND and MultiWave instrument AGND (analog ground)
should be designed as a solid ground plane.
The DGND (digital ground) connection of the MultiWave instrument should not be used.
This connection is reserved as a power return of the optional GBS (Giga Bit Sampler)
frontend clock.
GND_SENSE Connections
The GROUND_SENSE line of each used AWG and DIG channel should be connected to
the DUT_GROUND plane as close as possible to the appropriate DUT.
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Signal and Layer Arrangement
Signal and Layer Arrangement
Signals on the loadboard using the high frequency mode should be routed as 50 Ohm
traces.
It is recommended to route analog and digital lines on separate signal layers. Digital
traces should be separated from an analog signal layer through a solid ground plane.
For high precision PMU force and high precision AWG mode it is recommended to use
Kelvin connections. Therefore high sense and high force lines should be routed as a
differential signal pair.
Force and Sense should be shorted together as close as possible to the force node.
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MultiWave Instrument Connection Modes
Figure 105. Single Ended Digitizer Connection (LF-Mode)
Loadboard
MultiWave
ADC_CHx_P
DUT
+
_DIG
ADC_CHx_GND_S
AGND
PMU GND_SENSE
DUT_GND
Figure 106. Single Ended Digitizer Connection (HF-Mode)
Loadboard
DUT
50R
MultiWave
ADC_CHx_P
50R
ADC_CHx_N
ADC_CHx_GND_S
+
_DIG
PMU GND_SENSE
AGND
DUT_GND
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MultiWave Instrument Connection Modes
Figure 107. Differential Digitizer Connection (LF-Mode)
Loadboard
MultiWave
ADC_CHx_P
+
_DIG
DUT
ADC_CHx_N
ADC_CHx_GND_S
PMU GND_SENSE
AGND
DUT_GND
Figure 108. Differential Digitizer Connection (HF-Mode)
Loadboard
MultiWave
ADC_CHx_P
DUT
50R
50R
ADC_CHx_N
50R
+
_DIG
50R
ADC_CHx_GND_S
PMU GND_SENSE
AGND
DUT_GND
Figure 109. Single Ended AWG Connection (LF-Mode)
Loadboard
MultiWave
Baseline_P
DAC_CHx_P_S
DUT
DAC_CHx_P
AWG
DAC_CHx_GND_S
AGND
PMU GND_SENSE
DUT_GND
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Figure 110. Single Ended AWG Connection (HF-Mode)
Loadboard
MultiWave
Baseline_P
DAC_CHx_P
DUT
50R
AWG
50R
DAC_CHx_GND_S
AGND
PMU GND_SENSE
DUT_GND
Figure 111. Differential AWG Connection (LF-Mode)
Loadboard
MultiWave
Baseline_P
DAC_CHx_P_S
DAC_CHx_P
DUT
AWG
DAC_CHx_N
DAC_CHx_N_S
DAC_CHx_GND_S
Baseline_N
AGND
PMU GND_SENSE
DUT_GND
Figure 112. Differential AWG Connection (HF-Mode)
Loadboard
MultiWave
Baseline_P
50R
DAC_CHx_P
50R
DUT50R
DAC_CHx_N
50R
DAC_CHx_GND_S
AGND
AWG
Baseline_N
PMU GND_SENSE
DUT_GND
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MultiWave Instrument Connection Modes
Figure 113. AWG Channels—PPMU Connection
Loadboard
MultiWave
DAC_CHx_P_S
P/N MUX
HIGH_SENSE
DAC_CHx_P
HIGH_FORCE
DUT
DAC_CHx_N
PPMU
DAC_CHx_N_S
DAC_CHx_GND_S
LOW_SENSE
AGND
DUT_GND
Figure 114. Digitizer Channels—PPMU Connection
Loadboard
MultiWave
ADC_CHx_P_S
P/N MUX
HIGH_SENSE
ADC_CHx_P
DUT
HIGH_FORCE
ADC_CHx_N
PPMU
ADC_CHx_N_S
ADC_CHx_GND_S
LOW_SENSE
AGND
DUT_GND
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Notes
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E
Diamond Series Basic Program
Development
This appendix details the steps required to generate an executable job under the
Diamond Series software. An Icc test is used as the example.
These steps include:
•
Navigating the various windows and environments
•
Coding, compiling, executing, and datalogging a test
Each step shows an example of what the student will see.
Figure 115. Test System to DUT Connection
Vcc
VIS16 CH0 Force
VIS16 CH0 Sense
DUT
Gnd
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E – Diamond Series Basic Program Development
Generating the STIL File
The first step is to generate the STIL file. Program Developer (a customized version of
Slick Edit v8) is used to edit the STIL file.
To generate the STIL file:
1. Enter vs signals.stil & into a terminal window to start Program Developer as
shown in Figure 116.
Figure 116. Starting Program Developer
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Generating the STIL File
The Program Developer GUI opens as shown in Figure 117.
Figure 117. Program Developer GUI
Menus
Icons
Work Area
File Manager
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2. Edit the Signals STIL file:
a. Enter STIL 1.0; as the first line in the file. This statement specifies the STIL
version number.
b. Create a Signals block below the STIL statement. The example in Figure 118
creates one signal called vcc. The vcc signal is a Supply signal.
Figure 118. Signals STIL File
3. Save the edits.
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Starting Integrated Test Environment
Starting Integrated Test Environment
To start the Integrated Test Environment (ITE):
1. Navigate to the desired directory and enter ite &.
Figure 119. Command Window
This starts ITE.
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Figure 120. ITE Main Window
Menus
Icons
Work Area
File Manager
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Generating the Resource Definition File
Generating the Resource Definition File
The Resource Definition file assigns user defined names to test system resources.
The Icc test uses a VIS instrument located in slot 3 of the Diamond Series test system.
This must be noted in the Resource Definition File.
To generate the Resource Definition file:
1. Select File > New > Resource Def File.
Figure 121. New Pull-down Menu
The New Resource Def File window opens as shown in Figure 122.
Figure 122. New Resource Def File Window
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2. Enter the new file name and press OK. An empty Resource Def file opens in the ITE
GUI as shown in Figure 123.
Figure 123. New Empty Resource Def File
This DUT Icc example uses a VIS16 instrument in chassis 0, slot 3.
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Generating the Resource Definition File
3. Specify the Resource, Type, Chassis, and Slot fields as required.
4. Press Save before closing the window.
Figure 124. Resource, Type, Chassis, and Slot Fields
Figure 125 shows the code inserted into the Resource Def File based on the input to
the ITE GUI.
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Figure 125. Resource Def File Code
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Generating the Signal Map File
Generating the Signal Map File
The Signal Map file assigns signal names to user defined resources and channels for
each site.
To generate the Signal Map file:
1. Select File > New > Signal Map File.
Figure 126. New Pull-down Menu
The New Signal Map File window opens as shown in Figure 127.
Figure 127. New Signal Map File Window
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2. Enter the new file name and press OK. An empty Signal Map file opens in the ITE
GUI as shown in Figure 128.
Figure 128. New Signal Map File
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Generating the Signal Map File
3. Specify the Signal, Resource, and Channel fields as required. The signal name must
match the signal name in the STIL Signals block. The resource name was defined in
the Resource Definition file.
4. Press Save before closing the window.
Figure 129. Resource, Type, Chassis, and Slot Fields
Below is the code inserted into the Signal Map file based on the input to the ITE GUI.
Figure 130. Signal Map File Code
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Generating the C++ Header File
To generate the C++ Header file:
1. Enter vs example.h & (where example.h is the C++ header file name) into the
terminal window.
2. Press Enter.
Figure 131. Generating a C++ Header File
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Generating the C++ Header File
Editing the Header File
To edit the C++ Header file:
1. Enter #ifndef, #define, and #endif preprocessor commands to ensure that the
body of the header file is not included multiple times.
2. Enter using namespace std; to include the C++ standard library into the current
declarative region.
3. Enter #include CscDmd.h to include the predefined variables required by the
Diamond Series software.
4. Enter the header code and save the file.
Figure 132. Example Header Code
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Generating the C++ Source File for a Test
To generate the C++ Source file for the test:
1. Enter vs icc.cpp & (where icc.cpp is the C++ Source file name) into a terminal
window as shown in Figure 133.
2. Press Enter.
Figure 133. Generating a C++ Source File
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Editing the C++ Source File for a Test
Editing the C++ Source File for a Test
To edit the C++ Source file for a test:
1. Enter the function structure and instrument statements required for the desired test
and save the file.
2. Include the C++ Header file using the #include statement.
3. Create a function that contains the instrument statements required for the desired
test. The example in Figure 134 depicts an Icc measurement on the vcc signal.
Figure 134. C++ Source File
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Generating the C++ Source File for user_main()
To generate the C++ Source file:
1. Enter vs user_main.cpp & into a terminal window as shown in Figure 135.
2. Press Enter.
Figure 135. Generating a user_main C++ Source File
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Editing the C++ Source File for user_main()
Editing the C++ Source File for user_main()
To edit the C++ Source file for user_main():
1. Include the C++ Header file using the #include statement.
2. Create a function prototype for each test function.
3. Create the user_main() function. This function calls the test functions and then
returns. User_main() is the starting point of the test program.
4. Enter user_main code and save the file.
Figure 136. C++ Source File Example
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Generating the Job File
The Job file defines the parameters of the job.
To generate the Job file:
1. Switch to ITE and generate the Job file by selecting File > New > Job File.
Figure 137. New Pull-down Menu
2. Enter the job file name and press OK in the New Job File window as shown in
Figure 138.
Figure 138. New Job File Window
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Generating the Job File
An empty Job file opens in ITE. The Job file is divided into four tabs:
•
Main
•
Advanced
•
STIL
•
Test Program
Figure 139. Job File Tabs
Job File Tabs
3. Use the file chooser to select the Resource Definition, Signal Map, and STIL files in
the Main tab.
4. Type in the name of the Test Program library on the Main tab. This is the library file
that is created when the C++ files are compiled.
5. Press Save when done.
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Figure 140. Job File—Main Tab
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Generating the Job File
6. Use the file chooser to select the C++ source files and include directories in the Test
Program tab.
7. Press Save when done.
Figure 141. Job File—Test Program Tab
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Figure 142 shows the code inserted into the Job file based on the input to the ITE GUI.
Figure 142. Job File Code Example
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Building the Job File
Building the Job File
To build the job file:
1. Select Build > Build Tool... to build the job file.
Figure 143. Build Pull-down Menu
2. Enter or browse to the Job file in the Job File field.
3. Enter or browse to the Make file in the Makefile field.
4. Press the Generate Makefile button to compile the makefile from the Job file. The
makefile defines the compiler dependencies.
Figure 144. Build Dialog Window
Generate Makefile Button
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5. Press the make button to compile the STIL and C++ source files. If errors occur
during the make process, correct them before preceding.
Figure 145. make Button
make
Button
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Loading the Job File
Loading the Job File
To load the job file:
1. Double-click on the Job name in the ITE file chooser window. The Execution tab
appears after the job is loaded.
Figure 146. Job File—Execution Tab
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Enabling Datalog
To enable datalogging:
1. Select Tester > Datalog Control to enable datalogging.
Figure 147. Tester Pull-down Menu
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Enabling Datalog
The Datalog Control opens the ITE GUI.
Figure 148. Datalog Control
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2. Select the All Tests > Test check box to datalog all tests.
3. Select the Events > All check box to datalog all events as shown in Figure 149.
Figure 149. Real Time Datalog Options
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Running the Job
Running the Job
To run the job:
1. Select the Execution tab and press Run to run the job.
Figure 150. Job File—Execution Tab
Run Button
The results of the test are shown in the Test Executive window.
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Generating the Binning Definitions File
The Binning Definition file assigns user defined names to soft bins.
To generate the Binning Definition file:
2. Select File > New Binning Def File to generate a new Binning Definition file.
Figure 151. New Pull-down Menu
3. Enter the Binning Def file name and press OK in the New Binning Def File window
(see Figure 152).
Figure 152. New Binning Def File Window
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Generating the Binning Definitions File
An empty Binning Definition file opens in the ITE GUI.
Figure 153. New Binning Definition File
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4. Specify the name, attribute, number, and description for each soft bin. Press Save
before closing the window.
Figure 154. Soft Bin Attributes
Figure 155 shows the code that is inserted into the Binning Definition file based on the
input to the ITE GUI.
Figure 155. Binning Definition Code Example
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Generating the Binning Map File
Generating the Binning Map File
The Binning Map file maps hard bin numbers to soft bin numbers.
To generate the Binning Map file:
1. Select File > New > Binning Map File to generate the Binning Map file.
Figure 156. New Pull-down Menu
2. Enter the Binning Map file name and press OK in the New Binning Map File window
(see Figure 157).
Figure 157. New Binning Map File Window
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An empty Binning Map file opens in the ITE GUI.
Figure 158. New Binning Map File
Insert Soft Bins Button
3. Press the Insert Soft Bins button to import the soft bin names from the Binning
Definition file.
4. Select the Binning Definition file and press OK. The Soft Bin Name column is
automatically filed in.
5. Specify the hard bin number for each soft bin name.
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Generating the Binning Map File
6. Save before closing window. An example of a complete Binning file is shown in
Figure 159.
Figure 159. Completed New Binning Map File
Figure 160 shows the code inserted into the Binning Map file based on the input to the
ITE GUI.
Figure 160. Binning Map File Code Example
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Editing the Binning C++ Source File
To edit the Binning C++ Source file:
1. Enter vs binning.cpp & at the terminal window prompt to open the new file in
Program Developer.
Figure 161. Opening Program Developer
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Editing the Binning C++ Source File
2. Include the C++ header file by using the #include statement.
3. Create a function that contains the statements required to bin the device.
4. Save the file before closing the window.
Figure 162. Binning C++ Source File
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Adding Binning to user_main()
To add binning the user_main():
1. Open the C++ Source file that contains the user_main() function.
Figure 163. C++ Source File
2. Add a function prototype for the new function.
3. Call the new function from the user_main() function.
4. Save the file before closing the window.
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Adding Binning to user_main()
Figure 164. user_main() File with Binning
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Adding Binning to the Job file
To add binning to the Job file:
1. Select the Job file in the file manager window.
2. Right-click on the Job file and select Edit to open the job file in ITE.
Figure 165. Job File Right-Click Menu
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Adding Binning to the Job file
3. Select the Main tab.
4. Add the Binning Definition file in the Bin Definition field using the file chooser.
5. Add the Binning Map file in the Bin Map field using the file chooser.
Figure 166. Job File—Main Tab
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6. Select the Test Program tab and add the Binning C++ Source file using the file
chooser.
7. Save the file before closing the window.
Figure 167. Job File—Test Program Tab
File Chooser
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Recompiling the Job File
Recompiling the Job File
To recompile the Job file:
1. Select Build > Build Tool... to recompile the Job file.
Figure 168. Build Pull-down Menu
2. Press the Generate Makefile button to recreate the makefile.
Figure 169. Generate Makefile Button
Generate Makefile Button
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3. Press the make button to compile the STIL and C++ Source files.
Figure 170. make Button
make
Button
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Reloading the Job File
Reloading the Job File
To reload the Job file:
1. Double-click on the Job name in the ITE file chooser window to load the job.
Figure 171. Loaded Job File
2. A dialog box appears asking about reloading files (see Figure 172). Press Yes to
reload the test program.
Figure 172. Reloading Files Message
3. Press Run to run the job and view the binning results.
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E – Diamond Series Basic Program Development
Figure 173. Running the Job
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F
Credence Unified Robot Interface
Overview
The Credence Unified Robot Interface (CURI) has the following features:
•
Defines and implements a unified production integration environment across
Credence platforms
•
Implements a unified robot interface
The interface that integrates the CURI system includes:
•
Single API for all test systems
Support standard Credence programming environments (DLL interface for native
code base test systems)
•
API acts as bridge to unified driver set
•
Unified driver set requirements
The CURI software applications are installed from the CURI software CD and located in
the cred_apps folder.
For integration assistance or additional information contact the Credence Integration
Software Group at isg_help@credence.com
Production Robot
Handlers and probers are the most common examples of robots. Robots have to
following features:
•
•
Any equipment that can issue a ready to test event, including: (In the event of multiple
test start options, able to distinguish site.)
–
Parallel synchronous test
–
Parallel asynchronous test
–
Combination of above
Any equipment that can accept test system directed operations, including:
–
Chuck device (normally with binning information)
–
Pause test
–
Resume test
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–
Stop test
–
Abort test
–
User defined robot operations
Figure 174. System to Robot Flow
Independent
Test Systems
Test System
API
Unified
Controller
Robots
EG
Diamond Series
Test System
Unified
Native DLL
TEL
Robot
Controller
TSK
MCT
Mirare
Seiko
Test System API
The test system API must have the following features:
356
•
Can begin automated test (including Start test, End test, and Lot/Wafer/Site
information)
•
New features can be added without change in interface specification
•
Independent of global infrastructure
•
Customizable at multiple levels, including:
–
Customer can add a link to the end lot for data transfer
–
ISG can add new robot
–
Test system operating system can support new common features
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Test System Communications Protocol
Test System Communications Protocol
The first step in understanding the prober/handler interface software, is to understand the
handshaking that occurs between the test system and the handler or prober.
Figure 175. Test System to Handler Communication Flow
Test System
Handler
Send Bin/Test Complete
Load Next Device(s)
Send Test Start
Query for Active Sites
Send Active Sites
Run Device Test
Figure 176. Normal Prober Operation
Test System
Prober
Send Bin/Test Complete
Index to Next Die
Send Test Start
Query for X/Y Coords
Send X/Y Coords
Query for Active Sites
Send Active Sites
Run Device Test
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F – Credence Unified Robot Interface
Figure 177. Operation at End-of-Wafer
Test System
Prober
Send Bin/Test Complete
Send End-of-Wafer
Unload Tested Wafer
Call end_of_wafer()
Load New Wafer
Index to First Die
Send Test Start
Go to Figure 176
"Normal Prober Operation"
The software uses maps to store the wafer ID, X/Y coordinates, and other information.
GPIB ANSI Connector/IEEE 488 Interface
There is only one GPIB port on the test system (labelled GPIB). Since GPIB connectors
can be stacked on top of each other, it is possible to connect more than one piece of
equipment to the port.
The test system supports polling the GPIB port.
The following GPIB addresses are reserved for use by the test system:
•
21—Fluke
•
20—DC5010
•
19—ACS
•
13—1151 #2
•
12—1151 #1
•
0—GPIB controller board
Table 24. 24-Pin GPIB Bus Pin Out (Sheet 1 of 2)
358
Pin #
Signal Names
Signal Description
1
DIO1
Data Input/Output Bit 1
2
DIO2
Data Input/Output Bit 2
3
DIO3
Data Input/Output Bit 3
4
DIO4
Data Input/Output Bit 4
5
EIO
End-Or-Identify
6
DAV
Data Valid
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Test System Communications Protocol
Table 24. 24-Pin GPIB Bus Pin Out (Sheet 2 of 2)
Pin #
Signal Names
Signal Description
7
NRFD
Not Ready For Data
8
NDAC
Not Data Accepted
9
IFC
Interface Clear
10
SRQ
Service Request
11
ATN
Attention
12
Shield
Chassis Ground
13
DIO5
Data Input/Output Bit 5
14
DIO6
Data Input/Output Bit 6
15
DIO7
Data Input/Output Bit 7
16
DIO8
Data Input/Output Bit 8
17
REN
Remote Enable
18
Shield
Ground (DAV)
19
Shield
Ground (NRFD)
20
Shield
Ground (NDAC)
21
Shield
Ground (IFC)
22
Shield
Ground (SRQ)
23
Shield
Ground (ATN)
24
Single
GND Single Ground
RS-232 Interface
The RS-232 cable requires only three wires to be connected: pins 2, 3 and 7. Pins 2 and
3 are transmit and receive lines. They should be wired straight across (not the null
modem configuration). Pin 2 on one end of the cable should go to pin 2 on the other end
of the cable, and similarly for pin 3.
RS-232 interrupts can be enabled or disabled. The RS-232 ports on the test system are
labelled Prober 1 and Prober 2. Prober 1 is used with the testhead.
Table 25. RS-232—EIA232 Pinout (Sheet 1 of 2)
DB-25
1
DCE
DB-9
Name
Protective Ground
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Table 25. RS-232—EIA232 Pinout (Sheet 2 of 2)
DB-25
DCE
DB-9
Name
2
TXD
3
Transmitted Data
3
RXD
2
Received Data
4
RTS
7
Request To Send
5
CTS
8
Clear To Send
6
DSR
6
Data Set Ready
7
GND
5
Signal Ground
8
CD
1
Received Line Signal Detector
9
Reserved for data set testing
10
Reserved for data set testing
11
Unassigned
12
SCF
Secondary Rcvd Line Signl Detctr
13
SCB
Secondary Clear to Send
14
SBA
Secondary Transmitted Data
15
DB
Transmisn Signl Elemnt Timng
16
SBB
Secondary Received Data
17
DD
Receiver Signal Element Timing
18
Unassigned
19
SCA
20
DTR
21
CG
22
Secondary Request to Send
4
Data Terminal Ready
Signal Quality Detector
9 Ring Indicator
23
CH/CI
Data Signal Rate Selector
24
DA
Transmit Signal Element Timing
25
Unassigned
OIC
The Operator Interface Control (OIC) is a Graphical User Interface (GUI) that provides a
convenient way of operating the Diamond Series test system.
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OIC
The architecture for communicating with the test system is that of a Client-Server TCP/IP
interface between the OIC and the Diamond Series Test Executive.
For more information on the Diamond Series OIC, refer to chapter 24.
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CURI_CONF.XML Settings
The CURI_CONF settings are composed of four sections:
•
Default Equipment (1)
•
Equipment entries (multiple)
•
Config/Communications list (multiple allowed, only one is distro)
•
CommunicationsAccess (multiple allowed, only one is distro)
The curi_conf.xml file is located at \cred_apps\config\curi_conf.xml.
Default Equipment
Table 26. Default Equipment
Equipment Name
Library
Config Ref
Mapping Equipment
"Simulator" on page 363
simulator
Default configuration
False
"Simulate Probe" on page 363
simulator
Default configuration
True
"TSK UF Series" on page 364
uf200
Default configuration
True
"Electroglas Series" on page 365
EG_40xx
Default configuration
True
"TEL Series" on page 365
tel_P8
Default configuration
True
"TTL Test" on page 366
dio96_test
Default configuration
False
"Ismeca TTL" on page 366
ismeca_ttl
Default configuration
False
"NEC TTL" on page 366
nec_ttl
Default configuration
False
"Epson Series" on page 367
epson
Default configuration
False
"Aetrium TR Series" on page 367
aetrium
Default configuration
False
"EH3300" on page 367
eh3300
Default configuration
False
"Delta Flex" on page 368
flex
Default configuration
False
"HT8080" on page 368
ht8080
Default configuration
False
"MCT" on page 368
mct
Default configuration
False
"MultiTest 9510" on page 369
mt9510
Default configuration
False
"Mirae 5500" on page 369
mr5500
Default configuration
False
"Rasco Series" on page 369
rasco
Default configuration
False
"GPIB 4863" on page 370
gpib4863
Default configuration
False
"Hot Keys" on page 370
hotkeys
Default configuration
False
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CURI_CONF.XML Settings
Equipment Entries
Table 27. Simulator
Equipment Name
Library
Simulator
Simulator
Settings
Config Ref
Mapping
Equipment
Default
Configuration
False
ErrorHardBin
*7
ErrorSoftBin
*9999
SkipHardBin
11
SkipSoftBin
111
Note — * default value
Table 28. Simulate Probe
Equipment Name
Library
Config Ref
Mapping
Equipment
Default Configuration
True
ErrorHardBin
*7
ErrorSoftBin
*9999
SkipHardBin
11
SkipSoftBin
111
Token
Value
Equipment Sets Lot ID
*True
Equipment Sets Map ID
*True
Equipment Sets SubLot ID
*True
Simulator
Simulate Probe
Settings
boolSetting
Note — * default value
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Table 29. TSK UF Series
Equipment
Name
Library
uf200
Tsk Uf Series
Settings
boolSetting
stringSetting
Config Ref
Mapping Equipment
Default
Configuration
True
ErrorHardBin
*7
ErrorSoftBin
*9999
Token
Value
AutoStart
*True
OCRWfrID
*True
BIN_WITH
_CATEGORY
*True
Token
Value
BIN_TYPE
*Hard
CATEGORY
_DATA
*BINARY_MODE_0
BINARY_MODE_1
ORIGIN
*ORIGIN_TOP_LEFT,
ORIGIN_TOP_RIGHT,
ORIGIN_BOTTOM_LEFT,
ORIGIN_BOTTOM_RIGHT
Note — * default value
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CURI_CONF.XML Settings
Table 30. Electroglas Series
Equipment Name
Electroglas
Series
Library
EG_40xx
Settings
boolSetting
Config Ref
Mapping
Equipment
Default
Configuration
True
ErrorHardBin
*7
ErrorSoftBin
*9999
Token
Value
Equipment Sets
Lot ID
*True
Equipment Sets
Map ID
*True
Equipment Sets
SubLot ID
*True
Note — * default value
Table 31. TEL Series
Equipment Name
Library
tel_P8
TEL Series
Settings
boolSetting
Config Ref
Mapping
Equipment
Default
Configuration
True
ErrorHardBin
*7
ErrorSoftBin
*9999
Token
Value
Equipment Sets
Lot ID
*True
Equipment Sets
Map ID
*True
Equipment Sets
SubLot ID
*True
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F – Credence Unified Robot Interface
Table 32. TTL Test
Equipment Name
Library
dio96_test
TTL Test
Settings
Config Ref
Mapping
Equipment
Default
Configuration
False
ErrorHardBin
*7
ErrorSoftBin
*9999
Config Ref
Mapping
Equipment
Default
Configuration
False
ErrorHardBin
3
ErrorSoftBin
*9999
Config Ref
Mapping
Equipment
Default
Configuration
False
ErrorHardBin
0
ErrorSoftBin
*9999
Note — * default value
Table 33. Ismeca TTL
Equipment Name
Library
ismeca_ttl
Ismeca TTL
Settings
Note — * default value
Table 34. NEC TTL
Equipment name
Library
nec_ttl
NEC TTL
Settings
Note — * default value
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CURI_CONF.XML Settings
Table 35. Epson Series
Equipment Name
Library
epson
Epson Series
Settings
Config Ref
Mapping
Equipment
Default
Configuration
False
ErrorHardBin
*7
ErrorSoftBin
*9999
Config Ref
Mapping
Equipment
Default
Configuration
False
ErrorHardBin
*7
ErrorSoftBin
*9999
Config Ref
Mapping
Equipment
Default
Configuration
False
ErrorHardBin
*7
ErrorSoftBin
*9999
Note — * default value
Table 36. Aetrium TR Series
Equipment Name
Library
aetrium
Aetrium TR Series
Settings
Note — * default value
Table 37. EH3300
Equipment Name
Library
eh3300
EH3300
Settings
Note — * default value
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Table 38. Delta Flex
Equipment Name
Library
flex
Delta Flex
Settings
Config Ref
Mapping
Equipment
Default
Configuration
False
ErrorHardBin
*7
ErrorSoftBin
*9999
Config Ref
Mapping
Equipment
Default
Configuration
False
ErrorHardBin
*7
ErrorSoftBin
*9999
Config Ref
Mapping
Equipment
Default
Configuration
False
ErrorHardBin
*7
ErrorSoftBin
*9999
Note — * default value
Table 39. HT8080
Equipment Name
Library
ht8080
HT8080
Settings
Note — * default value
Table 40. MCT
Equipment Name
Library
mct
MCT
Settings
Note — * default value
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CURI_CONF.XML Settings
Table 41. MultiTest 9510
Equipment Name
Library
mt9510
MultiTest 9510
Settings
Config Ref
Mapping
Equipment
Default
Configuration
False
ErrorHardBin
*7
ErrorSoftBin
*9999
Config Ref
Mapping
Equipment
Default
Configuration
False
ErrorHardBin
*7
ErrorSoftBin
*9999
Config Ref
Mapping
Equipment
Default
Configuration
False
ErrorHardBin
*7
ErrorSoftBin
*9999
Note — * default value
Table 42. Mirae 5500
Equipment Name
Library
mr5500
Mirae 5500
Settings
Note — * default value
Table 43. Rasco Series
Equipment name
Library
rasco
Rasco Series
Settings
Note — * default value
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Table 44. GPIB 4863
Equipment Name
Library
gpib4863
GPIB-4863
Settings
Config Ref
Mapping
Equipment
Default
Configuration
False
ErrorHardBin
*7
ErrorSoftBin
*9999
Config Ref
Mapping
Equipment
Default
Configuration
False
ErrorHardBin
*7
ErrorSoftBin
*9999
Token
Value
CTRL
*True
ALT
*True
SHIFT
*True
OS
*True
Token
Value
KEY
G
Note — * default value
Table 45. Hot Keys
Equipment Name
Library
hotkeys
Hot Keys
Settings
boolSetting
stringSetting
Note — * default value
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CURI_CONF.XML Settings
Table 46. Default Communications List
Access
Name
Library
GPIB
curi_ni_gpib 1
\r\n
Com3
RS232
Standard
Comm Port
curi_rs232
\r\n
NI USB
DAQ DIO
TTL
curi_ni_daq
_dio96
ASL PCI
PORT
ASL_XP curi_asl_ttl
_TTL
False
ASL AT
PORT
ASL_NT curi_asl_ttl
_TTL
False
65000
Standard
IP Port
TCPIP
curi_tcpip
Standard
USB Port
USB
curi_usb
Access ID
NI GPIB
USB
Primary Termin TARGET
IP_ADDR IbcTMO IbcEOT Default
Address ation
_FQN
11
1
False
False
False
localhost 127.0.0.1
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
False
False
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F – Credence Unified Robot Interface
Table 47. Communications Access
Access
AutoLoad
Name
Primary GPIB
Address Link
ConfigRef
True
Default
Communications Configuration
List
Termination Default
Ibc
TMO
Ibc
EOT
Access
Library
Name
DriverID
1
GPIB
curi_ni_gpib
NI GPIB USB B
\r\n
False
11
1
3
Scope
curi_comms
_loopback
NI GPIB USB B
\r\n
False
11
1
5
Meter
curi_comms
_loopback
NI GPIB USB B
\r\n
False
11
1
Invoke
Command
tieTo
MustWait
useDire
ctCmd
Read
commsRead
False
Write
commsWrite
False
Query
commsQuery
False
Poll
directCommand
True
Purge
clearComms
False
WaitFor
commsWaitEvent True
SERIAL_
POLL
Example Code Using Direct Communications Access
try {
cscExec->Robot()->invokeCommand("GPIB Link:Meter:Query", "*IDN?", false);
std::string idnReply = cscExec->Robot()->get("GPIB Link:Meter:Query");
std::cout << "*IDN? : " << idnReply << std::endl;
} catch (...) {
std::cout << "*IDN? : " << "Query Failed" << std::endl;
}
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uf_series_maps.XML Commands
uf_series_maps.XML Commands
A (String):XY Travel (Absolute Distance)
A
Y
±
105 104 103 102 101 100 X
±
105 104 103 102 101 100 CR LF
(Unit: 100 µm or 10-4 inch)
Upon receiving this command, Chuck is set to Z-DOWN. It travels from the current
position by the demanded X/Y amounts, and then Chuck height is returned to that before
receiving this command.
X+ is leftward, and Y+ backward
Command receive
"A"
No
Command error
Yes
No
STB=74
Probing
going on?
Target Position
within probing area?
SRQ send
Yes
No
Chuck in
Z-DOWN?
Z-DOWN
Yes
Travel to the
target position
No
Z-UP
Finish at Z-UP
: STB = 67
Finish at Z-DOWN : STB = 65
Chuck in
Z-DOWN
before the travel?
SRQ send
Note — 1) The Probing going on period is from the positioning of the start die till the wafer
last die testing end. 2) A specified travel distance over 1/2 index (but less than one index)
in X or Y direction changes the die coordinate value by ±1 after the travel.
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H:Multisite Location No. Request
H
CR
LF
When Prober has received this command and it is allowed as Talker, it outputs the
channel location number registered in the device data.
Response
Channel Location Number
I:Index Size Setting
I
Y
104
103
102
101
100
X
104
103
102
101
100
CR
LF
(Unit: 100 µm or 10-4 inch)
At receiving this command, the index sizes of die are changed accordingly.
Command receive
"I"
No
Command error
Waiting
for lot process
start?
Yes
Setup of
X/Y index sizes
STB = 77
SRQ send
Note — After execution of this command, wafer alignment and probe-pad alignment
become necessary.
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uf_series_maps.XML Commands
<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE SITECONF [
<!-- Definition of Site Configuration Map -->
<!ELEMENT SITECONF (Config, Map+)>
<!ELEMENT Config (#PCDATA| EquipmentInfo)*>
<!ATTLIST Config
equipID ID #IMPLIED
DefaultEquipment CDATA #IMPLIED
>
<!ELEMENT EquipmentInfo (#PCDATA)>
<!ATTLIST EquipmentInfo
EquipmentName CDATA #IMPLIED
>
<!ELEMENT Map (BoxParam)+>
<!ATTLIST Map
MapReference CDATA "siteGrouping"
EquipRef IDREF #IMPLIED
FirstSite (0 | 1) "0"
NumSites
CDATA "1"
BoxWidth
CDATA "1"
BoxDepth
CDATA "1"
>
<!ELEMENT BoxParam (#PCDATA)>
<!ATTLIST BoxParam
Site
CDATA #REQUIRED
Xoffset
CDATA #REQUIRED
Yoffset
CDATA #REQUIRED
>
]>
Note — H returns a Map Reference 2 digit code
<SITECONF>
<Config equipID="TSK" DefaultEquipment="UF200" >
<EquipmentInfo EquipmentName="TSK UF Series"/>
</Config>
<Map MapReference="01" EquipRef="TSK" NumSites="2" BoxWidth="2" BoxDepth="2" >
Offset
-1
1
1
0
0
0
<BoxParam Site="0" Xoffset="0" Yoffset="0"/>
<BoxParam Site="1" Xoffset="-1" Yoffset="1"/>
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</Map>
<Map MapReference="26" EquipRef="TSK" NumSites="16" BoxWidth="2" BoxDepth="1" >
Offset
0
1
0
0
8
-1
1
9
-2
2
10
-3
3
11
-4
4
12
-5
5
13
-6
6
14
-7
7
15
<BoxParam Site="0" Xoffset="0" Yoffset="0"/>
<BoxParam Site="1" Xoffset="0" Yoffset="-1"/>
<BoxParam Site="2" Xoffset="0" Yoffset="-2"/>
<BoxParam Site="3" Xoffset="0" Yoffset="-3"/>
<BoxParam Site="4" Xoffset="0" Yoffset="-4"/>
<BoxParam Site="5" Xoffset="0" Yoffset="-5"/>
<BoxParam Site="6" Xoffset="0" Yoffset="-6"/>
<BoxParam Site="7" Xoffset="0" Yoffset="-7"/>
<BoxParam Site="8" Xoffset="1" Yoffset="0"/>
<BoxParam Site="9" Xoffset="1" Yoffset="-1"/>
<BoxParam Site="10" Xoffset="1" Yoffset="-2"/>
<BoxParam Site="11" Xoffset="1" Yoffset="-3"/>
<BoxParam Site="12" Xoffset="1" Yoffset="-4"/>
<BoxParam Site="13" Xoffset="1" Yoffset="-5"/>
<BoxParam Site="14" Xoffset="1" Yoffset="-6"/>
<BoxParam Site="15" Xoffset="1" Yoffset="-7"/>
</Map>
<Map MapReference="X9" EquipRef="TSK" NumSites="72" BoxWidth="12" BoxDepth="6"
FirstSite="1" >
376
Offset
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
1
34
36
35
24
22
20
18
16
15
12
2
4
0
29
32
33
25
23
19
17
11
13
1
3
5
-1
28
27
30
31
26
21
14
8
6
7
9
10
-2
46
45
43
44
38
52
59
65
67
66
64
63
-3
41
42
40
48
49
54
56
62
60
72
70
68
-4
39
37
47
50
51
53
55
57
58
61
71
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uf_series_maps.XML Commands
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
Site="1" Xoffset="0" Yoffset="0"/>
Site="2" Xoffset="1" Yoffset="1"/>
Site="3" Xoffset="1" Yoffset="0"/>
Site="4" Xoffset="2" Yoffset="1"/>
Site="5" Xoffset="2" Yoffset="0"/>
Site="6" Xoffset="-1" Yoffset="-1"/>
Site="7" Xoffset="0" Yoffset="-1"/>
Site="8" Xoffset="-2" Yoffset="-1"/>
Site="9" Xoffset="1" Yoffset="-1"/>
Site="10" Xoffset="2" Yoffset="-1"/>
Site="11" Xoffset="-2" Yoffset="0"/>
Site="12" Xoffset="0" Yoffset="1"/>
Site="13" Xoffset="-1" Yoffset="0"/>
Site="14" Xoffset="-3" Yoffset="-1"/>
Site="15" Xoffset="-1" Yoffset="1"/>
Site="16" Xoffset="-2" Yoffset="1"/>
Site="17" Xoffset="-3" Yoffset="0"/>
Site="18" Xoffset="-3" Yoffset="1"/>
Site="19" Xoffset="-4" Yoffset="0"/>
Site="20" Xoffset="-4" Yoffset="1"/>
Site="21" Xoffset="-4" Yoffset="-1"/>
Site="22" Xoffset="-5" Yoffset="1"/>
Site="23" Xoffset="-5" Yoffset="0"/>
Site="24" Xoffset="-6" Yoffset="1"/>
Site="25" Xoffset="-6" Yoffset="0"/>
Site="26" Xoffset="-5" Yoffset="-1"/>
Site="27" Xoffset="-8" Yoffset="-1"/>
Site="28" Xoffset="-9" Yoffset="-1"/>
Site="29" Xoffset="-9" Yoffset="0"/>
Site="30" Xoffset="-7" Yoffset="-1"/>
Site="31" Xoffset="-6" Yoffset="-1"/>
Site="32" Xoffset="-8" Yoffset="0"/>
Site="33" Xoffset="-7" Yoffset="0"/>
Site="34" Xoffset="-9" Yoffset="1"/>
Site="35" Xoffset="-7" Yoffset="1"/>
Site="36" Xoffset="-8" Yoffset="1"/>
Site="37" Xoffset="-8" Yoffset="-4"/>
Site="38" Xoffset="-5" Yoffset="-2"/>
Site="39" Xoffset="-9" Yoffset="-4"/>
Site="40" Xoffset="-7" Yoffset="-3"/>
Site="41" Xoffset="-9" Yoffset="-3"/>
Site="42" Xoffset="-8" Yoffset="-3"/>
Site="43" Xoffset="-7" Yoffset="-2"/>
Site="44" Xoffset="-6" Yoffset="-2"/>
Site="45" Xoffset="-8" Yoffset="-2"/>
Site="46" Xoffset="-9" Yoffset="-2"/>
Site="47" Xoffset="-7" Yoffset="-4"/>
Site="48" Xoffset="-6" Yoffset="-3"/>
Site="49" Xoffset="-5" Yoffset="-3"/>
Site="50" Xoffset="-6" Yoffset="-4"/>
Site="51" Xoffset="-5" Yoffset="-4"/>
Site="52" Xoffset="-4" Yoffset="-2"/>
Site="53" Xoffset="-4" Yoffset="-4"/>
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<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
<BoxParam
Site="54"
Site="55"
Site="56"
Site="57"
Site="58"
Site="59"
Site="60"
Site="61"
Site="62"
Site="63"
Site="64"
Site="65"
Site="66"
Site="67"
Site="68"
Site="69"
Site="70"
Site="71"
Site="72"
Xoffset="-4" Yoffset="-3"/>
Xoffset="-3" Yoffset="-4"/>
Xoffset="-3" Yoffset="-3"/>
Xoffset="-2" Yoffset="-4"/>
Xoffset="-1" Yoffset="-4"/>
Xoffset="-3" Yoffset="-2"/>
Xoffset="-1" Yoffset="-3"/>
Xoffset="0" Yoffset="-4"/>
Xoffset="-2" Yoffset="-3"/>
Xoffset="2" Yoffset="-2"/>
Xoffset="1" Yoffset="-2"/>
Xoffset="-2" Yoffset="-2"/>
Xoffset="0" Yoffset="-2"/>
Xoffset="-1" Yoffset="-2"/>
Xoffset="2" Yoffset="-3"/>
Xoffset="2" Yoffset="-4"/>
Xoffset="1" Yoffset="-3"/>
Xoffset="1" Yoffset="-4"/>
Xoffset="0" Yoffset="-3"/>
</Map>
</SITECONF>
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Writing CURI Drivers
Writing CURI Drivers
Creating a Handler Interface
Table 48. Commands
Command
Multitest
Command
Start handler
STA!
Stop handler
STO!
Reset to local mode
LOC!
Set handler ID
ID
%16S
Set SQB mask
SQBM
%D
Binning category site 1
A BIN
%(1..2)D
Binning category site 2
B BIN
%(1..2)D
Binning category site 1
and site 2
A BIN
%(1..2)D B BIN
Assignments to Contact
Sites is Allowed
Binning category site 3
(QUAD only)
C BIN
%(1..2)D
Binning category site 4
(QUAD only)
D BIN
%(1..2)D
Example:
A BIN 1 C BIN 13 B BIN 14
D BIN 2
Arguments
Note
MT9510 ONLY
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
Any Combination and
Sequence of Bin
379
F – Credence Unified Robot Interface
Figure 178. Handler Interface
CURI
User Defined Driver Code
Auto Test
User
Init?
Yes
User
Initialize
Start?
Start
Function?
Yes
Start Handler
Commands
User
Start
No
Test System
Ready?
Yes
Ready to Test?
Test
Program
All Sites
Complete?
Yes
Yes
User Send
Bin Info
Binning
Commands
Testing?
No
End Auto
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User defined code example:
/*!
* \file sqb_protocol.cpp
*
* \copyright 2006, Credence Systems Corporation, Integration Software Group
*
* A typical setup in the configuration file would be as follows:
*
<Equipment EquipmentName="MultiTest 9510" Library="sqb_protocol">
<CommunicationsList>
<GPIB_IF PrimaryAddress="10"/>
</CommunicationsList>
<Settings>
<ErrorHardBin> 7 </ErrorHardBin>
<ErrorSoftBin> 9999 </ErrorSoftBin>
<stringSetting token="Sites Supported" value="4"/>
<boolSetting token="Serial Poll Sets Sites Ready" value="true"/>
</Settings>
</Equipment>
*
*/
#if (defined(WIN32) || defined(_WINDOWS))
#include "stdafx.h"
#endif
#include <cmos_curi_platform.h>
#include <cmos_curi_types.h>
#include <cmos_curi_equipment.h>
#define CHUCK_DOWN 0
#define CHUCK_UP
1
#define SRQ_VALID 0x40
#define SRQ_SITE_MASK 0x0F
//////////////////////////////////////////////////////////////////////////
#ifdef _DEBUG
#define new DEBUG_NEW
#undef THIS_FILE
static char THIS_FILE[] = __FILE__;
#endif
//////////////////////////////////////////////////////////////////////////
class theHandler : public curi::plugins::equipment {
private:
bool m_usePollForSitesReady;
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F – Credence Unified Robot Interface
public:
theHandler(curi::plugins::equipment_controller& cCtrl,
const std::string& name,
const std::string& rev);
bool
bool
bool
bool
InitEquipment(void);
StartAutoTest(void);
GetSitesReady(i2iMap &activeDuts, InterfaceControlEvent & evt);
BinOut(const binInfoArray& binMap);
};
//////////////////////////////////////////////////////////////////////////
CMOS_CURI_REGISTER_EQUIPMENT
curi_register_equipment(curi::plugins::equipment_controller& cCtrl)
{
theHandler *handler = new theHandler(cCtrl, "SQB Protocol", "1.0");
return handler;
}
CMOS_CURI_CLEAR_EQUIPMENT curi_clear_equipment(curi::plugins::equipment*
thisRobot)
{
if (NULL == thisRobot) return false;
delete (theHandler *) thisRobot;
return true;
}
//////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////
theHandler::theHandler(curi::plugins::equipment_controller& cCtrl,
const std::string& name,
const std::string& rev) : equipment(cCtrl)
{
driverID(name);
driverRevision(rev);
m_usePollForSitesReady = false;
}
//////////////////////////////////////////////////////////////////////////
//
// User Initialization function.
//
// Here we query the configuration file to see how many sites the equipment
// supports. If the configuration file does not set the "Sites Supported"
// setting, the default to single site mode.
//
bool theHandler::InitEquipment(void)
{
long l_nSites = 1;
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// Get the number of sites from the configuration file as there
// is no way to read it back from the handler.
if (!ctrl().getL("Sites Supported", l_nSites)) l_nSites = 1;
ctrl().sitesSupported(l_nSites);
// We can use two methods for querying for sites ready, the first is using
// the serial poll (only if sites supported is 4 or lower), the second is to
// use the SQB? & SITES? commands.
m_usePollForSitesReady = false;
if (l_nSites < 5) ctrl().getB("Serial Poll Sets Sites Ready",
m_usePollForSitesReady);
return true;
}
//////////////////////////////////////////////////////////////////////////
//
// User Start Function
//
// As per the sqb protocol, on a start condition we can issue the "STA!"
// Command.
//
bool theHandler::StartAutoTest(void)
{
// As this is a start, lets clear the communications first.
if (!ctrl().clearAllComms()) return false;
// Return the condition of the write command.
return ctrl().curiWrite("STA!");
}
//////////////////////////////////////////////////////////////////////////
//
// Ready To Test? function.
//
//
bool theHandler::GetSitesReady(i2iMap &activeDuts, InterfaceControlEvent & evt)
{
long l_spoll = 0;
if (!ctrl().directCommand("SEROAL_POLL", l_spoll)) return false;
if ((l_spoll & SRQ_VALID) != SRQ_VALID) return false;
unsigned long l_sitesReady = 0;
if (m_usePollForSitesReady) l_sitesReady = l_spoll & SRQ_SITE_MASK;
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F – Credence Unified Robot Interface
else { // Use Slower SQB method.
std::string l_reply("");
if (!ctrl().curiQuery("SQB?", l_reply)) return false;
if (l_reply.length() < 1) return false;
l_sitesReady = (unsigned long)(l_reply[0]) & SRQ_SITE_MASK;
}
if (!l_sitesReady) return false;
long idx;
unsigned long mask;
bool l_haveSite = false;
for (idx = 0, mask = 0x01; idx < ctrl().sitesSupported(); idx++, mask <<= 1)
{
if (l_spoll & mask) {
l_haveSite = true;
activeDuts[idx] = 1;
}
}
if (l_haveSite) evt = START_DEVICE;
return l_haveSite;
}
//////////////////////////////////////////////////////////////////////////
//
// User Send Bin Info function
//
// Build up the output buffer using the defined protocol.
//
// eg, site 1, bin 4
//
site 3, bin 2
//
// Output A BIN 4 C BIN 2
//
bool theHandler::BinOut(const binInfoArray& binMap)
{
char binBuffer[256];
std::string binOut("");
char l_spacer[2];
memset(l_spacer, 0, sizeof(l_spacer));
binInfoArray::const_iterator binIter;
for (binIter = binMap.begin(); binIter != binMap.end(); binIter++) {
sprintf(binBuffer, "%c%c BIN %d", l_spacer, ('A' + binIter>second.siteNumber), binIter->second.hardBin);
binOut += binBuffer;
l_spacer[0] = ' ';
}
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return ctrl().curiWrite(binOut);
}
Putting It All Together
The Serial Polling service request feature mechanism is a very fast means to get the
information about contact sites ready for test via the IEEE communication. The slower
way is polling with the SQB? request command. This mechanism is always active, but the
test system is not obliged to use it.
Additionally bit 7 is set whenever one of the bits 0...3 changes to active state. Bit 7 states
that the test system can start to test the device under test (DUT). This is additional
information, if the test system cannot utilize bits 0...3.
•
Bit 0 set = CS 1 ready for test
•
Bit 1 set = CS 2 ready for test
•
Bit 7 set = Start of test active
Ready to Test
Table 49. User Defined Ready to Test
Multitest
Command
Response
Note
Contact sites
ready for test
SQB?
%1S[0..?]
MT93xx only:
For any combinations of CS Ready
For Test
Example of responses:
0 No CS Ready For Test
1 CS 1 Ready For Test
3 CS 1 and CS @ Ready For Test
? CS 1 TO CS 4 Ready For Test
Handler ID
ID?
%24S
Current
temperature of
contact sites CS
TMP?
%S4:1%S4:1
Command
Diamond ™ Series Mixed Signal (MultiWave) Applications – Student Guide
Format is contact site temp,
contact site temp.
Dual: CS ICS 2
Quad: CS1 + CS 2CS 3 + CS 4
Example: +100.1,+099.9
385
F – Credence Unified Robot Interface
Figure 179. Ready to Test
CURI
User Defined Driver Code
Test Program
Device Interface
Load
kph_initialize?
Yes
User Defined
Initialize
Start?
kph_start?
Yes
User Defined
Start
No
No
Test System
Ready?
Yes
No
All Sites
Complete?
Yes
Yes
Yes
User Defined
Ready to Test?
User Defined
Send Bin Info
Continue
Testing?
No
End Lot
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Using NI SPY to Log GPIB Communication
Using NI SPY to Log GPIB Communication
NI SPY uses National Instruments 488.2 software version 2.2.5 or higher.
Note — To use NI SPY to log GPIB communications, version 1.4.2 or later of the
Diamond Series software must be installed.
To log GPIB communications to using NI SPY:
1. Issue the nispy command to start the NI SPY program.
2. Select Options from the Spy pull-down menu.
Figure 180. Spy Pull-Down Menu
3. Enter 999999 for Call history depth, select Full Buffer from the NI Spy Options
window, and press Ok.
Figure 181. NI Spy Options
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F – Credence Unified Robot Interface
4. Start capture by pressing the Start Capture button (see Figure 182).
Figure 182. Start Capture Button
After the Start Capture option is set, the Ni-SPY application starts logging any GPIB
communication between the test system and the prober/handler.
If the test system is started with the prober/handler DLL loaded. Figure 183 shows the
Ni-SPY log.
Figure 183. NI Spy Capture Log
Note — To save the data to a file:
1. Select Stop Capture from the Spy pull-down menu.
2. Select Save from the File pull-down menu.
Figure 184. Spy Pull-Down Menu
on
Start Capture F8
Stop Capture Ctrl+Break
Options
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