ECE 5550 Solid State Electronics Semiconductor Fabrication Prof. Amar Basu [amar.basu@wayne.edu] Electrical and Computer Engineering Department ECE 5550: Solid State Electronics. Prof. Amar Basu [amar.basu@wayne.edu] 1 Transistor Density 2004 • Semiconduc tor manufacturi ng and miniaturizati on was the real driver behind the semiconduc tor revolution! 1971 Courtesy J. Hoyt, MIT, “Microelectronics Fabrication” Open Course Ware ECE 5550: Solid State Electronics. Prof. Amar Basu [amar.basu@wayne.edu] 2 1 Silicon Semiconductor Manufacturing: From sand to microchips 3 ECE 5550: Solid State Electronics. Prof. Amar Basu [amar.basu@wayne.edu] Resistor Structure/Design Top View Resistor Width (w) N-doped region Pad Resistor Length (L) Oxide coated regions Side View Oxide N-doped region Junction depth/ Resistor thickness (t) P-substrate Resistor Dimensions ECE 5550: Solid State Electronics. Prof. Amar Basu [amar.basu@wayne.edu] • R1: L=34mm, w=180µm • R2: L=34mm, w=43.5µm 4 2 Resistor Fabrication Process • Begin with P-type substrate – P-type Boron doped Si wafer P-substrate 5 ECE 5550: Solid State Electronics. Prof. Amar Basu [amar.basu@wayne.edu] Oxidation • Oxide layer naturally grows if the wafer is exposed to high temperature – Dry: 5 min with 8 L/min oxygen only at 1 atm – Wet: 45 min 1100C 12/8 L/min Hydrogen/Oxygen at 1 atm – Result ~6000 Angstrom film Oxide P-substrate ECE 5550: Solid State Electronics. Prof. Amar Basu [amar.basu@wayne.edu] 6 3 Photoresist Spin Coat • Photoresist is a UV light sensitive material – Shipley 1811 resist: 6000RPM gives ~1 um Photoresist Oxide P-substrate 7 ECE 5550: Solid State Electronics. Prof. Amar Basu [amar.basu@wayne.edu] Photolithography • Photoresist is exposed using a mask – Typical Dose: 15 seconds, 250 nm light Photomask UV Light Photoresist Oxide P-substrate ECE 5550: Solid State Electronics. Prof. Amar Basu [amar.basu@wayne.edu] 8 4 Photoresist development • The regions that were exposed get removed when placed in developer – CD30 developer for ~60 s Photoresist Photoresist Oxide P-substrate 9 ECE 5550: Solid State Electronics. Prof. Amar Basu [amar.basu@wayne.edu] Oxide Wet Etching • Oxide is selectively removed by dipping in Hydrofluoric acid (HF) – 5:1 Buffered Oxide Etch, ~10 minutes Photoresist Oxide Photoresist Oxide P-substrate ECE 5550: Solid State Electronics. Prof. Amar Basu [amar.basu@wayne.edu] 10 5 Photoresist removal • The remainder of the photoresist is removed by using a photoresist stripping solution – Acetone or commercial solution Oxide Oxide P-substrate 11 ECE 5550: Solid State Electronics. Prof. Amar Basu [amar.basu@wayne.edu] Resistor Structure • A solid phosphorous source wafer sublimates at high temperature, releasing dopant atoms.The dopant atoms travel to the silicon wafer and diffuse into the exposed regions (not covered by oxide) • The depth and the doping density are determined by the furnace temperature and the time, and doping disk material – PhosphoSource 250, 800-900C, 1hr Solid Phosphorous Source Wafer Oxide N-doped region P-substrate ECE 5550: Solid State Electronics. Prof. Amar Basu [amar.basu@wayne.edu] 12 6 Diode Fabrication • There are many types of diodes – Substrate (this is the one we will use): easiest, but lowest performance – Epitaxial: best performance, most difficult – Well diode: somewhere in the middle Planar Epitaxial Well http://www.doe.carleton.ca/~smcgarry/ELEC3908/Slides/ELEC3908_Lect_5.pdf 13 ECE 5550: Solid State Electronics. Prof. Amar Basu [amar.basu@wayne.edu] Planar Diode Structure Top View Pad (eg. D4) Metal Line Ndoped Oxide coated regions Side View Metal Line (Aluminum) Oxide + n V P-substrate • The cathode is the n-diffused region. The cathode is the p-type substrate ECE 5550: Solid State Electronics. Prof. Amar Basu [amar.basu@wayne.edu] 14 7 Diode Fabrication Process 15 ECE 5550: Solid State Electronics. Prof. Amar Basu [amar.basu@wayne.edu] Diode Fabrication Process ECE 5550: Solid State Electronics. Prof. Amar Basu [amar.basu@wayne.edu] 16 8 Diode Fabrication Process ECE 5550: Solid State Electronics. Prof. Amar Basu [amar.basu@wayne.edu] 17 Semiconductor Tools and Processes • Furnace – Oxidation: used to deposit films of silicon dioxide (an insulator) – Diffusion: Used for doping • Photolithography: – Spin coater: depositing photoresist – Mask Aligner: Patterning structures • Chemical Etching • Sputtering: depositing metal films ECE 5550: Solid State Electronics. Prof. Amar Basu [amar.basu@wayne.edu] 18 9 Oxidation and Doping Furnace Used for • Oxidation: 800-1200°C, Dry or wet oxidation • Doping: flowing dopant gasses – Col V (As, P) for n-type – Col III (B) for p-type ECE 5550: Solid State Electronics. Prof. Amar Basu [amar.basu@wayne.edu] PWS Furnace 19 Oxidation and Doping Furnace • Used for Diffusion, oxidation ECE 5550: Solid State Electronics. Prof. Amar Basu [amar.basu@wayne.edu] 20 10 Sheet resistivity vs. Doping Time ECE 5550: Solid State Electronics. Prof. Amar Basu [amar.basu@wayne.edu] 21 Junction Depth vs. Temperature ECE 5550: Solid State Electronics. Prof. Amar Basu [amar.basu@wayne.edu] 22 11 Photolithography • Uses light patterning to make small structures • Photoresist: solubility changes in response to light • + and – resists used Courtesy B. Bathula, Solid State Device Technology, Columbia University 23 ECE 5550: Solid State Electronics. Prof. Amar Basu [amar.basu@wayne.edu] Photoresist Spin Coater • Used to apply thin films of photoresist for lithography • Drop of resist placed in center of spinning wafer • Thickness increases with higher viscosity, decreases with higher spin speed Shipley 1800 Series Resists spin curve. http://www.microchem.com http://www.clean.cise.columbia.edu/process/spintheory.pdf ECE 5550: Solid State Electronics. Prof. Amar Basu [amar.basu@wayne.edu] 24 12 Mask Aligner • Used to align masks and expose photoresist during photolithography 25 ECE 5550: Solid State Electronics. Prof. Amar Basu [amar.basu@wayne.edu] Wet Bays Photoresist Developer Bay • Development: Developer chemicals dissolve exposed photoresist ECE 5550: Solid State Electronics. Prof. Amar Basu [amar.basu@wayne.edu] Wet Etching Bay • Wet Etching: removing metals 26 13 Sputter coater • Used for depositing thin film metals BJD1800 27 ECE 5550: Solid State Electronics. Prof. Amar Basu [amar.basu@wayne.edu] Sputter Coating ECE 5550: Solid State Electronics. Prof. Amar Basu [amar.basu@wayne.edu] 28 14 Surface Profilometer • Used to measure thicknesses of deposited films • Stylus profilometry and AFM are two variants http://probe.olympus-global.com/en/product/spm.cfm, http://www.rpi.edu/dept/cie/mncr/dektak8.html 29 ECE 5550: Solid State Electronics. Prof. Amar Basu [amar.basu@wayne.edu] Four Point Probe Measurement • A 4 point probe measurement is more accurate than a regular 2 point because it eliminates the contact resistance of the probes. • A current (I) is passed through the outer probes and induces a voltage (V) in the inner voltage probes • The resistance is R=V/I • Our FPP measures resistivity and sheet resistance as well http://pvcdrom.pveducation.org/CHARACT/4pp.HTM ECE 5550: Solid State Electronics. Prof. Amar Basu [amar.basu@wayne.edu] 30 15 Semiconductor Probe Station • Semiconductor wafer testing • Microprobes contact metal pads on wafer ECE 5550: Solid State Electronics. Prof. Amar Basu [amar.basu@wayne.edu] 31 Miniaturization of Transistor Fabrication Processes ECE 5550: Solid State Electronics. Prof. Amar Basu [amar.basu@wayne.edu] 32 16 Summary • This presentation covers some basic fabrication processes that have been used in the past to make devices • Today’s fabrication technologies are much more sophisticated, and can fabricate devices at the <15 nm scale • Examples of modern devices include – Steppers – E beam lithography – Dry etch – Automated wafer handlers – Automated test stations • Each new fabrication process costs billions of dollars in equipment and engineering costs! ECE 5550: Solid State Electronics. Prof. Amar Basu [amar.basu@wayne.edu] 33 17
