Semi-Custom
Layout Design: Flow, Issues and Solutions
Vinay Kr. Ladwal
1
Floorplanning
Vinay Kr. Ladwal
2
Stage: Floorplanning
Description:
Inputs required to start Floorplanning.
Solution:
Input files to Floorplanning stage are:
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Gate level Netlist (GLN) extracted
from synthesis stage.
Technology file
Design Library
Any (DEF) files (work that has been
partially or fully complete and
passed via design exchange format
(.def ) from top level designers ).
Timing Scenarios Settings (Multi
Mode Multi Corner Files).
Scan_chain.def from DFT unit.
Vinay Kr. Ladwal
3
Stage: Floorplanning
Description:
Netlist
Solution:
GLN contains only logical connections
of a circuit.
The devices in the Netlist are logic
gates.
Vinay Kr. Ladwal
4
Stage: Floorplanning
Description:
What all constitutes as Design
Constraints.
Solution:
Below things can be termed as Design
Constraints:
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Block Shape and Size (predefined
core/die area).
I/O placement pre-fixed.
Top chip-level power plan for Block
level design.
AOCV/POCV corner files specific to
the technology library.
Any other tool related preferred
settings.
Vinay Kr. Ladwal
5
Stage: Floorplanning
Description:
Multi Mode Multi Scenario
Solution:
In design that have multiple modes (i.e.
more than one and other than
functional or more extra functional
modes). Such cases a MMMC approach
is used to report/analyse design for
Timing verification.
This is required so that the design
perform exceptionally under all the
specifications it is designed for.
Types of cells
Vinay Kr. Ladwal
6
Stage: Floorplanning
Description:
Rules for Macro arrangement
Solution:
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Macros talking to each other must
be placed together.
Try minimizing macro stacking.
Pins of macro should be easily
accessible.
Macros orientation should not be
changed for UDSMT. Flipping is
allowed in some case. For DSMT
flipping/rotation is allowed.
Core area must be continuous.
Macros should not cover the I/O’s of
block may result in congestion.
Types of cells
Macro pins should face core area.
Vinay Kr. Ladwal
7
Stage: Floorplanning
Description:
Medium for Macro arrangement
Solution:
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Data Flow from design manual
Fly-line tools
Types of cells
Vinay Kr. Ladwal
8
Stage: Power Planning
Description:
What is power planning?
Solution:
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Adding Metal layers that creates the
power grid to supply VDD/VSS to
the cells inside the block.
Usually top metal layers used for
chip level or block level power
planning.
For Std-cells layer ME1 or ME2
based on structural design of the
Std-cells in the library.
Final goal is to clear every possible
DRC meeting the IR drop target as
set by top level designers, based on
working voltage, frequency and
temperature range of the chip.
Types of cells
Vinay Kr. Ladwal
9
Stage: Power Planning
Description:
Site-rows power planning
Solution:
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ME2 layer used for Std-cell power
planning.
Direction Horizontal.
Spacing: 1.26 microns (40nm Node)
Pitch: 2.52 microns
Width: 0.07 microns (minimum)
Offset: 0.00 microns
Types of cells
Vinay Kr. Ladwal
10
Stage: Power Planning
Description:
Commands Used!
Solution:
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create_pg_mesh_pattern L6 \
-parameters { w1 p1 of1 sp1 } \
-layers { \
{ width:@w1 } \
Variables
Width = w1
Pitch = p1
Offset = of1
Spacing = sp1
{ horizontal_layer: ME6 } \
{ pitch:@p1 } \
{ offset:@of1 } \
}
Vinay Kr. Ladwal
{ spacing:@sp1 ) \
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Stage: Power Planning
Description:
Commands Used!
set_pg_strategy SM6 -pattern \
{\
{ nets:@w1 } \
Solution:
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Variables
Width = w1
Pitch = p1
Offset = of1
Spacing = sp1
{ name: ME6 } \
}\
{ parameters:@p1 } \
-core \
-extension { stop:design_boundary_and_generate_pin }
complile_pg -strategies SM6
Vinay Kr. Ladwal
12
Stage: Power Planning
Description:
Commands Used!
Solution:
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Variables
ME2 layer
create_pg_std_cell_conn_pattern \
-check_std_cell_drc true P_std_cell_rail \
-layers { ME2 }
set_pg_strategy S_std_cell_rail_VSS_VDD \
-core \
-blockage { macros_with_keepout:$all_macro } \
-pattern
{\
{ pattern:P_std_cell_rail } \
{ nets: { VSS VDD } } \
compile_pg \
}
-strategies \
{ S_std_cell_rail_VSS_VDD }
Vinay Kr. Ladwal
13
Stage: Power Planning
Description:
Issues!
Solution:
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Floating Macros
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Missing Vias
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Floating Nets
Less than required Spacing
Vinay Kr. Ladwal
14
Stage: Floorplanning
Description:
Pre-placement preparation
Solution:
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Adding boundary/end-cap cells and
tap cells to the design.
Create pg connections between
power/ground and cells in design.
Using “connect_pg_nets”
Verify the continuity of boundary
cells
Verify PG connectivity and logical
legality.
Import Low power Setup.
Vinay Kr. Ladwal
15
Stage: Floorplanning
Description:
Sanity checks issues!
Solution:
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Check PG DRC
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Check Boundary cells
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Check Physical DRC
Check WELL connectivity
Check PG connectivity
Check Legality
Check scan-chain(s)
Report Timing and QoR
Vinay Kr. Ladwal
16
Placement
Vinay Kr. Ladwal
17
Stage: Placement
Description:
Inputs to placement stage.
Solution:
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Updated Block from Floor plan
Stage
Timing Setup (max corners)
Design Constraints
App options setting files
NDR Rules
Design Library (continuing from
Floor plan stage)
Vinay Kr. Ladwal
18
Stage: Placement
Description:
Flow!
Solution:
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Import the layout from floor plan
and save
Setup the timing scenarios for setup
analysis
Perform the
customization
tool
settings
and
Insert Spare cells
Placement
Create P/G connections
Run DRC / Timing checks
Save the block
Vinay Kr. Ladwal
19
Stage: Placement
Description:
Two pass Placement
Solution:
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Initial Place is the very elementary
stage in which the algorithm starts
by disconnecting the scan chain and
then simply run a course placement.
Keeping prime criteria as the
interconnect lengths between cells
should be minimum.
If we run SPG flow since the course
placement is already done this step
is skipped during two pass
placement.
Vinay Kr. Ladwal
20
Stage: Placement
Description:
Two pass Placement
Solution:
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Initial DRC also
known
as
HFS/DRC stage is responsible for
buffer tree generation.
In a design when we have high fanout signal like set, reset, clear .etc.
We need to generate a buffer tree for
this similar to clock tree.
The stage runs high fan-out
synthesis and then clear all the
possible DRC.
Synthesis occurs in three steps:
generate VR, insert buffers and
improve transition, delete the VR.
VR stands for virtual route also
known as global route.
Vinay Kr. Ladwal
21
Stage: Placement
Description:
Two pass Placement
Solution:
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Initial opto is a timing optimization
stage where algorithm simply run
Direct Timing Driven Placement
(DTDP).
Final Place stage the algorithm runs
am incremental placement where
based on efforts set power,
performance
and
timing
optimization are done at the same
time controlling routing congestion.
Final opto is again responsible for
final effort in timing optimization
then legalizing the whole design and
later recreating new scan chain.
Vinay Kr. Ladwal
22
Stage: Placement
Description:
Checks!
Solution:
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Check P/G connectivity
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Check Legality
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Check DRC,
Check Routability
Check WELL connectivity
Check ports Abnormality
Report Timings and analyse
Vinay Kr. Ladwal
23
Stage: Placement
Description:
Issues!
Solution:
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Controlling congestion
Cells
cells)
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not
legalized
(overlapping
Overlapping metal layers PG DRC
Shorts
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Blocked Ports (min/max constraints)
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Swapped WELL connections
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Unconnected WELL connections
Abnormal Port Shape/Size
Over Core utilization
Setup Timing violations
Vinay Kr. Ladwal
24
Stage: General
Description:
Extra Scripts Used!
Solution:
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add_spare_cells.tcl
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dont_use_cells.tcl
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connect_pg_nets.tcl
pg_connections.tcl
set_lib_cell_purpose.tcl
Vinay Kr. Ladwal
25
Clock Tree Synthesis
Vinay Kr. Ladwal
26
Stage: Clock Tree Synthesis
Description:
Inputs to CTS stage.
Solution:
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Updated
Stage
Block
from
placement
Timing Setup (All corners)
Design Constraints
App options setting files
NDR Rules
Design Library (continuing from
Floor plan stage)
Vinay Kr. Ladwal
27
Stage: Clock Tree Synthesis
Description:
Flow!
Solution:
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Import the layout from placement
stage and save
Setup the timing scenarios for hold
and setup analysis.
Set uncertainty value for each clock
domain
Perform the
customization
tool
settings
and
Clock_opt
Compute new latency
Create P/G connections
Run DRC / Timing checks
Save the block
Vinay Kr. Ladwal
28
Stage: Clock Tree Synthesis
Description:
Clock_opt
Solution:
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Build_clock is the primitive stage in
clock tree synthesis. Here the tree
generation is similar like the High
fan-out buffer tree. Difference is we
have some targets to satisfy
together
with
clearing
Hold
violations.
It starts with Building a virtual
route. There after it adds buffers or
inverters as required to improve
transition.
The virtual route structure follows
the NDR rules given by user.
Vinay Kr. Ladwal
29
Stage: Clock Tree Synthesis
Description:
Clock_opt
Solution:
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Route_clock stage based on the
greated virtual route the tool creates
metal traces for the same following
the NDR rules.
It starts as track assignments and
then detailed route.
Tracks are the path that tool uses as
reference to place metal layer and
intersection of two orthogonal tracks
are used for via insertions.
The clock tree is almost ready at
this stage with improved transition
in clock signal.
Vinay Kr. Ladwal
30
Stage: Clock Tree Synthesis
Description:
Clock_opt
Solution:
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Final_opto stage is responsible for
CCD or classic optimization.
The tool tries to meet all the hold
violations in the design keeping a
track of setup time such that
clearing hold should not affect a
already meeting setup time.
Also the tool is responsible to meet a
skew target while optimizing the
clock tree which should be ideally
zero but practically is kept between
5%-10% of the clock period.
CCD stands for concurrent clock and
data optimization.
Vinay Kr. Ladwal
31
Stage: Clock Tree Synthesis
Description:
CCD ( concurrent clock and data
optimization )
Solution:
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CCD is a algorithm that is
responsible for Hold analysis and
optimization considering the data
path also.
By the name suggested it optimizes
clock capture and data path both.
Added
perform
optimizations also.
further
PPA
For example when it need to
increase AT to clear hold violation it
considers that the setup time
shouldn't violate while doing that
hence optimizes the data path also.
Vinay Kr. Ladwal
32
Stage: Clock Tree Synthesis
Description:
NDR Rules
Solution:
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NDR rules stands for non default
routing rules .
Here we set the maximum allowable
layer and minimum allowable layers
for routing.
Added special spacing rules can also
be added for example in CTS thick
nets that have twice the width than
minimum width will have double
spacing also called as “double with
double spacing”.
Vinay Kr. Ladwal
33
Stage: Clock Tree Synthesis
Description:
CTS optimization
Solution:
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CTS optimization is generally done
using global skew.
The tool checks for the maximum
and minimum skew from a node and
the their difference should be
present in target range. If it is
achieved it checks next level else
transition is improved at that node.
Similarly the tool can also use local
skew with each related flop as
parameter for optimization only at
cost of increased runtime.
Vinay Kr. Ladwal
34
Stage: Clock Tree Synthesis
Description:
Checks!
Solution:
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Check P/G DRC
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Check P/G Connectivity
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Check Physical DRC
Check routes
Check LVS
Check Routability
Check Legality
Report Timing and analyse
Vinay Kr. Ladwal
35
Stage: Clock Tree Synthesis
Description:
Issues!
Solution:
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Zroutes issues shorts and opens
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Un-routed clock nets
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Minimum Spacing
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Clock/power shorts
Clock/clock shorts
Blocked ports.
Minimum Area
Vinay Kr. Ladwal
36
Routing
Vinay Kr. Ladwal
37
Stage: Routing
Description:
Inputs to Routing stage.
Solution:
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Updated Block from CTS stage
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Design Constraints
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Timing Setup (All corners)
App options setting files
NDR Rules
Design Library (continuing from
Floor plan stage)
Vinay Kr. Ladwal
38
Stage: Routing
Description:
Flow!
Solution:
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Import the layout from CTS and
save
Setup the timing scenarios for hold
and setup analysis.
Set latest latency and compute new
uncertainty.
Perform the
customization
tool
settings
and
Route_opt
Create P/G connections
Run DRC / Timing checks
Save the block
Vinay Kr. Ladwal
39
Stage: Routing
Description:
Route_opt
Solution:
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Routing is done in three stages first
a new global route is created. As
according to NDR if 2W2S was used
it might have consumed a lot of
resources and we need to take care
of spacing issues to that if FAT
metals.
So a new global_route is created
then track assignment is done, at
last it performs detailed routing.
Apply DFM rules.
Last step of detailed_route stage is
called “search and fix” where it
scans the design and fix all possible
DRC and antenna violation.
Vinay Kr. Ladwal
40
Stage: Routing
Description:
Checks!
Solution:
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Check P/G DRC
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Check P/G Connectivity
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Check Physical DRC
Check routes
Check LVS
Check Legality
Report Timing and analyse
Vinay Kr. Ladwal
41
Stage: Routing
Description:
Issues!
Solution:
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Zroutes issues shorts and opens
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Minimum Spacing
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Un-routed nets
Minimum Area
Antenna Issues
Vinay Kr. Ladwal
42
What Else?
Stage: Logic Equivalence Check
Stage: Physical Verification
Stage: Layout Versus Schematic
Solution:
Solution:
Solution:
Description:
Inputs to LEC stage.
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Updated Netlist after Routing
First synthesised Netlist
Description:
Inputs to PV stage.
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Current Layout
Technology File (design
rules)
Vinay Kr. Ladwal
Description:
Inputs to LVS stage.
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Final Layout
Latest updated Netlist
43
Solutions!
Vinay Kr. Ladwal
44
Floating Macros
Cause and Solution
• As visible the Pitch select for power mesh was
properly making power mesh to have VDD/VSS
strips on each macro and hence they will not get
floating.
Illustration
• If pitch was little larger than what this result is
for it might happen that a metal rail will not cross
the macro and hence now PG connections will be
made for that. This leads to floating macro.
• We usually take height of the smallest macro as
reference to start out pitch value and then
increase/decrease it slowly to meet our
requirement.
• Some time when a trace misses a macro by a
small factor offset can be used to move the whole
mesh and solve this floating issue.
Vinay Kr. Ladwal
45
Floating Nets
Cause and Solution
• Blue(ME7) main power strips that supplies to red
(ME6) for Macro power planning and further they
need to supply yellow (ME) for std.cells.
Illustration
• So if we see carefully if both the red strips are
connected using via, then the ME2 yellow strip
second from top supposed to be receiving a
connection might fail to connect if the via belongs
to second pole in the circuit. That means since tool
will experience a DRC violation here such that a
VDD via is too close to VSS via going to ME2 from
ME7. The tool will not drop a via and it will end
up a missing via.
• Ways to prevent is using proper pitch to maintain
that distance or can use offset if there exist very
few cases.
Vinay Kr. Ladwal
46
Missing Vias
Cause and Solution
• Floating nets are due to missing vias, so the
solution is kind of similar.
Illustration
• Other cause may be different width nets that are
needed to be connected. If the net from which a
via is dropped to another is thinner then the other
one then also this missing via issue may arise.
• Usual issues in power plan can be solved by
adjusting Pitch and offset value.
Vinay Kr. Ladwal
47
Less than Required Spacing
Cause and Solution
• As shown in the figure how width, spacing, pitch
and offset.
Illustration
• One thing to keep in mind is spacing is directly
related to width. And by that we mean is
according to fat metal information in technology
file. The spacing between two signal/power nets is
based on the width of the individuals and their
parallel running length.
• So increase parallel running length will increase
spacing similarly increase in width also increases
spacing requirement.
• So the spacing calculation should be done using
fat table values and then the issue will be
resolved.
Vinay Kr. Ladwal
48
Understanding Fat-Metal Rules
Cause and Solution
• Fat table is available in technology files within
layer information.
• Tool refers that when it needs to verify the
spacing between two metal tracks are correct or
not.
Illustration
fatmetaltabdimentions
fatmetaltabparallellength
= { 0.00 0.10 0.20 0.30 0.40 0.50 }
fatmetaltabspacing
= { 0.07 0.09 0.10 0.20 0.40 0.50
fatmetaltabwidth
• It starts as parallel length of the nets are
measured and then the fattest metal width is
taken.
• Based on the values the tool uses the 2D spacing
table with rows as parallel running length and
column as width a best spacing value is selected
that is used for both verifying post routing and
deciding spacing before routing.
=6
= { 0.00 0.07 0.09 0.10 0.14 0.20 }
0.09 0.10 0.20 0.40 0.50 0.50
0.10 0.20 0.40 0.50 0.50 0.50
0.20 0.40 0.50 0.50 0.50 0.50
0.40 0.50 0.50 0.50 0.50 0.50
}
0.50 0.50 0.50 0.50 0.50 0.50
• Example if of a 6x6 fat table.
Vinay Kr. Ladwal
49
Boundary Cells Continuity
Cause and Solution
• Yellow coloured area is blockage and blue colour
cells are boundary cells.
Illustration
• If the blockage that assigned is soft then
according to tool that place is open for std. cell
placement.
• And such area should be capped by boundary
cells, but when its visible that area is very small
so tool will not place any boundary cell there and
will show boundary cell continuity error.
• To solve the issue simply use hard keepout or
hard placement blockages.
Vinay Kr. Ladwal
50
Swapped WELL Connections
Cause and Solution
• Usual case when the command for connecting PG
nets and well pins was faulty.
• Verify properly the Nwell and Pwell pins using
command report_cells.
• Then use that reference name in command
connect_pg_nets –nets VDD/VSS and create
individual connections.
Vinay Kr. Ladwal
51
Scan-Chain Discrepancies
Cause and Solution
• Scan chain issues arises only if there some
changes took place at the floor plan stage after
importing scan chain info due to any unknown
cause.
• Only solution in such issues is re-import the
scan.def and verify if it works or else proceed with
next step in flow reporting the issue with DFT
team.
• Here proceeding ahead is allowed as at placement
stage an new scan chain will be build. Where the
issue will be most probably resolved.
Vinay Kr. Ladwal
52
Blk-Blk Overlap/Macro overlap
Cause and Solution
• A human fault while arranging macros makes
this issues.
• Point to take care is use align and distribute tool,
this helps to reduce the issues to a great extent.
Apart from that is using a keepout margin in
macro take care to use include_keepout option in
align command to prevent blk-blk overlap issues.
Vinay Kr. Ladwal
53
Congestion
Cause and Solution
• After placement due to optimization tool inserts a
lot of cells in design and tries its best to control
congestion where even then at some places there
exist routing congestion.
• So for congestion in core area we try controlling
cell and pin density to reduce routing congestions.
Here various types of partial blockages can be
used.
Illustration
• Channel Width =
.
∗
• Channel Width =
∗
• For specific channel congestion formulas are
available that are used to calculate channels
width to create a vacant space which can be used
for easy routing to reduce congestion.
Vinay Kr. Ladwal
54
Un-legalised Cells
Cause and Solution
• If un-legalised cells are present due to over
utilization of core are consider re-designing/reconstraining the design.
• Causes can be over use of blockages.
• And if cells are randomly looking un-legalised
then the reason could be the cells were added
after the placement stage was finished.
• So
legalise
then
using
legalise_placement –cell <name>
• Or
manually
arrange
legalise_placement.
and
command
simply
run
Vinay Kr. Ladwal
55
Blocked Ports
Cause and Solution
• Usual cause of blocked ports is the min/max
constraint.
• Else this can be due to a poor floor plan where the
macro cells that were supposed to be talking with
each other were kept far away in design.
• If floor plan in the cause the only solution is redoing the floor plan.
• Else if min/max constraint is the issues verify the
NDR rules and correct them if needed referring to
the top level designers.
Vinay Kr. Ladwal
56
Unconnected WELL’s
Cause and Solution
• Unconnected well will only when you forgot to
create PG connections.
• Use command connect_pg_nets to create those
power ground connection with the cells.
• This is a logical DRC issues as we define the
power connectivity only and are not physically
routing them yet.
Vinay Kr. Ladwal
57
Zroute Shorts/Opens
Cause and Solution
• During routing if tool experience to cross to nets
and due to some reason or rules it cannot use
second metal layer while routing. That case we
create short error.
Illustration
• To solve we simply create metal jump using one
higher metal layer.
• For opens we use commands first to solve such as
route_groups or route_eco, if this is not working
we go for manual routing.
Vinay Kr. Ladwal
58
Minimum Spacing
Cause and Solution
• Minimum spacing is value provided in technology
file. So if the spacing is smaller than minimum
this issues will arise. Another case if metal in fat
than minimum then also this issue will come
condition is spacing required will be larger than
minimum.
• To solve calculate the accurate spacing and edit
the route to solve. Can use snipping/stretching
tools.
Vinay Kr. Ladwal
59
Minimum Area
Cause and Solution
• Minimum area is a requirement to meet DFM
and value is specified in technology file. Whenever
the area of a net is less the minimum value this
DRC error will be shown.
• To solve take minimum area value from
technology file and divide that by width of track.
Then edit and stretch the track length equal to
calculated value.
Vinay Kr. Ladwal
60
Antenna Violations
Cause and Solution
• Antenna is a phenomenon that occurs during
manufacturing plasma etching process. The large
exposed metal behaves as antenna and charge in
kV range gets induced in them.
Illustration
• At that moment if the metal is connected to a gate
of device the equivalent area of gate is larger than
the gate area connected to it creates antenna
violation under DFM category.
• To solve the issues we use two methods as
illustrated in second and third figures the
jumping method or antenna diode insertion
method.
• Both are effective priority is given to jumping as it
is easy since after placement on substrate you will
hardly find any space for diode placement.
Vinay Kr. Ladwal
DIODE
61