Truechip VIPs, Silicon IPs
&
Design Services
Think VIP - Think TRUECHIP
12
Glorious Years
of
serving our
Customers
TRUECHIP - Introduction
Leaders in
P3 framework
India R&D
Centers
- Verification IP
- Proven Solution
- Silicon IP
- Perfect Integration
-Noida
- GUI
- Prompt Support
-Bengaluru
- Automation
- Debug
- Design Services
-Pune
-Hyderabad
Team Profile
- 200+ Engineers
- Avg Exp 6+ years
Truechip-Global Presence
Global Presence
Europe/Germany
China
UK
Japan
US
Korea
Taiwan
Israel
India
Truechip – Our Businesses
Verification IPs
NoC Silicon IP
GUI based Debug
- Crossbar Type
&
- Mesh Type
Automation Products
Verification Services
Other Design Services
IP/ SOC/ASIC,
Post Silicon Validation
GLS/ Timing sims
RTL, PD, DFT, AI/ ML SW
Milestone Journeys
Truechip’s Product Portfolio
Verification IP Products
8.1 Million Man-hours
of Experienced Team
500 +
VIP’s sold globally
50 +
Worldwide Customers
TruEYE™ : Debug & Automation GUI#
Verification Outsourcing: The Truechip Advantage
Verification IP Advantage:
• The team is well versed with all the standard protocols
• Well versed with SV and UVM methodology
Expertise in SOC Verification
• Automotive, Networking, AI and Cloud
• Working with Tier 1 customers in India
• Also working in ODC model with multiple international customers
Expertise in GLS, ECO (even using Spare cells) and Low Power verification
Experience with various processors: ARM, ARC, RISC-V
Expertise in Setup of SOC Testbench from scratch and bringup of GLS TB
10
Engineering Services:
Physical Design & Validation
Physical Design
• Experience with 7/ 10/ 14/ 16/ 22/ 28 NM Technologies
• RTL to GDSII:
• Logic Synthesis, timing constraints, Logic optimization for better correlation
• Floor planning, partitioning, Placement, clock-tree optimization
• Routing, Post Route Optimization, Timing Sign-off
PPA (Power, Performance & Area) Optimization
• Special structures for clocking and power networks
• Physical Verification, Physical design for manufacturability and yield
• Flow development and methodology development
• Management of design data and constraints
• Power Analysis, optimization. Power delivery network (PDN) design and analysis
Post Si Validation:
• Electrical Validation of Analog IP designed on 16/28/40/55/180 nm process nodes.
• Electrical Validation of High Speed and Mixed signal Analog IP’s like SAR ADC, IRC, Crystal Oscillators, PLL, PCIe, DDR3/4, LPDDR2/4, Temperature
Sensor, LIN PHY, CAN PHY
• Board bring-up and bench test setup preparation
• LabVIEW based test Automation development.
Engineering Services: DFT
Areas of expertise:
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•
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DFT Architecture design, RTL coding, IP and SoC verification
DFT flows: SCAN/MBIST/JTAG-TAP/BSCAN & DFT Simulations
Checking collage collaterals and getting model built clean
Ensuring DFT coverage is met
Debug Test failure; fixing integration issues
Adjacency tools for DFT knowledge: synthesis, timing analysis, constraining, equivalency
checking, RTL rules and lint checks
• Filing bugs (JIRA) and updating progress (Excel)
Vietnam / India Story
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India and Vietnam go a long way
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•
•
Buddhism - One of the prominent religion originated in India promoting
peace and prosperity in the world.
50 years of diplomatic ties.
Ever growing Mutual Cooperation in Defence and Oil Exploration.
Ever growing business relationship between India and Vietnam.
•
•
Vietnam and India among top 10 trading partner of each other with bilateral
trade touching ~$10B.
Tata, ESSAR, SRF, Adani Group and many more…
Truechip Vietnam Vision
Make Truechip Vietnam CoE
for VLSI development to
support and GROW
our International Client Base.
Roadmap
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150
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2022
2023
2023 - Q3 2024 - Q1 2024
2024 - Q3 2025 - Q1 2025
- Q1 2023
2025 - Q3
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