PROJECT REPORT
ON
TSPC BASED D FLIP FLOP
(VLSI DESIGN)
Submitted by:
Sahil Jakhar (2018H1230232P)
Vishal Singh Mandloi (2018H1230244P)
Rajat Porwal (2018H1230249P)
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Problem statement #1
Implement TSPC positive edge – triggered D Flip Flop. Compute its setup and hold time. Optimize its
power delay product.
ABSTRACT
Designing of positive and negative edge triggered TSPC (True single phase clock) based D flip flop is
performed alongwith suitable calculation and simulations on Cadence tool. Various design parameters
like propagation delay(high to low and low to high), setup time, hold time, power dissipation (static as
well as dynamic) are measured and optimized.
Using the above optimized TSPC based positive edge triggered D flip flop, SISO (Serial In Serial Out)
and SIPO (Serial In Parallel Out) are implemented and the functionality of the above designed
application is verified.
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1. Introduction
1.1 D flip flop
The ‘D’ in D flip flop stands for "data". This flip-flop stores a 1 bit value that is on the data line. It can
be thought of as a basic memory unit. D flip-flop can be built using NAND gates or with NOR gates.
The major applications of D flip-flop are to introduce delay in timing circuits, as a buffer and
as building blocks for shift registers. The symbol of a D flip flop is shown in Figure 1.1.
Figure 1.1: Symbol of a D flip flop.
The truth table of a D flip flop is shown in Figure 1.2.
Figure 1.2: Truth table of a D flip flop.
The operation of the D type flip-flop is as follows: Any input appearing (present state) at the input D,
will be produced at the output Q in time t+1 (next state) on encountering either the positive edge or
negative edge of the clock as per the design. The D-flip flop just transfers the input to the output on
the ACTIVE (positive/negative) edge of the clock.
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1.2 TSPC D flip flop
In two phase clocking schemes, there are chances of clock overlap which can lead to disturbances in the
output. This problem can be eliminated if there is only a single clock used throughout the circuit. The
True Single-Phase Clocked Register (TSPCR) was first proposed by Yuan and Svensson. In the design
of the edge triggered D flip-flop (positive or negative), TSPC logic is being used. The circuit consists of
alternating stages called n-blocks and p-blocks and each block is being driven by the same clock signal.
The circuit consists of 11 transistors. The true single phase clock (TSPC) is common to the dynamic flipflop which performs the flip-flop operation with little power and at high speeds.
Figure 1.3 shows the design of a single-phase edge-triggered D flip flop. When CLK = 0, the input
inverter is sampling the inverted D input on node X. The second (dynamic) inverter is in the precharge
mode, with M4 charging up node Y to VDD. The third inverter is in the hold mode, since M8 and M7
are off. Therefore, during the low phase of the clock, the input to the final (static) inverter is holding its
previous value and the output Q is stable. On the rising edge of the clock, the dynamic inverter M4- M6
evaluates. If X is high on the rising edge, node Y discharges. The third inverter M7-M8 is on
during the high phase, and the node value on Y is passed to the output Q. On the positive phase of the
clock, note that node X transitions to a low if the D input transitions to a high level. Therefore, the input
must be kept stable till the value on node X before the rising edge of the clock propagates to Y. This
represents the hold time of the register (note that the hold time less than 1 inverter delay since it takes 1
delay for the input to affect node X). The propagation delay of the register is essentially three inverters
since the value on node X must propagate to the output Q. Finally, the set-up time is the time for node
X to be valid, which is one inverter delay.
Figure 1.3: Positive edge triggered D flip flop.
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1.3 Design methodology
1.3.1 Equivalent transistor sizing calculation
W
𝐒𝐭𝐚𝐠𝐞 : ( L)
eq−p
W
= 2.45μ
𝐒𝐭𝐚𝐠𝐞 : ( )L
W
∴ ( L ) = 2μ (For M5 & M6)
p
W
neq
W
eq−n
= 1μ
W
∴ ( ) = 2μ (For M8 & M9)
eq−p
W
= ( ) = 2.45μ (For M7)
L
W
eq−p
= ( L ) = 2.45μ (For M4)
W
𝐒𝐭𝐚𝐠𝐞 : ( L)
W
( )
L eq−p
L n
L
W
(L)
n
W
W
( )
n
= ( L ) = 1μ (For M3)
𝐒𝐭𝐚𝐠𝐞 : ( L)
= 1μ
W
∴ ( L ) = 4.9μ (For M1 & M2)
(L)
eq−n
W
eq−n
W
= ( L ) = 1μ (For M11)
n
= ( ) = 2.45μ (For M10)
L
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1.3.2 Transistor sizing calculations
Calculation of 𝝁 /𝝁𝒑 for transistor sizing:-
circuit for nmos
circuit for pmos
(W/L ratios for both the transistors have been taken equal to 3)
The transistors are biased such that they always operate in saturation region. The current in saturation
region is given as:
for nmos
for pmos
𝐼=
2
(
𝐺𝑆−
)
2
⇒ √𝐼 = √( 2 ) (𝐺𝑆 − )
---------(1)
---------(2)
𝐼=
⇒ √𝐼
2
(
𝐺𝑆−
=√
)
(
2
2
---------(3)
− )
---------(4)
𝐺𝑆
Assuming turn on current of transistors to be 1𝜇𝐴, the threshold voltage () comes out to be 0.467V
(approx) for nmos transistor and -0.5489V (approx) for the pmos transistor.
𝐼 𝑣 𝐺𝑆 curve for nmos
𝐼 𝑣 𝐺𝑆 curve for pmos
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From the 𝐼 𝑣 𝐺𝑆 curves, at point A, =3.46mA & 𝑽𝑺 = 𝟐𝟎. 𝐦𝐕 and at point B, =2.91mA
& 𝑽𝑺 = −. 𝐦𝐕.
substituting these values in equation (2) and (4)
for nmos
3.46m (𝐴)2 = √(
1
2
) (620.8 − 467.9 )
⇒ = 1.03 × 10−3 A/V2
⇒ 𝜇𝐶𝑥 ( ) = 1.03 × 10
for pmos
2.91 (𝐴)2 = √(
1
2
) (−749.5 − (548.9 ))
⇒ = 4.2 × 10−4 A/V2
−3
⇒ 𝜇𝐶𝑥 ( ) = 4.2 × 10
𝑊
−4
𝑊
as we have taken ( ) = 3,
we have taken ( ) = 3,
⇒ 𝜇𝐶𝑥 = 3.44 × 10−4 A/V2
-------(5)
⇒ 𝜇 𝐶𝑥 = 1.4 × 10−4 A/V2
using equations (5) and (6),
𝜇𝑥
3 . 44× 10−4
𝜇𝑥
1.4×10−4
=
= 2.457
------(7)
--------(6)
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1.4 Schematic & Outputs
1.4.1 Positive edge triggered D flip flop
The schematic of positive edge triggered D flip flop is shown in Figure 1.4.
Figure 1.4: Schematic of positive edge triggered D flip flop.
The symbol of the TSPC based D flip flop is generated from the above schematic and is shown in
Figure 1.5.
Figure 1.5: Symbol and final implementation of positive edge triggered D flip flop.
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1.4.1.a Output waveform
The output waveform of a positive edge triggered D flip flop is shown in Figure 1.6.
Figure 1.6: Output waveform.
1.4.1.b Propagation delay measurement (TT process corner)
Figure 1.7: High to low propagation delay.
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Figure 1.8: Low to High propagation delay.
1.4.1.c Setup time measurement (TT process corner)
Figure 1.9: Setup time calculation.
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1.4.1.d Hold time measurement (TT process corner)
Hold time was observed to be 0 ns.
1.4.1.e Power dissipation measurement (TT process corner)
Dynamic power dissipation:
Figure 1.10: Dynamic power calculation waveform and value.
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Static power Calculations:
The static power is calculated at each of the 4 possible stable states of operation(namely at CLK=0
D=0, CLK=0 D=1, CLK=1 D=0 and CLK=1 D=1) of the D-flip flop.
Figure 1.11 below shows one specific case when CLK=1 and D=1 (output has stablilized to its
supposed value). Later, the power consumed during these input and output combinations will be
averaged together to produce the static power.
1 ∫ 2 × 𝐼()d
𝑃=
2 −1 1
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Figure 1.11: Static power dissipation waveform and calculated values.
The power for other 3 cases is calculated in a similar manner. the final results have been summarized
in the table below.
CLK
0
0
1
1
D
0
1
0
1
Power
68.7nW
38.3nW
1.26nW
0.2496uW
averaging the above results gives,
𝑃𝑎𝑖𝑐 =
68.7 + 38.3 + 1.26 + 249.6
4
= 89.46
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1.4.2 Negative edge triggered D flip flop
The schematic of negative edge triggered D flip flop is shown in Figure 1.11
Figure 1.12 Schematic of negative edge triggered D flip flop.
Figure 1.13: Symbol and final implementation of negative edge triggered D flip flop.
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1.4.2.a Output waveform
The output waveform of a negative edge triggered D flip flop is shown in Figure 1.13.
Figure 1.14: Output Waveform.
1.4.2.b Propagation delay measurement (TT process corner)
Figure 1.15: High to Low Propagation delay.
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Figure 1.16: Low to High Propagation Delay.
1.4.2.c Setup time measurement (TT process corner)
Figure 1.17: Setup Time Measurement.
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1.4.2.d Hold time measurement (TT process corner)
Hold time was observed to be 0 ns.
1.4.2.e Power dissipation measurement (TT process corner)
Dynamic power dissipation:
Figure 1.18: Dynamic power calculation waveform and value.
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1.5 Maximum operating frequency calculation
Maximum frequency of operation is of prime importance while designing any sequential circuit.
To calculate the same, the following relation is used:
Tclk ≥ tsetup + tcq
𝑓clk−max =
1
Tclk
From the obtained values of setup time and clock to output delay, 𝑓clk−max comes out to be 1.13 GHz.
(Although, the design starts to produce significant glitches after 0.9 GHz.)
Figure 1.19: Output waveform at 0.9GHz.
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Summary of Results
Positive edge triggered DFF
𝝉𝑷𝑳(nS)
𝝉𝑷𝑳(nS)
𝝉𝑷𝒂𝒈 (nS)
𝒑(pS)
𝑷𝒚𝒂𝒊(𝜇)
TT
0.84
0.86
0.85
30
0.42
FF
0.69
0.72
0.705
30
0.467
SS
1.03
1.03
1.03
30
5.83
TT
0.91
0.84
0.875
10
0.41
FF
0.75
0.70
0.725
33
0.363
SS
1.11
1.01
1.06
35
5.35
Negative edge triggered DFF
𝝉𝑷𝑳(nS)
𝝉𝑷𝑳(nS)
𝝉𝑷𝒂𝒈 (nS)
𝒑(pS)
𝑷𝒚𝒂𝒊(𝜇)
Configuration(TT)
Positive Edge Triggered
Negative Edge Triggered
Total Power(𝜇)
0.51
0.49
Avg Delay(nS)
0.85
0.875
FOM(power-delay product)
0.4335 fJ
0.4288 fJ
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APPLICATION:
Above designed edge triggered D Flip Flop can be used to implement Registers. The basic building
block of a register is a D Flip Flop. A register is used to hold multiple bits at a time.
Four different types of registers can be designed, namely
1)
2)
3)
4)
SISO
SIPO
PISO
PIPO
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In the design, SISO and SIPO have been implemented. Figure 1.20 depicts the schematic of a SISO
and SIPO register.
Figure 1.20: Schematic of SISO and SIPO registers.
Figure 1.21: Output Waveforms of SISO and SIPO Registers.
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References
1. Digital Integrated Circuits: A Design Perspective Author: Jan Rabey , Prentice Hall, 2005.
2. CMOS Digital Integrated Circuit, Analysis and Design, Sung-Mo Kang and Yusuf Leblebici,
Publisher: McGraw- Hill Companies, Inc.2003.
3. J. Yuan and C. Svensson, “High-speed CMOS circuit techniques,” IEEE J. Solid-State
Circuits, vol. 24, no.1, pp. 62–70, Feb. 1989.
4. Uming Ko; Balsara, P.T. “High-performance energy efficient D-flipflop circuits” IEEE
Transactions on Very Large Scale Integration(VLSI) systems, Volume 8, Issue 1, Feb. 2000
Page(s):94 – 98.
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