A Brief Introduction to Liberty Variance Format – LVF Liberty Variance Format – LVF – is the most important change to sign-­‐off timing since the introduction of CCS modeling in 2004. LVF introduces significantly better methods for handling on chip process variation during physical design and timing sign-­‐off to improve yield, performance and time to market. If your physical design team has been struggling to meet timing and power closure with OCV or AOCV, now is the time to start the adoption process. LVF is the best approach for modeling on chip process variation in combination with CCS models. LVF represents variance uniquely for each load/slew/arc point in a cell, and enables sign-­‐off timing and optimization to come much closer to true Monte Carlo SPICE results. It eliminates much of the excessive pessimism that comes from using OCV, as well as, AOCV/SBOCV. LVF, part of the Liberty Modeling Standard, is now supported by all of the leading static timing analysis (STA) tools. Whether your timing vendor calls it POCV or SOCV, all of them depend on LVF to supply the data. 2015 will see LVF integration into physical design tools, starting with late stage power and timing optimization in the first half of the year, with tape-­‐outs not far behind. LVF provides a safe, practical approach to managing process variance that will deliver: 1. Improved Yield: by driving the STA and optimization tools to center the design about the true critical nets, yield should increase around the primary sign-­‐off corners. 2. Improved Power and Speed: by eliminating the excessive guardbands from OCV, there should be more ‘safe’ slack that can be applied to reduce power, and to drive up clock frequency without penalizing yield. 3. Faster Time to Market: The easier it is to find slack to hit yield, power and speed targets, the easier it is to close timing with confidence. ©2015 CLK Design Automation, Inc. All rights reserved. The CLK logo, Variance FX, Path FX and Clock FX are trademarks of CLK Design Automation, Inc. All others are properties of their respective holders. 1 What is LVF? Liberty Variance Format models the impact of on chip process variance on timing. LVF is part of the overall Liberty Library Modeling Standard, which covers all aspects of creating timing, power and noise models, such as CCS or NLDM. LVF adds variance information that can be used with the CCS delay models. Every arc/rise-­‐fall/load/slew/cell in every process/voltage/temperature corner can have unique variance information – how much that delay can shift in that PVT corner due to local process information. The following information can be added to every cell: • Delay variance (per arc/load/slew/rise/fall/early/late) • Output/Slew variance (per arc/load/slew/rise/fall/early/late) • Flat variance multiplier (per cell) • Constraint variance for registers/latches (per slew/slew/rise/fall) LVF has a delay and output slew variance value (sigma or σ) that models how much each delay or output slew for a given arc can vary due to process variation for every load/input slew combination for every arc in all cells in a library. Rise and fall sigma are modeled separately. The sigma values for timing arcs can have an early and late value. This addresses potential asymmetric distributions (non-­‐Gaussian) and captures unique behavior for when a path has to be slow or fast for set-­‐
up and hold checks (slow data/fast clock or fast data/slow clock). LVF also has a flat multiplier value per cell condition to adjust for other factors such as voltage, temperature or jitter. This enables timing teams to incorporate multiple contributing factors in addition to process variance. LVF also includes variance for the timing constraints – the set-­‐up and hold windows for each flop, latch or register that are used to determine if a path meets timing. LVF can be included in the same file as the delay models, or as a unique file that is separately read in by an EDA tool. This is intended to add flexibility into the library characterization and management process. ©2015 CLK Design Automation, Inc. All rights reserved. The CLK logo, Variance FX, Path FX and Clock FX are trademarks of CLK Design Automation, Inc. All others are properties of their respective holders. 2 How does LVF Work? LVF works just like any other library – except that the timer reads it in to calculate variance instead of delay. When the timer (standalone STA or embedded physical design timer) reports out timing, it uses the LVF data to adjust the delays. Usually, the report will be at some number of sigma from nominal: three sigma or five sigma depending on how conservative a number the end user desires. For example, the data side of path might use three sigma, but the clock side (particularly for hold) might apply five sigma. Warning: The interpretation of the LVF information is up to each tool. This is not specified by the standard. It is possible to get very different answers from different STA tools with the same inputs. You need to have an open conversation with your tool supplier and ask them to explain how their tools interpret LVF. At its most basic level, the delay sigma along each cell in a path can literally be summed up using ‘statistical addition.’ At the end of the path at the flop, latch or register there is a single sigma value for delay. The arrival time of clock and data are corrected for this value before determining slack. Instead of reporting corner delay, the timer will report a nominal delay (at a global corner such as SSG or FFG) plus or minus ‘n’ sigma. Slew sigma is a more complicated. It is necessary to adjust for slew sigma at each gate in a path. Because the output slew from the driver gate changes the delay calculation at the receiver gate, and only nominal delays are propagated, output slew must be corrected for variance before the next stage is evaluated. Constraint uncertainty is the simplest. The set-­‐up and hold windows at each register or flop are adjusted for variance based upon the input slews at the clock and data pins. When the STA tool calculates slack at the end of every path, it will use the variance-­‐adjusted constraints. ©2015 CLK Design Automation, Inc. All rights reserved. The CLK logo, Variance FX, Path FX and Clock FX are trademarks of CLK Design Automation, Inc. All others are properties of their respective holders. 3 What does LVF look like? LVF follows the standard format for all Liberty structures. As noted earlier, LVF is intended to work as a standalone file or fully integrated with the base library itself. However, it is up to each tool to support standalone files. Here is a sample of the LVF structure: /* liberty example */ cell (BUFFER) { pin (OUT) { timing() { ocv_sigma_cell_rise(2D_template) { sigma_type: early; index_1 (“0.1, 0.2, 0.3”); index_2 (“0.4, 0.5, 0.6”); values (“0.1, 0.2, 0.3, \ 0.4, 0.5, 0.6, \ 0.7, 0.8, 0.9”); } } } } Effectively this parallels the basic Liberty structure as would be used for representing CCS, NLDM or any of the other content. What is Required For Putting LVF into Production? There are three key requirements for putting LVF into production: • Tool flow compatibility • LVF tables or an LVF characterization flow • Adjustments to the sign-­‐off methodology Tool flow: Obviously, the first step is to have tools that can read and apply LVF. The two most important are STA and late stage optimization. Fortunately, the two leading STA tools, PrimeTime and Tempus, have both released LVF support. Since most of the late stage optimization flows use sign-­‐off STA results to drive their timing, all of the ingredients are in place for an LVF sign-­‐off flow. ©2015 CLK Design Automation, Inc. All rights reserved. The CLK logo, Variance FX, Path FX and Clock FX are trademarks of CLK Design Automation, Inc. All others are properties of their respective holders. 4 LVF Tables and Characterization: The foundries (TSMC, UMC, Intel, GF, Samsung) have not officially announced LVF support yet, but characterization capability has been released. The leading tool in this area is, of course, Variance FX from CLK Design Automation. Variance FX provides a complete AOCV, POCV, and LVF capability, including delay, slew and constraint uncertainty. Variance FX is in production at the most advanced nodes, with all of the leading foundries. Sign Off Methodology Adjustments: LVF does require changes to the sign-­‐off methodology. Most importantly, LVF works off of global corners (SSG, FFG, TTG), instead of the fixed corners (SS, FF, TT). Foundries do support sign-­‐off at the global corners, but this is done on a company-­‐by-­‐company basis. There are other smaller changes that have to be made, particularly if constraint uncertainty is used. Designers need to avoid ‘double counting’ margin. For example, clock uncertainty and clock skew values should be examined to make sure that they only include the clock related behavior, not the flop constraint behavior. This will now be accounted for in the constraint uncertainty value. There are similar examples where existing flat derates (that often account for multiple factors – process, IR drop, metal…) must be decomposed to exclude components that are addressed by LVF. Summary LVF is a major breakthrough for improving the quality of sign-­‐off timing. By adding highly granular on die variance information for each cell in a library, engineers now have a much more accurate way of incorporating manufacturing variance into their sign-­‐off flows. This will enable design teams to capture much more of the potential of advanced FinFET processes, as well as implementing new power reduction schemes through low voltage operation. ©2015 CLK Design Automation, Inc. All rights reserved. The CLK logo, Variance FX, Path FX and Clock FX are trademarks of CLK Design Automation, Inc. All others are properties of their respective holders. 5