DESIGN AND IMPLEMENTATION OF ARITHMETIC
AND LOGICAL UNIT (ALU) USING XILINX ISE
DESIGN SUITE V14.7
A Project Report
Submitted by
NISHANT SAHAY
180130111052
In partial fulfillment for the award of the degree of
BACHELOR OF ENGINEERING
in
Electronics & Communication Engineering
Government Engineering College, Gandhinagar
Gujarat Technological University, Ahmedabad
April, 2022
First Page
Government Engineering College, Gandhinagar
Gandhinagar - Vijapur Rd, Sector 28 GIDC, Sector 28, Gandhinagar, Gujarat 382028
CERTIFICATE
This is to certify that the project report submitted along with the project entitled
Design and Implementation of Arithmetic and Logical Unit (ALU) using
Xilinx ISE Design Suite v14.7 has been carried out by Nishant Sahay under my
guidance in partial fulfillment for the degree of Bachelor of Engineering in
Electronics and Communication 8th Semester of Gujarat Technological
University, Ahmadabad during the academic year 2021-22.
Sign:
Sign:
Prof. Devendra H. Patel
Dr. Kishor G. Maradia
Internal Guide
Head of the Department
Government Engineering College, Gandhinagar
Gandhinagar - Vijapur Rd, Sector 28 GIDC, Sector 28, Gandhinagar, Gujarat 382028
DECLARATION
We hereby declare that the Internship/Project report submitted along with the
Internship/Project entitled Design and Implementation of Arithmetic and
Logical Unit (ALU) using Xilinx ISE Design Suite v14.7 submitted in partial
fulfillment for the degree of Bachelor of Engineering in Electronics and
Communications to Gujarat Technological University, Ahmedabad, is a
bonafide record of original project work carried out by me at Indicus
Technology, Ahmedabad under the supervision of Prof. Devendra H. Patel
and that no part of this report has been directly copied from any students’ reports
or taken from any other source, without providing due reference.
Name of the Student
Sign of the student
Nishant Sahay
_______________
ACKNOWLEDGEMENT
It gives me immense pleasure to express my heartfelt gratitude and sincere thanks to my faculty
mentor Prof. Devendra H. Patel (Assistant Professor, Electronics and Communication
Engineering) for his timeless and valuable contribution, suggestion and encouragement for the
completion of this project. His continuous guidance had led me to execute my project titled
“DESIGN AND IMPLEMENTATION OF ARITHMETIC AND LOGICAL UNIT (ALU)
USING XILINX ISE DESIGN SUITE V14.7”. I am deeply indebted to my mentor.
I would also like to acknowledge Indicus Technology, Ahmedabad, especially Shri. Vishnu
Vaishnav, under whose guidance I learned to use the software accessible to me in the field of
VLSI during my internship. I am deeply thankful for his continuous support, encouragement,
and suggestions that helped my complete this project successfully.
NISHANT SAHAY (E.No. 180130111052)
i
ABSTRACT
My internship in the given 12-week tenure was in the field of VLSI front end
domain, which involved training in digital fundamentals, Verilog HDL
programming, ISE Design Suite tool, and understanding various methods of
verification. The internship took place at Indicus Technology, Ahmedabad.
The resources that were available to me during my internship helped me develop
my project regarding Arithmetic and Logical Unit. ALU is a fundamental block
of CPU, that is responsible for logical and arithmetical operations over given
binary inputs. The internship involved the use of Xilinx ISE Design tool,
QuestaSim simulation tool, and other EDA tools that were taught in the given
duration of my internship, and I was able to successfully use them for my project
work. This project showcases the process of designing digital system and
understanding the methodology of verifying such systems. Simulation based
testing, self-verification programming, and generic coding are few of the skills
that I have developed during my internship and showcased the same in the given
project.
The internship also involved continuous evaluation, assessments, assignments,
and expert talk to help us understand and be more knowledgeable of the current
trends in the VLSI industry.
ii
List of Figures
Fig 2.1
Block Diagram for 32-bit ALU ...............................................................................8
Fig 2.2
Multiplexer 4:1 Taking 32-bit Input ...................................................................... 13
Fig 2.3
Ripple Carry Adder 32-bit .................................................................................... 13
Fig 2.4
Logical Unit 32-bit ............................................................................................... 15
Fig 2.5 Shift Unit 32-bit.................................................................................................... 15
Fig 2.6
32-bit ALU PERT Chart ....................................................................................... 17
Fig 3.1
ALU System Design ............................................................................................. 19
Fig 3.2
Design Process ..................................................................................................... 21
Fig 3.3
Arithmetic Unit RTL Schematic ........................................................................... 22
Fig 3.4
Logical Unit RTL Schematic ................................................................................ 23
Fig 3.5 Shift Unit RTL Schematic .................................................................................... 23
Fig 3.6
ALU State Transition Diagram ............................................................................. 24
Fig 4.1
ALU Chip Scale ................................................................................................... 35
Fig 4.2
ALU Module Scale ............................................................................................... 36
Fig 4.3
ModelSim Simulation of Test Bench .................................................................... 40
Fig 4.4
ModelSim Simulation for Self-Checking Test Bench ............................................ 46
Fig 4.5 Self-check from Console for Simulation Results ................................................... 46
iii
List of Tables
Table 2.1 Truth Table for 32-bit ALU ............................................................................... 12
Table 2.2 Timeline of Project ........................................................................................... 18
Table 5.1
Continuous Evaluation dates with objective of the week ................................... 49
iv
List of Abbreviations
ALU
Arithmetic and Logical Unit
VLSI
Very Large Scale Integration
ASIC
Application Specific Integrated Circuit
EDA
Electronic Design Automation
ERP
Enterprise Resource Planning
FPGA
Field Programmable Gate Arrays
ASIC
Application Specific Integrated Circuit Design
AMS
Analog Mixed Signal Design
DFT
Design for Test
PCB
Project Circuit Board
VHDL
Very high speed integration circuit Hardware Description Language
HDL
Hardware Description Language
UNIX
UNiplexed Information Computing System
SOC
System On Chip
STA
Static Timing Analysis
UVM
Universal Verification Methodology
RTL
Register Transfer Level
I2C
Inter-Integrated Circuit
SPI
Serial Peripheral Interface
UART
Universal Asynchronous Receiver/Transmitter
ISE
Integrated Synthesis Environment
CPU
Central Processing Unit
GPU
Graphic Processing Unit
FPU
Floating-Point Unit
LSL
Logical Shift Left
LSR
Logical Shift Right
v
ASL
Arithmetic Shift Left
ASR
Arithmetic Shift Right
MUX
Multiplexer
ACM
Association for Computing Machinery
PERT
Program Evaluation Review Technique
vi
Table of Content
ACKNOWLEDGEMENT................................................................................................... i
ABSTRACT ........................................................................................................................ ii
List of Figures .................................................................................................................... iii
List of Tables ..................................................................................................................... iv
List of Abbreviations ...........................................................................................................v
CHAPTER 1: OVERVIEW OF THE COMPANY ........................................................1
1.1 HISTORY ................................................................................................................1
1.2 SCOPE OF WORK ..................................................................................................2
1.3 COMPANY MODULES FOR TRAINING ..............................................................4
CHAPTER 2: INTRODUCTION TO PROJECT ..........................................................7
2.1 PROJECT SUMMARY ............................................................................................7
2.2 PURPOSE OF THIS PROJECT ...............................................................................8
2.3 SCOPE .....................................................................................................................9
2.4 TECHNOLOGY AND LITERATURE REVIEW ................................................... 10
2.5 PROJECT PLANNING .......................................................................................... 12
2.6 PROJECT SCHEDULING ..................................................................................... 17
CHAPTER 3: SYSTEM DESIGN ................................................................................. 19
3.1 SYSTEM DESIGN AND METHODOLOGY ........................................................ 20
3.2 RTL SCHEMATIC ................................................................................................ 22
3.3 STATE TRANSITION DAIGRAM........................................................................ 24
CHAPTER 4: IMPLEMENTATION ........................................................................... 25
4.1 SOURCE CODE FOR RTL DESIGN..................................................................... 25
4.2 SOURCE CODE FOR SIMULATION TEST BENCH ........................................... 36
4.3 SOURCE CODE FOR SELF-CHECKING TEST BENCH..................................... 41
CHAPTER 5: CONCLUSION AND DISCUSSION .................................................... 47
5.1 LIMITATION AND FUTURE ENHANCEMENT ................................................. 48
5.2 CONTINUOUS EVALUATION ............................................................................ 49
REFERENCES .................................................................................................................. 52
APPENDIX ........................................................................................................................ 54
vii
Team ID: 220312
Overview of the Company
CHAPTER 1: OVERVIEW OF THE COMPANY
Indicus Technology provides professional training courses in VLSI front-end domain. Their
aim is to train young engineers in Advance VLSI Design and Verification domain and make
them industrial ready. They have highly skilled and experienced trainer, who help their trainees
to attain guaranteed success by offering outstanding training, motivation and support.
1.1 HISTORY
Indicus Technology is an Ahmedabad based VLSI Training Institute established in August
2015. The founder of the company is Shri. Vishnu Vaishnav, who’s a bachelorette in
Electronics and Communication Engineering and has had over 11 years of experience in VLSI
domain. They started their company by offering a partnership in the sphere of software
development and outsourcing. Software outsourcing means that some of the non-core software
projects from companies in foreign countries are delivered to other companies which have low
costs of human resources, so that they can reduce the costs of software development. The
company offered services in web design and development, E-commerce website, digital
marketing, web hosting, ERP solutions, mobile app development, and graphics design.
The company later added a training program in the field of front-end VLSI domain. Interested
candidates were asked to give an entrance test and an interview, based on which they were
selected for the program. The training course would usually last for 5-6 months, based on the
trainee’s capability. They provide fully technical & practical training programs and hands on
experience with modern EDA tools and methods, to meet the requirement of extensively
growing VLSI Industries. The training involved the following courses:
1. Advance ASIC Verification.
2. Advance Design and Verification.
Gujarat Technological University
1
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Overview of the Company
1.2 SCOPE OF WORK
The world of technology as we know is highly depended on powerful, complex, and small
integrated chips. VLSI stands for Very Large Scale Integration which involves designing and
connecting millions and billions of transistors in an integrated chip. Future scope of such
domain is very high as the world is full of electronic devices which consists of
microcontrollers, microprocessors, etc. To design and integrate these chips VLSI engineers are
required. The digital world is filled with “smart” electronic devices like smartphones, smart
TV, laptops, computers, home automation gadgets, etc. Some of the different fields where
VLSI engineer can work are given as follows:
1.2.1 Application VLSI Engineer
This job is for those who are good at interacting with customers and those who want to
work in R&D. In this job, engineers must travel a lot and should take the requirements
of customers based on application. This job requires good communication skills,
interaction skills with people, and understanding customer requirements. The field also
consists of subdomains such as application engineer for field and application engineer
for corporate.
1.2.2 VLSI Chip Design Engineer
In this field, the engineer will design chips by using tools. The field consists of various
subdomains such as FPGA (Field Programmable Gate Arrays), ASIC (Application
Specific Integrated Circuit Design), AMS (Analog Mixed Signal Design), DFT (Design
for Test), PCB (Board Design).
Gujarat Technological University
2
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Overview of the Company
1.2.3 VLSI Engineer for Verification
The work of the verification engineer is to verify the chips once the design is completed.
The verification engineers must check whether the chip is working properly or not.
Knowledge of programming languages such as Verilog or VHDL. The subdomains of
verification engineers are product validation, hardware-software co-verification, frontend verification, etc.
1.2.4 Engineers for CAD
This job is suitable for those who like to manage tools. The job of engineers is to
manage EDA tools. Engineers should also know which tool is used for each process.
1.2.5 VLSI Engineers for Sales
The engineers for sales and marketing are responsible to sell the chips at the market.
Good interaction skills with people, communication skills, sales and marketing skills
are required for this job.
Gujarat Technological University
3
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Overview of the Company
1.3 COMPANY MODULES FOR TRAINING
The VLSI training consists of 12 modules that are covered over a span of 6 months. These
modules are given as below:
1.3.1 Introduction to VLSI
Discussion regarding Design flow in VLSI. Various domains of VLSI. Future scope
of VLSI. Opportunities in VLSI.
1.3.2 Digital Electronics
Various numbering systems in digital electronics and their conversions. Use of
logic gates, minimization of logic gates. Discussion on combinational circuit,
sequential circuit, finite state machine. Various types of memories.
1.3.3 UNIX Basics
Handling directory Operation from Command Prompt. Handling files Operation
from Command Prompt Handling File Editor Application (vi, vim, gvim).
1.3.4 Verilog HDL
Verilog Data Types & Operators. Verilog Assignment & construct. Verilog System
Task. Combinational & Sequential design. Synchronous & Asynchronous design.
Task & Function. Self-Checking test bench. Code Coverage.
Gujarat Technological University
4
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Overview of the Company
1.3.5 FPGA, ASIC, SOC basics
What is FPGA? What is ASIC? What is SOC? Comparison Between FPGA, ASIC,
SOC.
1.3.6 STA Basics
Delay calculation in circuit, maximum operating frequency calculation, skew and
jitter clock domain and variation clock network distribution.
1.3.7 System Verilog
System Verilog Data types. Arrays in SV. Task & Function in SV. Interface OOPS
& Advance OOPs. Concept Randomization. Threads, Mailbox, Semaphore, Events.
System Verilog TB Environment. Function Coverage.
1.3.8 System Verilog Assertion
Immediate assertion. Simple assertion. Sequence composition, ABV assertion
coverage,
1.3.9 UVM Methodology
UVM Factory, UVM phases, UVM Reporting Mechanism, TLM, UVM Sequence,
Virtual Sequence & Virtual Sequencer, UVM TB Environments, UVM Callbacks.
1.3.10 Python Script
Variable Types, Operators, number, string and list. If else and loops tuple and
dictionary, function, file I/O Operation.
Gujarat Technological University
5
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Overview of the Company
1.3.11 Mini Project
Verilog based mini project. System Verilog based mini project. UVM based mini
project.
1.3.12 Industrial Standard Project
Specification, Design Architecture, RTL Design using Verilog HDL, RTL
Verification using system Verilog/UVM, AXI4/ AXI3/ AHB/ APB/ ASB/ Bridge
SPI/ I2C/ UART.
Gujarat Technological University
6
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Introduction to Project
CHAPTER 2: INTRODUCTION TO PROJECT
The following is a 32-bit Arithmetic and Logical Unit project programmed using Xilinx ISE
Design Suite Tool. This project was programmed in Verilog HDL language. The program was
later synthesized and verified using Xilinx ISE Design Tool and ModelSim tool.
2.1 PROJECT SUMMARY
The Arithmetic Logic Unit (ALU) is a fundamental building block of the Central Processing
Unit (CPU) of a computer. We can say that ALU is a core component of all central processing
unit within in a computer and is an integral part of the execution unit. ALU is capable of
calculating the results of a wide variety of basic arithmetical and logical computations. The
ALU takes as input the data to be operated on (called operands) and a code from the control
unit indicating which operation to perform. The output is the result of the computation (Maaz
et al., 2016).
The ALU implemented in this project will perform the following operations:

Arithmetic operations (addition, subtraction, increment, decrement, transfer)

Logic operations (AND, NOT, OR, EX-OR)

Shift operations (LSR, LSL, ASL, ASR)
This 32-bit ALU consists of an arithmetic unit, a logic unit, a shift unit, clock gating unit and
an output multiplexer (Fig 2.1). Here the 32-bit ALU is implemented by using the behavioral
modelling style to describe how the operation of ALU is being processed. This is accomplished
by using a hardware description language VHDL.
Gujarat Technological University
7
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Introduction to Project
Fig 2.1
Block Diagram for 32-bit ALU
2.2 PURPOSE OF THIS PROJECT
The purpose of the following project is to demonstrate the functioning of a simple 32-bit ALU.
The use of Xilinx Design Tool simulates the process of designing, synthesizing, and verifying
a digital electronic circuit. The 32-bit ALU is designed in this project to simplify the
understanding of the operation a general ALU. The ALUs used in general VLSI industry are
comparatively much more complex, fast, and sophisticated. However, the core functionality,
building blocks, and planning for design remains the same.
The ALU is one of the most important components of a CPU. It is responsible for arithmetic
and logical operation. The ALU designed here is limited to 7 arithmetic operations, 4 logical
operations, and 4 shifting operations. The arithmetic operations demonstrated involves
addition, addition with carry, subtraction, subtraction with borrow, transfer, increment, and
decrement. The logical operations demonstrated involves logical AND operation, logical OR
operation, logical XOR operation and logical NOT operation. The shift operations that are
demonstrated here involves logical right shift, logical left shift, arithmetic right shift, arithmetic
left shift. (Nayak, 2018)
Gujarat Technological University
8
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Introduction to Project
2.3 SCOPE
The ALU in modern general purpose processors is much more powerful, complex, and
sophisticated. The arithmetic and logical operation demonstrated here are a fraction of
operations that a modern ALU can perform. Moreover, modern ALUs are designed to work
with more than one ALU, thus making their operation even more sophisticated.
There are many other arithmetic operations, such as multiplication and division, that are not
covered in this project, due to their complex design. Many logical operations such as NAND,
NOR, EX-NOR, etc. are also not covered in this project. Other than this there are various other
shift operations, and many more arithmetic operations that a modern ALU is capable.
Furthermore, the ALU in this project is 32-bit wide, meaning it can take operands of length up
to 32-bit. Modern ALUs can work at much bigger lengths such as 62-bit or even 128-bit.
That said the general functionality of an ALU as described in this project reflects the actual
operational stages in an ALU. Every ALU consists of various operational units, which
generally involves an arithmetic unit, logical unit and shift unit. Each of these units are
controlled and selected based on a set of control signals. The control unit is responsible to
generate these control signals based on the program to be executed.
The addition and subtraction operations in this project are synthesizable in the form of a ripple
full adder. This is a very common sequential circuit that has not only seen its use in ALUs but
also in other complex sequential circuits. The ALU gets its input from an input register, at this
stage the bit stream over which the operation is to take place is referred an operand. The result
generated by an ALU is stored in an output register.
Gujarat Technological University
9
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Introduction to Project
2.4 TECHNOLOGY AND LITERATURE REVIEW
The ALU stands for Arithmetic and Logical Unit. It is an integrated circuit in CPU or GPU,
that performs arithmetic and logic operations. Arithmetic instructions include addition,
subtraction, and shifting operations, while logic instructions include Boolean comparisons,
such as AND, OR, XOR, and NOT operations. (techterms.com, 2011)
ALUs are designed to perform integer calculations. Therefore, besides adding and subtracting
numbers, ALUs often handle the multiplication of two integers, since the result is also an
integer. However, ALUs typically do not perform division operations, since the result may be
a fraction, or a "floating point" number. Instead, division operations are usually handled by the
floating-point unit (FPU), which also performs other non-integer calculations. (study.com,
2015)
While the ALU is a fundamental component of all processors, the design and function of an
ALU may vary between different processor models. For example, some ALUs only perform
integer calculations, while others are designed to handle floating point operations as well.
Some processors contain a single ALU, while others include several arithmetic logic units that
work together to perform calculations. Regardless of the way an ALU is designed, its primary
job is to handle integer operations. Therefore, a computer's integer performance is tied directly
to the processing speed of the ALU.
ALU research is an important part of computer science, classified under Arithmetic and logic
structures in the Association for Computing Machinery (ACM) Classification System. Nayak
(2018) has designed the ALU by using VHDL. This is a hardware description language used
in electronic design to describe digital and mixed-signal systems such as field-programmable
gate arrays and integrated circuits. Mixed Modeling Style is used while designing the ALU.
Xilinx ISE (Integrated Software Environment) is a software tool produced by Xilinx for
synthesis and analysis of HDL designs, enabling the developer to synthesize their designs,
Gujarat Technological University
10
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Introduction to Project
perform timing analysis, examine RTL diagrams, simulate a design's reaction to different
stimuli, and configure the target device with the programmer.
The ALU is realized using parallel implementation of functional units that perform individual
functions such as addition, subtraction etc. Operands are fed to the unit corresponding to the
operation to be performed and result is generated by that unit and given to the output lines of
the ALU. The select lines determine the operation to be performed. While designing the ALU
a modular design is followed, that consist of smaller, more manageable blocks, some of which
can be re-used. One-bit ADDER–SUBTRACTOR, OR, AND, NOT, XOR, LEFT SHIFT,
RIGHT SHIFT UNIT are designed. These bit-slices can then be connected to make a 32-bit
ALU. Block diagram of ALU is shown in Fig 2.1. (Suchita and Mhala., 2012; Kaliamurthy
Sownmiya, 2012)
It accomplishes arithmetic operations such as increment, decrement, add and sub. Logical
operations are NOT, AND, XOR and OR. Shift operations are logical shift left and right. Table
2.1 shows various operations performed by proposed ALU design. These various operations
are executed using a set of functional blocks, each implementing a function, these may also be
done using sharing of same hardware with use of certain additional units like multiplexers. The
ALU has 3 set of input signals and one output signal. Operands A and B are both 32 bits each.
These are given to these functional units along with select lines which will decide the operation
to be performed. Each combination of the select lines corresponds to one particular function
(Navabi, 2007; Esther et al., 2011)
Gujarat Technological University
11
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Introduction to Project
Table 2.1
S3
0
0
0
0
0
0
0
0
0
0
0
0
1
1
S2
0
0
0
0
0
0
0
0
1
1
1
1
0
0
S1
0
0
0
0
1
1
1
1
0
0
1
1
0
1
S0
0
0
1
1
0
0
1
1
0
1
0
1
X
X
Truth Table for 32-bit ALU
Cin
0
1
0
1
0
1
0
1
X
X
X
X
X
X
Result
A+B
A+B+1
A–B
A–B–1
A–1
A
A
A+1
A·B
A+B
A⊕B
~A
A>>2
A<<2
Operation
Addition
Addition with carry
Subtraction
Subtraction with borrow
Decrement
Transfer
Transfer
Increment
AND
OR
XOR
Compliment
Shift Right
Shift Left
2.5 PROJECT PLANNING
The approach used here is to split the ALU into three modules, Arithmetic, Logic and Shift
module. The arithmetic, logic and shifter units introduced earlier can be combined into ALU
with common selection lines. The shift micro-operations are often performed in a separate unit,
but sometimes the shifter unit made part of overall ALU. For 32-bit ALU, a 33 bit 4:1 MUX
is needed (Fig 2.2). A particular arithmetic or logic or shift operation is selected according to
the selection inputs S0 and S1. The final output of the ALU is determined by the set of
multiplexers with selection lines S2 and S3. The function table for the ALU is shown in the
Table 2.1. The Table 2.1 lists 14 micro-operations: 8 for arithmetic, 4 for logic and 2 for shifter
unit. For shifter unit, the selection line S1 is used to select either left or right shift operation.
Gujarat Technological University
12
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Introduction to Project
Fig 2.2
Multiplexer 4:1 Taking 32-bit Input
An Arithmetic unit does the following task: Addition, Addition with carry, Subtraction,
Subtraction with borrow, Decrement, Increment and Transfer function. Now first of all we start
with making one-bit Full Adder, then a 4-bit Ripple Carry Adder using four numbers of Full
Adder and at last a 32-bit Ripple Carry Adder using eight numbers of 4-bit Ripple Carry Adder
as shown in Fig 2.3. (Divya et al., 2020)
Fig 2.3
Ripple Carry Adder 32-bit
Then we have designed Thirty-two numbers of single-bit 4:1 multiplexer have been designed
as shown in Fig 2.2. The circuit has a 32-bit parallel adder and thirty-two multiplexers for 32bit arithmetic unit. There are two 32-bit inputs A and B and 33-bit output is result. The size of
each multiplexer is 4:1. The two common selection lines for all thirty-two multiplexers are S0
and S1. (Nayak, 2018)
Gujarat Technological University
13
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Introduction to Project
A Logic unit does the following task: Logical AND, Logical OR, Logical NOT and Logical
EX-OR operation. A logic unit has been designed that can perform the four basic logic microoperations: OR, AND, EX-OR and Complement, because from these four micro-operations,
all other logic micro operations can be derived. The logic unit consists of four gates and a 4:1
multiplexer. The outputs of the gates are applied to the data inputs of the multiplexer. Using to
selection lines S0 and S1 one of the data inputs of the multiplexer is selected as the output. For
a logic unit of 32-bit, the output will be of 33-bit with 33rd bit to be High-impedance. The
common selection lines are applied to all the stages. The unit is shown in Figure 2.4.
Shift unit is used to perform logical shift micro-operation. The shifting of bits of a register can
be in either direction-left or right. The content of a register that has to be shifted first placed
onto common bus. This circuit uses no clock pulse. When the shifting unit is activated the
register is shifted left or right according to the selection unit as shown in Fig 2.5 (Chandrakasan
and Brodersen, 1995; Srivastava et al., 2009).
Gujarat Technological University
14
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Introduction to Project
Fig 2.4
Fig 2.5
Gujarat Technological University
Logical Unit 32-bit
Shift Unit 32-bit
15
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Introduction to Project
Synthesis and performance analysis of these designs are done using Xilinx ISE tool. Each
operational unit is first designed separately and then implemented using the tool. Later, a test
bench for that unit is written to test and verify the respective outputs. The simulation waves
are obtained from ModelSim, which is a part of the Xilinx Tool. The approach towards
verification is to give a random sequence of input and operate over it thorough via blocks. The
select lines control which block will operate over the input and the output is observed in
“result” register.
Two different forms of test benches are made. First one is a simulation based test bench. The
inputs given are operated on, and the resulting waveforms are generated and then observed for
verification. However, this ALU consists of 14 operations, with both input and output being
32-bit long. Such type of verification is thus time consuming and can lead to human error.
Thus, a second type of approach is also demonstrated.
The second approach is a concept in verification which referred as self-checking code. The test
bench written here consists a section in program that replicates the behavior of the specification
of the design. For example, the approach by the designer for addition of two 32-bit values is to
synthesize a 32-bit ripple adder. However, fundamentally the operation of addition can be
stated as “A + B” where A and B are the inputs (or in this case operands). Thus, the test bench
written will consists a “task” that adds to given inputs and stores the result in a separate
variable. This variable is then matched with the output of the ALU. If the results are the same
then the test is considered to pass and the design is said to be working properly, if the result
fails then the designed had to be debugged. The self-checking approach is a lot faster than the
simulation approach, it is also “human” error free, and can also be modified to display only
those parts of program that have failed.
Gujarat Technological University
16
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Introduction to Project
2.6 PROJECT SCHEDULING
The Fig 2.6 is a PERT chart for 32-bit ALU. The process started with searching for Research
papers regarding 32-bit ALU. The papers were studied and later the arithmetic, logical, and
shift unit were designed and implemented separately. Each of these units were then tested,
and finally after verification all blocks were connected together and finally verified for the
same.
Fig 2.6
32-bit ALU PERT Chart
The table 2.2 summarizes the timeline of the project.
Gujarat Technological University
17
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Introduction to Project
Table 2.2 Timeline of Project
Date
Objective
Time taken
14-03-2022

Project decision and planning
2 days
17-03-2022

Research Papers
3 days

Browsing for ideas

Design implementation.

Separate design planning for each unit

Test Bench for each block

Simulation for each block

Verification of each block

RTL synthesis of all blocks in a single
22-03-2022
29-03-2022
04-04-2022
4 days
4 days
2 days
program

Schematic Review as per initial design
07-04-2022

Test bench (simulation based) for final RTL
2 days
09-04-2022

Test bench, self-checking based for final RTL
2 days
TOTAL DAYS
Gujarat Technological University
19 DAYS
18
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
System Design
CHAPTER 3: SYSTEM DESIGN
The 32-bit ALU as demonstrated is divided into 3 design units. Arithmetic unit, which is
responsible for seven arithmetic operations which include addition, addition with carry,
subtraction, subtraction with borrow, increment, decrement, and transfer. The logical unit,
which consists of four logical operations that include AND, OR, EXOR, and NOT. And finally,
the shift unit which is responsible for 2 types of shift, arithmetic and logical shift, each in left
and right direction. The flow of design is shown in Fig 3.1.
ARITHMETIC RTL DESIGN
ARITHMETIC TEST BENCH
LOGICAL RTL DEISGN
LOGICAL TEST BENCH
SHIFT RTL DESIGN
SHIFT TEST BENCH
SINGLE MODULE ALU WITH
SIMULATION AND SELF
CHECKING VERIFICATION
Fig 3.1
Gujarat Technological University
ALU System Design
19
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
System Design
3.1 SYSTEM DESIGN AND METHODOLOGY
The designing of each unit is done in Verilog HDL. First, the modules required to do an
operation regarding that particular unit are written, each of these modules are then port
instantiated to the “unit” module. This module uses “switch…case” to select one of the
operational modules based on the control signal. One such example is given below for
Arithmetic Unit module:
//MODULE ADDITION
module add(
input [WIDTH-1:0] a,b,
output [WIDTH-1:0] f);
assign f = a + b;
endmodule
The above mentioned module performs an addition operation on two given inputs. This
module will be selected when the select line inputs for “arithmetic unit” will be “000”. This
selection can be seen via the “switch…case” section of arithmetic module:
always @ (*) begin
case(sel)
3'b000 : f <= w1;
3'b001 : f <= w2;
3'b010 : f <= w3;
3'b011 : f <= w4;
3'b100 : f <= w5;
3'b101 : f <= w6;
3'b110 : f <= w7;
default : f <= 0;
endcase
end
Gujarat Technological University
20
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
System Design
“w1” is a wire type variable that holds the result of addition. As we can see it is selected
when select line inputs are “000”. This same methodology of design is implemented in
logical and shift unit as well. Each program consists of separate modules for unit specific
operations which are selected by the “main” module based on the control signals. The select
lines for the MUX acts as the control signals for the module.
The diagram below shows a very simplified view of the electronic system design process
incorporating Verilog. The central portion of the diagram shows the parts of the design process
which will be impacted by Verilog.
Fig 3.2
Gujarat Technological University
Design Process
21
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
System Design
3.2 RTL SCHEMATIC
Once the program is written, Xilinx ISE tool is used to synthesize the given design. The
following are the RTL schematics for each unit. RTL stands for Register Transfer Language.
It shows the implementation logic of the circuit that demonstrates how data flows in and out
from the circuit.
Fig 3.3
Gujarat Technological University
Arithmetic Unit RTL Schematic
22
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
System Design
Fig 3.4
Fig 3.5
Gujarat Technological University
Logical Unit RTL Schematic
Shift Unit RTL Schematic
23
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
System Design
3.3 STATE TRANSITION DAIGRAM
ALU
S (3:4) control signal
LOGICAL UNIT
ARITHMETIC UNIT
SHIFT UNIT
S (0:1)
S (0:2)
S (0:1)
ADD
ADD WITH
CARRY
AND
OR
LOGICAL
RIGHT
SUBTRACT
SUBTACT
WITH BORROW
XOR
NOT
ARITHMETIC
RIGHT
INCREMENT
DECREMENT
TRANFER
TRANFER
Fig 3.6
Gujarat Technological University
LOGICAL
LEFT
ARITHMETIC
LEFT
ALU State Transition Diagram
24
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Implementation
CHAPTER 4: IMPLEMENTATION
The following project is implemented using Xilinx ISE Design Suite tool v14.7. The Verilog
HDL code was written in gvim text editor. The RTL design was then synthesized, and observed
as per specification. The test bench written was used to simulate the behavior of the design.
The simulation waveforms were observed and verified. The self-checking test bench was later
used to better assess the simulation.
4.1 SOURCE CODE FOR RTL DESIGN
`define WIDTH 32
//ARITHMETIC AND LOGICAL UNIT
//MODULE ADDITION
module add(
input [`WIDTH - 1:0] a,b,
output [`WIDTH - 1:0] f);
//addition operation
assign f = a + b;
endmodule
//MODULE ADDITION WITH CARRY
module add_with_carry(
input [`WIDTH - 1:0] a,b,
output [`WIDTH - 1:0] f);
Gujarat Technological University
25
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Implementation
//addtion operation with carry
assign f = a + b + 1;
endmodule
//MODULE SUBTRACTION
module subtract(
input [`WIDTH - 1:0] a,b,
output [`WIDTH - 1:0] f);
//subtraction operation
assign f = a + ~b;
endmodule
//MODULE SUBTRACTION WITH BORROW
module sub_with_borrow(
input [`WIDTH - 1:0] a,b,
output [`WIDTH - 1:0] f);
//subtracition operation with borrow
assign f = a + ~b + 1;
endmodule
//MODULE INCREMENTATION
module increment(
input [`WIDTH - 1:0] a,
output [`WIDTH - 1:0] f);
Gujarat Technological University
26
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Implementation
//increment operation
assign f = a + 1;
endmodule
//MODULE DECREMENTATION
module decrement(
input [`WIDTH - 1:0] a,
output [`WIDTH - 1:0] f);
//decrement operation
assign f = a - 1;
endmodule
//MODULE TRANSFER
module transfer(
input [`WIDTH - 1:0] a,
output [`WIDTH - 1:0] f);
//tranfer operation
assign f = a;
endmodule
//MODULE ARITHMETIC UNIT
module arithmetic_unit(
input
[`WIDTH - 1:0] a,b,
input
[2:0]
sel,
Gujarat Technological University
27
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Implementation
output reg [`WIDTH - 1:0] f);
wire
[`WIDTH - 1:0] w1,w2,w3,w4,w5,w6,w7;
//module port instantiation
add
A1(a,b,w1);
add_with_carry A2(a,b,w2);
subtract
A3(a,b,w3);
sub_with_borrow A4(a,b,w4);
increment
A5(a,w5);
decrement
A6(a,w6);
transfer
A7(a,w7);
//output selection based on control signal
always @ (*) begin
case(sel)
3'b000 : f <= w1;
3'b001 : f <= w2;
3'b010 : f <= w3;
3'b011 : f <= w4;
3'b100 : f <= w5;
3'b101 : f <= w6;
3'b110 : f <= w7;
default : f <= 0;
endcase
Gujarat Technological University
28
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Implementation
end
endmodule
////////////////////LOGIC UNIT////////////////////////////////
//AND MODULE
module and_4(
input [`WIDTH - 1:0] a,b,
output [`WIDTH - 1:0] f);
//lgical AND operation
assign f = a & b;
endmodule
//OR MODULE
module or_4(
input [`WIDTH - 1:0] a,b,
output [`WIDTH - 1:0] f);
//logical OR operation
assign f = a | b;
endmodule
//XOR MODULE
module xor_4(
Gujarat Technological University
29
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Implementation
input [`WIDTH - 1:0] a,b,
output [`WIDTH - 1:0] f);
//logical XOR operation
assign f = a ^ b;
endmodule
//NOT MODULE
module not_4(
input [`WIDTH - 1:0] a,
output [`WIDTH - 1:0] f);
//logical NOT operation
assign f = ~a;
endmodule
//LOGIC UNIT MODULE
module logic_unit(
input
[`WIDTH - 1:0] a,b,
input
[1:0]
sel,
output reg [`WIDTH - 1:0] f);
wire
[`WIDTH - 1:0] w1,w2,w3,w4;
//module port instantiation
and_4 A1 (a,b,w1);
or_4 O1 (a,b,w2);
xor_4 X1 (a,b,w3);
Gujarat Technological University
30
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Implementation
not_4 N1 (a,w4);
//output selection based on control signal
always @ (*) begin
case (sel)
2'b00 : f <= w1;
2'b01 : f <= w2;
2'b10 : f <= w3;
2'b11 : f <= w4;
default : f <= 0;
endcase
end
endmodule
////////////////////SHIFT UNIT////////////////////////////////
//MODULE LEFT SHIFT
module left_shift(
input [`WIDTH - 1:0] a,
output [`WIDTH - 1:0] f);
//left shift operation
assign f = a<<2;
endmodule
//MODULE RIGHT SHIFT
Gujarat Technological University
31
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Implementation
module right_shift(
input [`WIDTH - 1:0] a,
output [`WIDTH - 1:0] f);
//right shift operation
assign f = a>>2;
endmodule
//MODULE LEFT ARITHMETIC SHIFT
module left_arth_shift(
input [`WIDTH - 1:0] a,
output [`WIDTH - 1:0] f);
//arithmetic left shift operation
assign f = a<<<2;
endmodule
//MODULE RIGHT ARITHMETIC SHIFT
module right_arth_shift(
input [`WIDTH - 1:0] a,
output [`WIDTH - 1:0] f);
//arithemtic right shift operation
assign f = a>>>2;
endmodule
//MODULE SHIFT UNIT
module shift_unit(
Gujarat Technological University
32
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Implementation
input
[`WIDTH - 1:0] a,
input
[1:0]
sel,
output reg [`WIDTH - 1:0] f);
wire
[`WIDTH - 1:0] w1,w2,w3,w4;
//module port instantiation
left_shift
right_shift
L1(a,w1);
R1(a,w2);
left_arth_shift L2(a,w3);
right_arth_shift R2(a,w4);
//output selection based on control signal
always @ (*) begin
case(sel)
2'b00 : f <= w1;
2'b01 : f <= w2;
2'b10 : f <= w3;
2'b11 : f <= w4;
endcase
end
endmodule
Gujarat Technological University
33
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Implementation
////////////////////ARITHMETIC & LOGICAL UNIT////////////////////////////////
module ALU(
input
[`WIDTH - 1:0] a,b,
input
[4:0]
sel,
output reg [`WIDTH - 1:0] f);
wire
[`WIDTH - 1:0] w1,w2,w3;
//module port instantion
arithmetic_unit A1(a,b,{sel[0],sel[1],sel[2]},w1);
logic_unit
A2(a,b,{sel[0],sel[1]},w2);
shift_unit
A3(a,{sel[0],sel[1]},w3);
//output selection based on control signal
always @ (*) begin
case({sel[3],sel[4]})
2'b00 : f <= w1;
2'b01 : f <= w2;
2'b10 : f <= w3;
default : f <= 0;
endcase
end
endmodule
Gujarat Technological University
34
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Implementation
4.1.1 RTL SCHEMTIC OBESERVED FOR THE SAME
Fig 4.1
Gujarat Technological University
ALU Chip Scale
35
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Implementation
Fig 4.2
ALU Module Scale
4.2 SOURCE CODE FOR SIMULATION TEST BENCH
`define WIDTH 32
//ALU TESTBENCH
module ALU_4bit_tb();
//input signals
reg [`WIDTH-1:0] a,b;
reg [4:0]
sel;
//output signals
wire [`WIDTH-1:0] f;
Gujarat Technological University
36
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Implementation
//output for indivual units
reg [`WIDTH-1:0]
a_au;
reg [`WIDTH-1:0]
b_au;
reg [`WIDTH-1:0]
a_lu;
reg [`WIDTH-1:0]
b_lu;
reg [`WIDTH-1:0]
a_su;
//port instatiation for DUT
ALU DUT (.a(a),
.b(b),
.sel(sel),
.f(f));
///////////////SIMULATION RUN/////////////////////
initial begin
arithmetic_unit();
//ARITHMETIC UNIT SIMULATED
assign a_au = a;
assign b_au = b;
arithmetic_unit_tb();
#20;
logic_unit();
//LOGICAL UNIT SIMULATED
assign a_lu = a;
assign b_lu = b;
logial_and_shift_unit_tb();
#20;
shift_unit();
Gujarat Technological University
37
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Implementation
//SHIFT UNIT SIMULATED
assign a_su = a;
logial_and_shift_unit_tb();
#20 $finish;
end
//////////////ARITHMETIC UNIT ASSIGNMENTS//////////////
task arithmetic_unit;
begin
//set control signals
sel[3] = 1'b0;
sel[4] = 1'b0;
//random input values given
a = $random;
b = $random;
#10;
end
endtask
//////////////LOGIC UNIT ASSIGNMENTS////////////////
task logic_unit;
begin
//set control signals
sel[3] = 1'b0;
sel[4] = 1'b1;
//random input values given
Gujarat Technological University
38
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Implementation
a = $random;
b = $random;
#10;
end
endtask
//////////////SHIFT UNIT ASSIGNMENTS////////////////
task shift_unit;
begin
//set control signals
sel[3] = 1'b1;
sel[4] = 1'b0;
//random input values given
a = $random;
#10;
end
endtask
/////////////ARITHMETIC UNIT OPERATIONS/////////////
task arithmetic_unit_tb;
begin
//set control signals
{sel[2],sel[1],sel[0]} = 3'b000;
//cycle thorugh all input lines
repeat(8) begin
{sel[2],sel[1],sel[0]} = {sel[2],sel[1],sel[0]} + 3'b001;
#5;
Gujarat Technological University
39
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Implementation
end
end
endtask
//////////LOGICAL AND SHIFT UNIT OPERATIONS/////////
task logial_and_shift_unit_tb;
begin
//set control signals
{sel[2],sel[1]} = 2'b00;
//cycle though all input lines
repeat(4) begin
{sel[2],sel[1]} = {sel[2],sel[1]} + 2'b01;
#5;
end
end
endtask
endmodule
4.2.1 SIMULATION RESULTS
Fig 4.3
ModelSim Simulation of Test Bench
Gujarat Technological University
40
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Implementation
4.3 SOURCE CODE FOR SELF-CHECKING TEST BENCH
`define WIDTH 32
//ALU self-checking test bench
module ALU_tb();
//port direction
reg [`WIDTH - 1 : 0] a,b;
reg [4 : 0] sel;
wire [`WIDTH - 1 : 0] f;
//DUT port intantiation
ALU DUT (.a(a),
.b(b),
.sel(sel),
.f(f));
//refernece model
reg [`WIDTH - 1 : 0] f_exp;
integer i_a, i_s, i_l;
//simulation run
initial begin
arithmetic_check({$random},{$random});
logical_check({$random},{$random});
shift_check({$random});
#5 $finish;
end
//task for arithmetic checks
Gujarat Technological University
41
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Implementation
task arithmetic_check (input [`WIDTH - 1 : 0] A_a, input [`WIDTH - 1 : 0] B_a);
begin
a = A_a;
b = B_a;
sel[3] = 1'b0;
sel[4] = 1'b0;
//loop thorugh control signals
for (i_a=0; i_a<8; i_a=i_a+1) begin
//set control signals
{sel[0],sel[1],sel[2]} = i_a;
f_exp = arithmetic_ref({sel[0],sel[1],sel[2]},A_a,B_a);
#1;
if (f_exp == f)
$display("SUCCESS ; ALU output : %d , Reference output : %d, at %t",f,f_exp,$time);
else
$display("FAIL ; ALU output : %d , Reference output : %d, at %t",f,f_exp,$time);
#5;
end//for end
end//begin end
endtask
//function to run arithmetic operations
function [`WIDTH-1:0] arithmetic_ref (input [2:0] a_ref, input [`WIDTH - 1 : 0] A_ra, input
[`WIDTH - 1 : 0] B_ra);
begin
case(a_ref)
3'b000 : arithmetic_ref = A_ra + B_ra;
3'b001 : arithmetic_ref = A_ra + B_ra + 1;
Gujarat Technological University
42
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Implementation
3'b010 : arithmetic_ref = A_ra + ~B_ra;
3'b011 : arithmetic_ref = A_ra + ~B_ra + 1;
3'b100 : arithmetic_ref = A_ra + 1;
3'b101 : arithmetic_ref = A_ra - 1;
3'b110 : arithmetic_ref = A_ra;
default : arithmetic_ref = `WIDTH'd0;
endcase
end
endfunction
//task for logical check
task logical_check (input [`WIDTH - 1 : 0] A_l, input [`WIDTH - 1 : 0] B_l);
begin
a = A_l;
b = B_l;
sel[3] = 1'b0;
sel[4] = 1'b1;
//loop thorugh control signals
for (i_l=0; i_l<4; i_l=i_l+1) begin
//set control signals
{sel[0],sel[1]} = i_l;
f_exp = logical_ref({sel[0],sel[1]},A_l,B_l);
#1;
if (f_exp == f)
$display("SUCCESS ; ALU output : %d , Reference output : %d, at %t",f,f_exp,$time);
else
Gujarat Technological University
43
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Implementation
$display("FAIL ; ALU output : %d , Reference output : %d, at $t",f,f_exp,$time);
#5;
end//for end
end//begin end
endtask
//function to run logical operation
function [`WIDTH-1:0] logical_ref (input [1:0] l_ref, input [`WIDTH - 1 : 0] A_rl, input
[`WIDTH - 1 : 0] B_rl);
begin
case(l_ref)
2'b00 : logical_ref = A_rl & B_rl;
2'b01 : logical_ref = A_rl | B_rl;
2'b10 : logical_ref = A_rl ^ B_rl;
2'b11 : logical_ref = ~A_rl;
endcase
end
endfunction
//task for shift check
task shift_check (input [`WIDTH - 1 : 0] A_s);
begin
a = A_s;
sel[3] = 1'b1;
sel[4] = 1'b0;
Gujarat Technological University
44
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Implementation
//loop thorugh control signals
for (i_s=0; i_s<4; i_s=i_s+1) begin
//set control signals
{sel[0],sel[1]} = i_s;
f_exp = shift_ref({sel[0],sel[1]},A_s);
#1;
if (f_exp == f)
$display("SUCCESS ; ALU output : %d , Reference output : %d, at %t",f,f_exp,$time);
else
$display("FAIL ; ALU output : %d , Reference output : %d, at %t",f,f_exp,$time);
#5;
end//for end
end//begin end
endtask
//function to run shift operation
function [`WIDTH-1:0] shift_ref (input [1:0] s_ref, input [`WIDTH - 1 : 0] A_rs);
begin
case(s_ref)
2'b00 : shift_ref = A_rs<<2;
2'b01 : shift_ref = A_rs>>2;
2'b10 : shift_ref = A_rs<<<2;
2'b11 : shift_ref = A_rs>>>2;
endcase
end
endfunction
Gujarat Technological University
45
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Implementation
endmodule
4.3.1 SIMULATION RESULTS
Fig 4.4
Fig 4.5
ModelSim Simulation for Self-Checking Test Bench
Self-check from Console for Simulation Results
Gujarat Technological University
46
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Conclusion and Discussion
CHAPTER 5: CONCLUSION AND DISCUSSION
The project as described in this report concludes the operation and verification of a 32-bit ALU.
This project demonstrates the use of Xilinx ISE tool for digital circuit designing and
verification of the same. This project demonstrates the use of Verilog HDL for programming
such digital systems and writing the test benches for the same. (Taraate, 2017)
The 32 bit ALU, as shown demonstrates 18 operations, 7 arithmetic operations which include
addition, addition with carry, subtraction, subtraction with borrow, increment, decrement, and
transfer, 4 logical operations that include AND, OR, XOR, and NOT operations, and finally 4
shift operations which include 2 logical shifts and 2 arithmetic shifts (left and right).
This project was made possible via the training and resources that were available to me during
my internship at Indicus Technology, Ahmedabad. Over a 12-week period I learned about
digital fundamentals, learned to use the Xilinx ISE tool, writing program in Verilog HDL, and
various methods of verification of a design.
Verilog is not ideally suited for abstract system-level simulation, prior to the hardwaresoftware split. This is, to some extent, can be dealt by System Verilog. Unlike VHDL, which
has support for user-defined types and overloaded operators which allow the designer to
abstract his work into the domain of the problem, Verilog restricts the designer to be working
with pre-defined system functions and tasks for stochastic simulation and can be used for
modelling performance, throughput and queueing but only in so far as those built-in language
features allow. Designers occasionally use the stochastic level of abstraction for this phase of
the design process.
Gujarat Technological University
47
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Conclusion and Discussion
Verilog is suitable for its use in digital hardware design process, from functional simulation,
manual design and logic synthesis down to gate-level simulation. Verilog tools provide an
integrated design environment in this area. Verilog is also suited for specialized
implementation-level design verification tools such as fault simulation, switch level simulation
and worst case timing simulation. Verilog can be used to simulate gate level fan-out loading
effects and routing delays through the import of SDF files. The RTL level of abstraction is
used for functional simulation prior to synthesis. The gate level of abstraction exists postsynthesis but this level of abstraction is not often created by the designer, it is a level of
abstraction adopted by the EDA tools (synthesis and timing analysis, for example).
5.1 LIMITATION AND FUTURE ENHANCEMENT
The ALU design as presented in this project is a simplified version of real-world ALUs.
Modern day CPUs use more than one ALUs each with its own set of sophisticated operations.
This project is only helpful to demonstrate the process of developing such ALUs. The three
fundamental units of any ALU include arithmetic, logical, and shift unit, which are
programmed and simulated here.
This ALU design can be enhanced in terms of its operation speeds, and total number of
operations that take place. One such example to reduce design are and increase speed, is to use
a controlled Adder-Subtractor for addition and subtraction. Such a circuit consists of a full
adder connected in a cascaded way, with a control signal given to each full adder that
complements the input of subtrahend when subtraction is to be performed. Many such smaller
and sophisticated design can help make this ALU faster, smaller, and less power consuming.
Which is the general approach towards any digital design.
Gujarat Technological University
48
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Conclusion and Discussion
Another form of implementation involves the use of Vedic mathematics for reversibility of
logic gates. Here Vedic algorithm (Urdhva Triyambakam Sutra-16 sutras) can be used for
faster execution of an arithmetic module of an ALU. A Vedic Multiplier is designed using
Reversible logic gates and adders. Vedic multiplier increases the speed of the Architecture.
Here Reversibility is used to reduce the complexity. Reversible gates are circuits in which
number of outputs is equal to the number of inputs and there is a one to one correspondence
between inputs and outputs. (Priyanka, 2017)
5.2 CONTINUOUS EVALUATION
Table 5.1
DATE
Continuous Evaluation dates with objective of the week
OBJECTIVE OF THE WEEK
TOTAL HOURS
SPENT IN WEEK
23-02-2022  Introduction to VLSI
10 hours
 VLSI Design Flow
 Scope and opportunities in VLSI
04-03-2022  Digital Electronics Introduction
10 hours
 Number systems and conversion
 Logic Gates Minimization
 Combinational Circuits
11-03-2022  Sequential Circuits
10 hours
 Timing Graphs
 Timing Analysis of Sequential Circuits
21-03-2022  Finite State Machines
10 hours
 Real world application of Finite State Machines
Gujarat Technological University
49
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Conclusion and Discussion
 Memories (Higher Level RAM synthesis from
lower level RAMs)
28-03-2022  Verilog HDL Introduction
25 hours
 Data types and operators
 Various model discussions
 LAB WORK: MUX base programs
04-04-2022  Types of constructs: branching and looping
25 hours
 Blocking and Non-Blocking Statements
 Generic Coding
11-04-2022  Self-checking TB
25 hours
 Memories
 Timescale and specific frequency clock
generation
18-04-2022  Working with memories. Understanding read and
25 hours
write operations.
 Understanding Asynchronous resets
 Working with Event Scheduler
 Code Coverage with FSMs
25-04-2022  FPGA, ASIC and SOC understanding and
25 hours
industrial applications.
02-05-2022  STA Basics
25 hours
 Delay Calculations
 Clock domain and variations
 Clock network distribution
 Understanding skew and jitter
09-05-2022  Advantage and use of System Verilog
25 hours
 Data types in system Verilog
 Working with arrays in System Verilog
Gujarat Technological University
50
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Conclusion and Discussion
16-05-2022  Task and functions in System Verilog
25 hours
 Interface in System Verilog
 OOPs and Advance OOPs Concepts
Gujarat Technological University
51
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
References
REFERENCES
1. "ALU
Definition." TechTerms.
Sharpened
Productions,
24
March
2011.
<techterms.com/definition/alu>.
2. "Arithmetic Logic Unit (ALU): Definition, Design & Function." Study.com, 22 May
2015.
<study.com/academy/lesson/arithmetic-logic-unit-alu-definition-design-
function.html>.
3. “Arithmetic
Logic
Unit
(ALU).”
Tutorialspoint.com,
02
Jan
2019.
<tutorialspoint.com/arithmetic-logic-unit-alu>
4. “Verilog
Tutorial”.
asic-world.com,
Feb
09,
2014.
<https://www.asic-
world.com/verilog/veritut.html>
5. Chandrakasan Anantha P. and Brodersen Robert W. (1995) “Minimizing Power
Consumption in CMOS Circuits” Proceedings of IEEE, Vol. 83, Issue 4, pp. 498-523.
6. Esther Rani T., Rani M.A. and Rao R. (2011) “AREA optimized low power arithmetic
and logic unit,” IEEE International Conference on Electronics Computer Technology,
pp. 224–228.
7. Geetanjali and Nishant Tripathi (2012) VHDL Implementation of 32-Bit Arithmetic
Logic Unit (ALU). International Journal of Computer Science and Communication
Engineering, IJCSCE Special issue on “Emerging Trends in Engineering”, pp 41-43.
8. Kaliamurthy S. and Sownmiya U., (2011) "VHDL design of arithmetic processor",
Global Journal of Researches in Engineering: Electrical and Electronic Engineering.
Vol. 11, Issue 6, pp 30-35.
Gujarat Technological University
52
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
References
9. Kamble Suchita and Mhala. N. N. (2012) VHDL Implementation of 8-Bit ALU, IOSR
Journal of Electronics and Communication Engineering (IOSRJECE), ISSN: 22782834, Vol. 1(I) PP 07-11.
10. Kunduru Priyanka (2017) Design and Implementation of ALU Using Application
Specific Reversibility with Vedic Mathematics. Global Journal of Research Analysis
6(3) pp 625-627.
11. M. Yamini Divya and B. K. L. Aruna (2020) Implementation of 32-Bit Adders using
Different Full Adders. International Journal of Engineering Research & Technology
(IJERT) Vol. 9(10) pp 307-314.
12. Maaz Arif; Brij Bhushan Choudhary and Nitish Kumar (2016) Implementation of Low
Power High Speed 32 bit ALU using FPGA. International Journal of Research. Vol. 3
(9) pp 418-423.
13. Navabi Zainalabedin (2007) VHDL: Modular Design and Synthesis of Cores and
Systems‖, McGraw-Hill Professional; 3rd edition.
14. Nayak, Subramanya G. (2018) Implementation of 32-Bit Arithmetic Logic Unit on
Xilinx using VHDL. Second International Conference on Computing Methodologies
and Communication pp 525-529.
15. Srivastava Richa, Imam S.A., Pandey Sujata (2009), “Low Power Design Techniques
for high performance Digital Integrated Circuits,” MASAUM Journal of Reviews and
Surveys, Vol. 1, No.1.
16. Taraate, Vaibbhav. (2017). Design Implementation Using Xilinx Vivado. PLD Based
Design with VHDL pp 369-394.
Gujarat Technological University
53
Government Engineering College,
Gandhinagar, Sector-28
Team ID: 220312
Appendix
APPENDIX
Form type
GTU Project Poster
Total
Pages
1
Date of
signature
-
AICTE: Format 1. Student Internship Program Application
1
25/04/2022
AICTE: Format 3. Objectives/ Guidelines/ Agreement: Internship
3
25/04/2022
AICTE: Format 6. Supervisor Evaluation of Intern
1
25/04/2022
AICTE: Format 7. Student feedback of Internship
2
25/04/2022
AICTE: Format 10. Attendance Sheet
4
25/04/2022
GTU: Student Weekly record (23-02-2022 to 03-03-2022)
2
03/03/2022
GTU: Student Weekly record (04-03-2022 to 11-03-2022)
2
15/03/2022
GTU: Student Weekly record (11-03-2022 to 18-03-2022)
2
22/03/2022
GTU: Student Weekly record (21-03-2022 to 25-03-2022)
2
30/03/2022
GTU: Student Weekly record (28-03-2022 to 01-04-2022)
2
06/04/2022
GTU: Student Weekly record (04-04-2022 to 08-04-2022)
3
11/04/2022
GTU: Student Weekly record (11-04-2022 to 15-04-2022)
3
19/04/2022
GTU: Student Weekly record (18-04-2022 to 22-04-2022)
3
25/04/2022
GTU: Student Weekly record (25-04-2022 to 29-04-2022)
2
25/04/2022
GTU: Student Weekly record (02-05-2022 to 06-05-2022)
2
25/04/2022
GTU: Student Weekly record (09-05-2022 to 13-05-2022)
2
25/04/2022
GTU: Student Weekly record (16-05-2022 to 23-05-2022)
2
25/04/2022
GTU: Annexure 2 Feedback form by Industry expert
1
25/04/2022
Synopsis
Gujarat Technological University
54
Government Engineering College,
Gandhinagar, Sector-28
Design and Implementation of Arithmetic & Logical Unit (ALU) using
Xilinx ISE Design Suite v14.7
Prepared by: Nishant Sahay
Guided by: Prof. Devendra Patel
Government Engineering College Gandhinagar, Sector-28
Simulation & Implementation
Introduction
 The Arithmetic Logic Unit (ALU) is a fundamental building block of the Central Processing Unit
The approach used here is to split the ALU into three modules, one Arithmetic, one Logic and one Shift
module (Fig. 7). The arithmetic, logic and shifter units introduced earlier can be combined into ALU with
common selection lines. The shift micro-operations are often performed in a separate unit, but sometimes
the shifter unit made part of overall ALU. Since the ALU is composed of three units, namely Arithmetic, Logic
and Shifter Units. For 32-bit ALU a 33 bit 4:1 MUX is needed (Table 4). A particular arithmetic or logic or shift
operation is selected according to the selection inputs S0 and S1. The final output of the ALU is determined
by the set of multiplexers with selection lines S2 and S3. The function table for the ALU is shown. The table
lists 14 micro-operations: 8 for arithmetic, 4 for logic and 2 for shifter unit. For shifter unit, the selection line
S1 is used to select either left or right shift micro-operation.
(CPU) of a computer. We can say that ALU is a core component of all central processing unit within
in a computer and is an integral part of the execution unit. (Maaz et al., 2016)
 ALU is capable of calculating the results of a wide variety of basic arithmetical and logical computations.
 The ALU takes as input the data to be operated on (called operands) and a code from the control
unit indicating which operation to perform. The output is the result of the computation. (Geetanjali
and Nishant, 2012)
Table 4: Truth Table for Arithmetic & Logic Unit
Fig. 1: ALU Block Diagram
The ALU implemented will perform the following operations:



S3
0
0
S2
0
0
S1
0
0
S0
0
0
Cin
0
1
Result
A+B
A+B+1
Operation
Addition
Addition with carry
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
1
1
1
0
0
1
1
0
1
0
1
X
X
0
1
0
1
0
1
X
X
X
X
X
X
A + B’
A + B’ + 1
A–1
A
A
A+1
A.B
A+B
A’B + AB’
A’
LSR A
LSL A
Subtraction
Subtraction with borrow
Decrement
Transfer
Transfer
Increment
AND
OR
XOR
Compliment
Shift Right
Shift Left
Arithmetic operations (addition, subtraction, increment , decrement , transfer)
Logic operations (AND, NOT, OR, EX-OR)
Shift operations (LSR,LSL)
32 bit ALU consists of an arithmetic unit, a logic unit, a shift unit, clock gating unit and an output multiplexer (Fig. 1). Here the 32-bit ALU is implemented by using the behavioural modelling style to describe how
the operation of ALU is being processed. This is accomplished by using a hardware description language
VHDL.
Fig. 8: Test Bench Simulation Results
Fig. 7: ALU—RTL Schematic
Design
32 bit ALU consists of an
arithmetic unit, a logic unit, a
shift unit, clock gating unit
and an output multiplexer.
The Logic unit (Fig. 3) does
the following tasks: logical
AND, logical OR, logical
XOR, logical NOT and complement operation (Fig. 4).
The logic unit consists of four
gates and a 4:1 multiplexer.
The output of the gates is applied to the data inputs of the
multiplexer. Using selection
lines S0 and S1 one the data
inputs of the multiplexer is selected as the output (Table 2).
The Arithmetic unit (Fig. 2)
performs 7 operations such
as addition, addition with
carry, subtraction, subtraction with borrow, increment,
decrement, transfer (Table
1). The circuit consists of a
32 bit parallel adder and thirty two numbers of single bits
4:1 multiplexer. A and B is a
32 bit input and the output is
33 bit result, there is 2 common selection lines S0 and
S1, Cin is carry input of the
parallel adder and the carry
out is Cout.
Fig. 2: Arithmetic Unit
Fig. 5: Shift Unit
Fig. 3: Logic Unit
A
B
A.B
A
B
A+B
A
B
AB’ + A’B
A
A’
Fig. 6: Logical Shifts
Fig. 4: Logical Operations
Table 1: Truth Table for Arithmetic Unit
Table 2: Truth Table for Logic Unit
S1
0
S0
0
Cin
0
Result
A+B
Operation
Addition
0
0
1
A+B+1
Addition with Carry
0
1
0
A + B’
Subtraction
0
1
1
A + B’ + 1
Subtraction with Carry
1
0
0
A -1
Decrement
1
0
1
A
Transfer
1
1
0
A
Transfer
1
1
1
A+1
Increment
Conclusion
The following project demonstrates the working, designing and implementation of a 32-bit ALU. All the schematics, chip layout and
programming were prepared using Xilinx ISE Design Suite(v14.7).
The ALU consists of three main components namely, Arithmetic
Unit, Logical Unit, and Shift Unit. Each of these components were
separately designed, programmed, tested and implemented. The
respective results are shown for the same. Finally, the ALU module
was prepared using these components and later, implemented and
tested for the same. The simulation results were then verified.
Shift unit (Fig. 5) is used to
perform logical shift operations. Shift left shifts one bit
to the left (Fig. 6) and gives a
result which is the original
number multiplied by two,
similarly shifting n times to
the left gives result which is
equivalent to the original
number multiplied by 2n
(Table 3). Shift Right shifts
one bit to the right (Fig. 6)
and gives a result which is
the original number divided
by two similarly n times to the
right gives result which is
equivalent to original number
divide by 2n (Table 3). For a
shift unit of 32-bit, the output
will be of 33-bit with 33rd bit
to be the outgoing bit.
S0
0
0
1
1
S1
0
1
0
1
Result
A.B
A+B
A‘B + AB’
~A
Operation
AND
OR
XOR
Compliment
Acknowledgement
It gives me immense pleasure to express my heartfelt gratitude and
sincere thanks to my faculty mentor Prof. Devendra H. Patel
(Assistant Professor, Electronics And Communication Engineering)
for his valuable suggestion and encouragement for the completion
of this project.
I would also like to acknowledge Indicus Technology, Ahmedabad
especially Shri Vishnu Vaishnav, under whose guidance I learned to
use the resources available to me during my internship and successfully completed this project.
Table 3: Truth Table for Shift Unit
S0
0
1
Operation
Right Shift A
Left Shift A
References
 Geetanjali and Nishant Tripathi (2012) VHDL Implementation of
32-Bit Arithmetic Logic Unit (ALU). International Journal of Computer Science and Communication Engineering, IJCSCE Special
issue on “Emerging Trends in Engineering”, pp 41-43.
 Maaz Arif; Brij Bhushan Choudhary and Nitish Kumar (2016) Implementation of Low Power High Speed 32 bit ALU using FPGA.
International Journal of Research. 3 (9): 418-423.