Smart Grids Work
Design and Simulation of a Bidirectional
Boost Three Phase Rectifier
Alejandro Figueroa Pulido - M21039
Table of contents
List of Figures ................................................................................................... 3
List of Tables..................................................................................................... 4
Introduction ...................................................................................................... 5
Bidirectional Boost Three Phase Rectifier ................................................. 5
Specifications ............................................................................................. 5
Open Loop Converter ...................................................................................... 6
Topology .................................................................................................... 6
Modulation ................................................................................................. 7
Simulations ................................................................................................ 8
PLL Design ........................................................................................................ 9
Synchronous Reference Frame - PLL ........................................................ 9
SOGI-QSG ............................................................................................... 12
Closed Loop Converter .................................................................................. 14
Rectifying Mode ...................................................................................... 16
Step function in the load current .................................................................. 18
Step function in the input voltage................................................................. 19
Inverting Mode (Grid Feeding Mode) ..................................................... 20
Step function in the reference of active and reactive power ......................... 21
Losses ............................................................................................................... 22
Component selection ................................................................................ 22
Power loss estimation .............................................................................. 23
Efficiency ................................................................................................. 24
References ....................................................................................................... 25
2
List of Figures
Figure 1: Three-phase bidirectional Boost Rectifier [1] ....................... 5
Figure 2: Three-phase bidirectional Boost Rectifier in Open Loop ..... 6
Figure 3: Grid custom block ................................................................. 6
Figure 4: Block diagram of SPWM [1]................................................. 7
Figure 5: Open loop Modulator ............................................................ 7
Figure 6: DC Bus values (voltage, current & power) ........................... 8
Figure 7: AC Grid values (voltage, current, power & PF) ................... 8
Figure 8: dq axis out of phase ............................................................... 9
Figure 9: SRF – PLL ............................................................................. 9
Figure 10: PLL small signal model ....................................................... 9
Figure 11: SRF - PLL implemented in PLECS .................................. 10
Figure 12: Frequency step of 50% ...................................................... 10
Figure 13: Voltage step of 25% .......................................................... 11
Figure 14: Distorted and unbalance grid ............................................. 11
Figure 15: SOGI-QSG......................................................................... 12
Figure 16: Sequence detection ............................................................ 12
Figure 17: SOGI-QSG block............................................................... 13
Figure 18: PLL input transition between Vabc and Vabc+ ................ 13
Figure 19: dq model for Boost rectifier [1] ......................................... 14
Figure 20: Control loop in dq reference frame ................................... 15
Figure 21: Parameters of the simulation ............................................. 15
Figure 22: Control schematic .............................................................. 16
Figure 23: Rectifying Mode scheme ................................................... 16
Figure 24: Control of the Rectifying Mode ........................................ 17
Figure 25: Step in the load current ...................................................... 18
Figure 26: Step in the input voltage .................................................... 19
Figure 27: Inverting Mode scheme ..................................................... 20
3
Figure 28: Control of the Inverting Mode........................................... 20
Figure 29: Step in the reference of active and reactive power............ 21
Figure 30: MOSFET MSC035SMA070B4 ........................................ 22
Figure 31: MOSFET losses on turn-on and turn-off........................... 22
Figure 32: MOSFET conduction losses .............................................. 23
Figure 33: Estimation of conduction and switching losses in PLECS 23
Figure 34: Converter efficiency at full load (15kW) .......................... 24
Figure 35: Efficiency variation due to a load step (22.5 kW)............. 24
List of Tables
Table 1: Specifications .......................................................................... 5
Table 2: MOSFET thermal impedance ............................................... 23
4
Introduction
The objective of this work is the design and implementation of a three-phase
bidirectional boost rectifier connected to the grid.
The paper covers the development of the open-loop topology, the
implementation of the PLL, the closed-loop control based on Park transformations and
loss estimation.
Bidirectional Boost Three Phase Rectifier
The main constraint of this topology is that the DC bus voltage needs to be higher
than the maximum line to line voltage of input generator, it is necessary to obtain full
control over the rectifier switches. Composed of three inductors at the input (one per
phase), six bidirectional switches and a capacitor to stabilize the bus voltage.
The main drawback of this rectifier is that it has poor tolerance to shoot-through of
the rectifier bridge leg which would cause the DC bus to short-circuit and complete failure
of the system [1].
Figure 1: Three-phase bidirectional Boost Rectifier [1]
Specifications
The operating specifications for this work are given in Table 1. The phase
voltage of the input three-phase network was selected in 230 VAC, with a frequency
of 50 Hz. The output voltage will be 800 volts, with a nominal power of 15 kW.
PARAMETER
VALUE
230/380 VAC
50Hz
800 V
15 kW
20kHz
Vgrid
Fgrid
Vout
Po
Fsw
Table 1: Specifications
5
Open Loop Converter
To test the topology and validate its operation it was implemented the rectifier
in open loop, that is, without control.
Topology
The topology shown in Figure 2 has been implemented in PLECS.
Figure 2: Three-phase bidirectional Boost Rectifier in Open Loop
A custom block has been created to emulate the grid. It has functionalities to
simulate grid variations and harmonic distortions (third harmonic or unbalances).
The three-phase grid is generated from a block that has the frequency and the
voltage amplitude as inputs, and by means of the Inverse Park transformation is
achieved the three-phase signals. As mentioned above, the figure below shows the
internal design of the customized grid.
Figure 3: Grid custom block
6
Modulation
The modulation used in open loop for the Rectifier is Sinusoidal Pulse Width
Modulation with symmetrical triangular carrier [1].
Figure 4: Block diagram of SPWM [1]
In this modulation approach, low frequency (sinusoidal) reference signal is
compared to a high frequency triangular carrier. If reference signal is higher than the
carrier, upper switch in the leg is turned on while lower one is off and vice-versa as it
can be seen in the right image of Figure 5.
Figure 5: Open loop Modulator
It is important to mention that independent SPWMs were implemented to
generate the pulses for each of the phases, since each one had different references
(same amplitude but 90º degrees out of phase).
7
Simulations
The bidirectional Boost rectifier has been simulated to validate the topology,
obtaining the following results. Firstly, it can be seen how the converter is in open loop
since it is not able to regulate the bus voltage when there is a load jump (Figure 6).
Figure 6: DC Bus values (voltage, current & power)
Another disadvantage of having the converter in open loop is that the grid current
may not be in phase with the voltage, thus generating reactive power that will
negatively affect the efficiency. Also, as can be seen in Figure 7 there is a certain
percentage of harmonic distortion in the grid current that is reflected in the power and
in the losses of the converter.
Figure 7: AC Grid values (voltage, current, power & PF)
8
PLL Design
To obtain a true time invariance of the transformed abc domain variables, the dq
frame needs to be always fixed to the reference vector from the domain. Therefore, the
dq frame should rotate at the same speed as the reference vector (θ= θ´), so to obtain
this, the Vq variable will be made 0.
Figure 8: dq axis out of phase
Synchronous Reference Frame - PLL
The next step is to obtain the parameters that will be used to control the converter
for phase synchronization. The input is the three-phase voltage of the grid, or the
positive sequence obtained in the SOGI block described in the next section. At the
output, it is obtained the parameter theta used in the control loop to adapt the converter
to the operating sequence of the grid.
Figure 9: SRF – PLL
Firstly, it is necessary to obtain the parameters of the PI regulator, in the Figure
10 it is seen the PLL small signal model.
Figure 10: PLL small signal model
9
➢ 𝑲=
𝐼 1
𝐾 (1 + 𝑠) ∗ 𝑠
𝜃´
𝐾𝑠 + 𝐾 ∗ 𝐼
=
= 2
𝐼
1
𝜃 1 + 𝐾 (1 + ) ∗
𝑠 + 𝐾𝑠 + 𝐾𝐼
𝑠 𝑠
➢ 𝑰=
𝟗,𝟐
𝑻𝑺
𝟐,𝟑
𝑻𝑺
= 𝟗𝟐𝟎𝟎
= 𝟐𝟑𝟎𝟎
4,6
➢ 𝑇𝑆 = 𝑊
𝑛 ∗𝛾
= 1𝑚𝑠
The parameters obtained analytically from the regulator were implemented in
the PLECS simulation (Figure 11). Note that the Vq parameter is multiplied by a gain
to achieve a voltage close to unity, and the angular velocity of grid is added to the PI
output to achieve a faster loop.
Figure 11: SRF - PLL implemented in PLECS
The SRF-PLL has been tested for a 50% frequency step, for a 25% voltage
step in the amplitude of the grid and for an unbalanced grid with a direct sequence of
the third harmonic with 10% amplitude.
In the following scopes the voltages in the phases a, b and c are presented in the
top, followed by the angle estimation of the PLL used for all dq transformations in the
circuit, and finally the voltages in d and q axes.
Note that in the figures below, for all the grid conditions, the SRF-PLL can
follow the network.
Figure 12: Frequency step of 50%
10
Figure 13: Voltage step of 25%
As can be seen in Figure 14, when introducing a significant distortion to the grid,
both Vd and Vq start to oscillate because the PLL is not able to accurately track the
frequency of the grid. This is an important problem because it will cause a malfunction
of the converter in closed loop, that is why SOGI-QSG is implemented to avoid it.
Figure 14: Distorted and unbalance grid
11
SOGI-QSG
SOGI-QSG allows to track the frequency of the grid. In this case, the input of
the SOGI block would be the three-phase voltage of the grid and it would obtain the
positive sequence of the same (the negative is also extracted to check the proper
functioning of the system).
Figure 15: SOGI-QSG
The signals obtained at the output of the SOGI-QSG block are two sines (v' and
qv') with an offset of 90º. The component v' has the same magnitude and phase as the
input signal v (in this case an abc → alpha-beta transformation is previously done).
By adjusting the gain of the configuration (Ks in the figure above) it is possible
to vary the bandwidth and the dynamic response: as Ks decreases the frequency range
is narrower and the dynamic response slower.
In the following schematic the treatment described above is carried out for the
voltage grid signal corresponding to the alpha and beta coordinates. Once these are
tracked and v' and qv' are obtained in each block, it is operated to obtain the positive
sequence and the negative sequence.
Figure 16: Sequence detection
12
The SOGI block implementation is as follows (Figure 17), the gain Ks is fixed
in 1 and w is the angular velocity of the grid.
Figure 17: SOGI-QSG block
To check that the SOGI-QSG block works correctly, it was changed the PLL
input, previously Vabc, to the positive sequence of Vabc to immunize the PLL from
possible distortions in the grid.
Figure 18: PLL input transition between Vabc and Vabc+
You can see in the previous scope how the positive sequence of the grid is
obtained without any distortion, and after 0.96 s (time where the transition between
the PLL inputs is made) the frequency tracking is much more accurate, removing the
oscillations generated by the distortions of the grid.
13
Closed Loop Converter
In this section the modulation signal will be generated, which will allow by
means of a modulator block, to produce the PWM that makes the converter work in
closed loop.
The control is performed in the dq-axis from the converter plant as show in the
next figure.
Figure 19: dq model for Boost rectifier [1]
The equations obtained from this model are the following:
➢ L
𝑑𝑖𝑑
➢ L
𝑑𝑖𝑞
➢ 𝐶
𝑑𝑉𝑜𝑢𝑡
= 𝑉𝑑 − 𝑅 ∗ 𝑖𝑑 + 𝑤 ∗ 𝐿 ∗ 𝑖𝑞 − 𝑑𝑑 ∗ 𝑉𝑜𝑢𝑡
𝑑𝑡
𝑑𝑡
= 𝑉𝑞 − 𝑅 ∗ 𝑖𝑞 − 𝑤 ∗ 𝐿 ∗ 𝑖𝑑 − 𝑑𝑞 ∗ 𝑉𝑜𝑢𝑡
𝑑𝑡
3
𝑉𝑜𝑢𝑡
2
𝑅𝑜𝑢𝑡
= ∗ (𝑑𝑑 ∗ 𝑖𝑑 + 𝑑𝑞 ∗ 𝑖𝑞 ) −
The obtained dq model is behaving like a DC circuit, which will simplify the
analysis and design of the regulator.
It also provides independent control of active power by the d-channel and
reactive power by the q-channel. If unity PF is required, it can be obtained simply by
forcing iq to zero and the amount of active power transfer is then determined by id
through duty cycle dd.
The control of the closed-loop converter is characterized in Figure 20. Two
important things to mention, the first one is that there is a cross-coupling between the
quantities of the d-axis and the q-axis due to presence of cross-coupled current
controlled voltage sources wLiq and wLid. And the second one is that the reference of
id and iq will be obtained depending on the operational mode of the converter:
Rectifying or Inverting mode.
14
Figure 20: Control loop in dq reference frame
The control is divided into two different branches, on one hand the treatment of
the signal d, in which the main objective is to correct the error in the grid current by
means of a comparison with the current to be obtained, that will depend on the
operational mode. Then, the PI controller is introduced which allows us to adjust the
dynamics of the closed loop and the effect of Ed.
On the other hand, in the q branch of the scheme, a 0 is set as a reference since
the converter is intended to work as a PFC circuit and therefore the power factor should
be unity or very close to it. In both operational modes the iq reference is obtained by
the reactive power.
The result of this control (Ed and Eq) is combined with the theta obtained in the
PLL block to make the inverse Park transformation (dq →γβ), which would result in
the voltages used to make the modulation.
The design of the regulator for the current loop has been obtained as follows:
• ̃
𝑉𝐿 = (𝑅 + 𝐿𝑠) ∗ 𝐼̃𝐿 → 𝑮(𝒔) =
• 𝑳(𝒔) =
• 𝑹(𝒔) =
𝑾𝑩𝑾
𝒔
𝑰̃𝑳 (𝒔)
̃𝑳 (𝒔)
𝑽
𝟏
= (𝑹+𝑳𝒔)
= 𝑅(𝑠) ∗ 𝐺(𝑠)
𝑾𝑩𝑾
𝒔
𝟏
(𝑹+𝑳𝒔)
=
𝑾𝑩𝑾 ∗(𝑹+𝑳𝒔)
𝑺
= (𝑾𝑩𝑾 ∗ 𝑳) + (
𝑾𝑩𝑾 ∗𝑹
Figure 21: Parameters of the simulation
15
𝒔
)
This converter is bidirectional, so it is necessary that it works in both directions,
when it absorbs power from the grid it will work in the rectifier mode and when it delivers
power it will work in the inverter mode. That is why it will be necessary to implement
both controls depending on the mode of operation.
The following figure shows the implementation of the converter control with both
operating modes, the transition between them occurs when the converter switches from
absorbing to delivering power or vice versa.
Figure 22: Control schematic
Two different simulations will be used to verify the proper functioning of the
closed loop, first it will be implemented the rectifying mode and next the inverting
mode.
Rectifying Mode
In our case the three-phase bidirectional Boost (AC/DC block) is part of a twostage ESS (Energy Storing System) connected to a battery. During the rectifier mode
the battery is charging, this means that the converter is absorbing power from the grid.
Figure 23: Rectifying Mode scheme
16
The following figure shows the rectifier mode control. In this case it is necessary
to control the bus voltage, therefore an external voltage loop is implemented, where
the id reference is obtained. Also, it is controlled the reactive power in the q-branch in
order to obtain unity PF.
Figure 24: Control of the Rectifying Mode
The design of the regulator for the voltage control has been obtained as follows:
• 𝑉̃𝑜 =
1
𝐶𝑠
1
𝑅𝑜 +
𝐶𝑠
𝑅𝑜 ∗
• 𝑳(𝒔) =
• 𝑹(𝒔) =
2
𝑾𝑩𝑾𝟐
𝒔
̃
𝑹𝒐
𝑰𝒅
𝟏+𝑹𝒐 ∗𝑪∗𝒔
3
𝑽 (𝒔)
∗ ∗ 𝑑𝑑 ∗ 𝐼̃𝑑 → 𝑮(𝒔) = ̃𝒐(𝒔) =
𝟑
∗ ∗ 𝒅𝒅
𝟐
= 𝑅(𝑠) ∗ 𝐺(𝑠)
𝑾𝑩𝑾𝟐
𝒔
𝑹𝒐
𝟑
∗ ∗𝒅
𝟏+𝑹𝒐 ∗𝑪∗𝒔 𝟐 𝒅
𝑾𝑩𝑾𝟐
=(
𝒅𝒅
𝟐
𝑾𝑩𝑾𝟐
𝟑
𝒔
∗ ∗ 𝑪) + (
𝟐
𝟏
𝟑
𝒅𝒅 ∗𝑹𝒐
∗ ∗
)
Note that the current loop must be faster than the voltage loop to avoid losing
the reference. Therefore, the current loop bandwidth is set one decade after, Wbw =
10*Wbw2.
➢ Wbw= 1000*2*π
➢ Wbw2= 100*2*π
17
Step function in the load current
The result of this test shows that the specified output voltage (800V) is achieved
without problems, getting a good dynamic response when the load step is
implemented. In addition, the line currents meets the specifications with respect to the
power factor close to unity that characterizes the topology.
The nominal power is established in 15kW, for the current step a load with a
twice bigger value than the original load is parallelized to increase the power to
22.5kW.
Figure 25: Step in the load current
18
Step function in the input voltage
For the experiment to introduce a step in the input voltage, the results shows that
it is achieved the required output voltage (800V) with a good dynamic response when
the input voltage step is implemented. Also as in the other test, the line currents meets
the specifications with respect to the unity power factor.
The nominal rms input voltage is established in 230VAC and with the input
voltage step it reaches 322VAC, a 40% increase compared with the original values.
Figure 26: Step in the input voltage
19
Inverting Mode (Grid Feeding Mode)
During the inverting mode, also known as grid feeding mode, the battery is
discharging which means that the converter is delivering power to the grid.
Figure 27: Inverting Mode scheme
The following figure shows the inverting mode control. In this case it is
necessary to control the active power, where the id reference is obtained, and the
reactive power delivered to the grid, from which it is obtained the iq reference.
Figure 28: Control of the Inverting Mode
20
Step function in the reference of active and reactive power
For this experiment it was introduce a step in the reference of the active and
reactive power, the results shows that the specified powers are achieved with a fast
dynamic response when the step is implemented. Also, for the inverting mode control
the line currents goes in phase with the grid voltage, having unity power factor.
Firstly, the converter is delivering to the grid the nominal power established
(P=-15kW and Q=0) with PF=1. When the step is introduced, the active power is
reduced to -10kW and the reactive increases to -5kW instantaneously. It is important
to mention that by having reactive power the current will be out of phase with the grid
voltage, introducing higher losses and reducing the PF as it can be seen in Figure 29.
Figure 29: Step in the reference of active and reactive power
21
Losses
Component selection
In order to obtain the losses of the converter it was necessary to make a
component selection. The MOSFETs that met the blocking voltage condition were
filtered, trying not to oversize them since the higher the blocking voltage, the higher
the switching losses, which means lower efficiency.
It was finally decided on the MSC035SMA070B4 model from Microsemi. This
device is a 900V SiC MOSFET with a TO-247 package.
Figure 30: MOSFET MSC035SMA070B4
Within PLECS, thermal models were introduced in order to get results closer to
reality. The first images show the switching losses of the MOSFETs, the left graph
shows the losses due to switching on and the right graph shows the losses due to
switching off.
Figure 31: MOSFET losses on turn-on and turn-off
The graph of the MOSFET conduction losses and the thermal impedance of the
MOSFET is shown below.
22
Figure 32: MOSFET conduction losses
Foster
R
τ
1
0.1767 K/W
0.0049771 s
2
0.11856 K/W
0.0111083 s
3
0.07442 K/W
0.0102448 s
4
0.0269 K/W
0.0001335 s
Table 2: MOSFET thermal impedance
Power loss estimation
PLECS was used to calculate the conduction and switching losses by summing
the losses that occur during a switching cycle in the MOSFETs, their parasitic diodes
and in the inductors of each phase.
Figure 33: Estimation of conduction and switching losses in PLECS
23
Efficiency
To calculate the efficiency of the converter, the rectifier mode was implemented.
First, the efficiency was evaluated at nominal power and then a load step was
introduced to check its variation.
Figure 34: Converter efficiency at full load (15kW)
It was also tested how an increase in the power from 15kW to 22.5kW could
affect the efficiency as shown in the following scope.
Figure 35: Efficiency variation due to a load step (22.5 kW)
Due to the increase in the load, the efficiency decreases by 0.4% to 98.1%. For
the calculation of efficiency, several PLECS blocks have been used to obtain the
following formula:
𝑃𝑖𝑛
𝑃𝑙𝑜𝑠𝑠
𝜂=
= 1−
𝑃𝑖𝑛 + 𝑃𝑙𝑜𝑠𝑠
𝑃𝑖𝑛 + 𝑃𝑙𝑜𝑠𝑠
➢ Efficiency at full load (15kW): 98.5%
➢ Efficiency with the load step (22.5kW): 98.1%
24
References
[1]
U. Borović, Analysis and Comparison of Different Active
Rectifier Topologies for Avionic Specifications, 2014.
[2]
Kim, Ju-Hye & Jou, Sung-Tak & Choi, Dae-Keun & Lee,
Kyo-Beum. (2013). Direct Power Control of Three-Phase Boost
Rectifiers by using a Sliding-Mode Scheme. Journal of Power
Electronics. 13.
[3]
Frisfelds, K. & Krievs, Oskars. (2019). Design of a ThreePhase Bidirectional PWM Rectifier with Simple Control
Algorithm. Latvian Journal of Physics and Technical Sciences.
[4]
Kadhum, Zainab & Hassan, Turki. (2020). ANALYSIS
AND SIMULATION OF A THREE-PHASE MULTILEVEL
RECTIFIER. Journal of Engineering and Sustainable
Development.
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