UNIVERSAL COLLEGE OF ENGINEERING & TECHNOLOGY
DOKIPARRU (V), MEDIKONDURU (M), GUNTUR-522438
Affiliated to JNTU, Kakinada & Approved by AICTE, New Delhi
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
COURSE FILECONTENTS
Sl.
No
Description
1
2
3
4
5
A
B
I.
I.
II.
III.
IV.
6
7
8
C
I.
II.
III.
9
IV.
10
V.
11
12
13
14
15
16
D
E
VI.
I.
I.
II.
III.
IV.
17
18
19
20
21
22
23
24
25
26
27
F
G
I.
II.
III.
IV.
V.
VI.
VII.
H
I.
II.
I
I.
II.
28
J
I.
29
K
I.
Available/Not
Available
Contents of Course File
Syllabus with Prescribed text books
Course Objectives and Outcomes
CO-PO and PSO mapping with justification
Gap Identification and Contents Beyond Syllabus with
mapping
Academic Calendar
Teaching/Instructional Plan
Instructional Methodology – Pedagogical initiatives and
Innovation
Assessment of Attainment of COs Plan – Direct and
Indirect
University Results for Previous years and Current
Attainment Target
Individual Time Table
Course Materials/Notes – Unit wise
Previous Question papers – Internal and External
Question Bank – Unit wise
Assignment and Tutorial Questions with Scheme
Internal Examination – Question Papers with Key and
Scheme of Evaluation
Attendance Record
List of Slow Learners in the course
List of Advanced Learners and Programs conducted
Remedial Classes to the Slow Learners
Remedial Classes Attendance Report
Syllabus Coverage – Prescribed and Actual
Make Up classes - Schedule
Evaluation Record – Internal, Quiz and Assignments
Sample Internal Answer Scripts and Assignments
Attainment Record – Direct and Indirect
Attainment Analysis – Corrective Action/Remedial
Measures
University Results – Regular, Revaluation, Supplementary
(1st)
Course Closure Report – Suggestion for Continuous
Improvement
Signature of the Faculty
Signature of the HoD
UNIVERSAL COLLEGE OF ENGINEERING & TECHNOLOGY
DOKIPARRU (V), MEDIKONDURU (M), GUNTUR-522438
Affiliated to JNTU, Kakinada & Approved by AICTE, New Delhi
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
CMOS MIXED SIGNAL CIRCUIT DESIGN
SYLLABUS
UNIT-I: Switched Capacitor Circuits
Introduction to Switched Capacitor circuits- basic building blocks, Operation and Analysis,
Non- ideal effects in switched capacitor circuits, Switched capacitor integrators first order
filters, Switch sharing, biquad filters.
UNIT-II: Phased Lock Loop (PLL)
Basic PLL topology, Dynamics of simple PLL, Charge pump PLLs-Lock acquisition,
Phase/Frequency detector and charge pump, Basic charge pump PLL, Non-ideal effects in
PLLs- PFD/CP non-idealities, Jitter in PLLs, Delay locked loops, applications.
UNIT-III: Data Converter Fundamentals
DC and dynamic specifications, Quantization noise, Nyquist rate D/A converters- Decoder
based converters, Binary-Scaled converters, Thermometer-code converters, Hybrid
converters
UNIT-IV: Nyquist Rate A/D Converters
Successive approximation converters, Flash converter, Two-step A/D converters,
Interpolating A/D converters, Folding A/D converters, Pipelined A/D converters, Timeinterleaved converters.
UNIT-V: Oversampling Converters
Noise shaping modulators, Decimating filters and interpolating filters, Higher order
modulators, Delta sigma modulators with multibit quantizers, Delta sigma D/A
TEXT BOOKS:
1.Design of Analog CMOS Integrated Circuits- BehzadRazavi, TMH Edition, 2002
2.CMOS Analog Circuit Design - Philip E. Allen and Douglas R. Holberg, Oxford University
Press, International Second Edition/Indian Edition, 2010.
3.Analog Integrated Circuit Design- David A. Johns,Ken Martin, Wiley Student Edition,
2016
REFERENCE BOOKS:
1.CMOS Integrated Analog-to- Digital and Digital-to-Analog converters-Rudy Van De
Plassche, Kluwer Academic Publishers, 2003
2.Understanding Delta-Sigma Data converters-Richard Schreier, Wiley Interscience, 2005.
3.CMOS Mixed-Signal Circuit Design - R. Jacob Baker, Wiley Interscience, 2009.
Signature of the Faculty
Signature of the HoD
UNIVERSAL COLLEGE OF ENGINEERING & TECHNOLOGY
DOKIPARRU (V), MEDIKONDURU (M), GUNTUR-522438
Affiliated to JNTU, Kakinada & Approved by AICTE, New Delhi
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
COURSE OBJECTIVES & OUTCOMES
NAME OF THE FACULTY: Mr. Dr.Tejavath
DESIGINATION: PROFESSOR.
ACADEMIC YEAR: 2018-19
REGULATION: R16
COURSE, BRANCH: M.Tech VLSID
YEAR&SEM: I & II
SUBJECT: CMSCD
CODE: J6802
COURSE OBJECTIVES:
The main objectives of this course are to understand:
OB.1.To Introduction to Switched Capacitor circuits- basic building blocks.
OB.2.To teaches the Basic PLL topology, Dynamics of simple PLL.
OB.3.To introduces the Data Converter theory and applications.
OB.4.To teaches the theory of Nyquist Rate A/D Converters.
OB.5.To introduce the concepts of Delta sigma modulators with multibit quantizers
COURSE OUTCOMES:
At the end of this course the student can able to:
CO.1.Identify the significance of Switched capacitor integrators first order filters
CO.2.Analyze various Charge pump PLLs, Jitter in PLLs and Delay locked loops
CO.3. Analyze various Nyquist rate D/A converters: Thermometer-code converters, Hybrid
converters
CO.4.Design A/D converters, Folding A/D converters, Pipelined A/D converters Waveforms
using Op-Amp 741
CO.5. Analyze Delta sigma modulators with multibit quantizers
Signature of the Faculty
Signature of the HoD
UNIVERSAL COLLEGE OF ENGINEERING & TECHNOLOGY
DOKIPARRU (V), MEDIKONDURU (M), GUNTUR-522438
Affiliated to JNTU, Kakinada & Approved by AICTE, New Delhi
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
CO: PO and PSO Mapping
NAME OF THE FACULTY: Mr. Dr.Tejavath
DESIGINATION: PROFESSOR.
ACADEMIC YEAR: 2018-19
REGULATION: R16
COURSE ,BRANCH: M.Tech VLSID
YEAR&SEM: I & II
SUBJECT: CMSCD
CODE: J6802
2
3
1
2
2.66 1
PSO3
1
PSO2
3
2
1
2
3
2
2
3
2
2
3
2
2
3
2
1
2.33 1
PO12
3
3
PO11
1
3
PO10
2
1
PO9
3
2
PO8
1
3
PO7
2
2
PO6
2
PO5
1
PO4
3
PSO1
AVG.
PO3
CO.1: Identify the significance of
Switched capacitor integrators first
order filters
CO.2: Analyze various Charge
pump PLLs, Jitter in PLLs and
Delay locked loops
CO.3: Analyze various Nyquist
rate D/A converters: Thermometercode converters, Hybrid converters
CO.4: Design A/D converters,
Folding A/D converters, Pipelined
A/D converters Waveforms using
Op-Amp 741
CO.5: Analyze Delta sigma
modulators
with
multibit
quantizers
PO2
Course Outcomes
PO1
After the completion of the course the students will be able to,
Note:Enter Correlation levels 1,2 or 3 as defined below:
1: Slightly(Low)
If there is no correlation, put “-“
2: Moderate(Medium)
3: Substantial(High)
UNIVERSAL COLLEGE OF ENGINEERING & TECHNOLOGY
DOKIPARRU (V), MEDIKONDURU (M), GUNTUR-522438
Affiliated to JNTU, Kakinada & Approved by AICTE, New Delhi
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
CO: PO and PSO Mapping with Justification:
CO
Justification
1
CO1 is strongly mapped with PO1,Moderately mapped to PO3, lightly mapped with
PO2,PO4and strongly mapped with PSO2, Moderately mapped with PSO1
To introduce the concept of Switched Capacitor circuits- basic building blocks and types to
analyze the Switched capacitor integrators first order filters to student.
2
CO2 is strongly mapped with PO3, lightly mapped toPO2,PO4,Moderately mapped to
PO2 and strongly mapped with PSO2, Moderately mapped with PSO1
To distinguish between Charge pump PLLs and Basic charge pump PLL and understand
the significance of Non-ideal effects in PLLs.
3
CO3 is strongly mapped with PO3, lightly mapped to PO1, Moderately mapped to
PO2 and strongly mapped with PSO2, Moderately mapped with PSO1
To analyze the characteristics of Nyquist rate D/A converters- Decoder based converters,
Binary-Scaled converters.
4
CO4is strongly mapped with PO1, lightly mapped to PO2, Moderately mapped to
PO3 and strongly mapped with PSO2, Moderately mapped with PSO1
To conceptually understand the Interpolating A/D converters, Folding A/D converters,
Pipelined A/D converters, Time-interleaved converters.
5
CO5 is strongly mapped with PO1, lightly mapped to PO2,PO4, Moderately mapped
to PO3 and strongly mapped with PSO2, Moderately mapped with PSO1
To determine the Delta sigma modulators with multibit quantizers, Delta sigma D/A
.
Signature of the Faculty
Signature of the HoD
UNIVERSAL COLLEGE OF ENGINEERING & TECHNOLOGY
DOKIPARRU (V), MEDIKONDURU (M), GUNTUR-522438
Affiliated to JNTU, Kakinada & Approved by AICTE, New Delhi
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
NAME OF THE FACULTY: Mr. Dr.Tejavath
DESIGINATION: PROFESSOR.
ACADEMIC YEAR: 2018-19
REGULATION: R16
COURSE, BRANCH: M.Tech VLSID
YEAR&SEM: I & II
SUBJECT: CMSCD
CODE: J6802
ACADEMIC CALENDAR
UNIVERSAL COLLEGE OF ENGINEERING & TECHNOLOGY
DOKIPARRU (V), MEDIKONDURU (M), GUNTUR-522438
Affiliated to JNTU, Kakinada & Approved by AICTE, New Delhi
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
LESSON PLAN
NAME OF THE FACULTY: Mr. Dr.Tejavath
DESIGINATION: PROFESSOR.
ACADEMIC YEAR: 2018-19
REGULATION: R16
COURSE, BRANCH: M.Tech VLSID
YEAR&SEM: I & II
SUBJECT: CMSCD
CODE: J6802
PERIODS
REQUIRED
UNIT
NAME OF THE TOPIC
10
I
Switched Capacitor Circuits:
Introduction to Switched Capacitor circuits- basic building blocks
Operation and Analysis
Non- ideal effects in switched capacitor circuits
Switched capacitor integrators first order filters
Switch sharing
biquad filters
Phased Lock Loop (PLL)
Basic PLL topology, Dynamics of simple PLL
Charge pump PLLs-Lock acquisition
Phase/Frequency detector and charge pump
Basic charge pump PLL
Non-ideal effects in PLLs- PFD/CP non-idealities
Jitter in PLLs
Delay locked loops, applications
Data Converter Fundamentals
10
DC and dynamic specifications
Quantization noise,
Nyquist rate D/A converters- Decoder based converters
Binary-Scaled converters
Thermometer-code converters
Hybrid converters
1
2
1
1
1
1
Nyquist Rate A/D Converters
10
Successive approximation converters
Flash converter
1
1
2
II
III
IV
Two-step A/D converters
Interpolating A/D converters
Folding A/D converters
Pipelined A/D converters
2
2
1
2
2
1
2
1
2
1
2
1
2
REFERENCE
T-1, REF-1
T-1,2 REF-2
7
1
2
1
REF-3
T-3,REF-2
V
Time-interleaved converters
2
Oversampling Converters
8
Noise shaping modulators
Decimating filters and interpolating filters
Higher order modulators
Delta sigma modulators with multibit quantizers
Delta sigma D/A
2
1
2
1
2
Total Classes Required
REF-1
45
TEXT BOOKS:
1.Design of Analog CMOS Integrated Circuits- BehzadRazavi, TMH Edition, 2002
2.CMOS Analog Circuit Design - Philip E. Allen and Douglas R. Holberg, Oxford University
Press, International Second Edition/Indian Edition, 2010.
3.Analog Integrated Circuit Design- David A. Johns,Ken Martin, Wiley Student Edition,
2016
REFERENCE BOOKS:
1.CMOS Integrated Analog-to- Digital and Digital-to-Analog converters-Rudy Van De
Plassche, Kluwer Academic Publishers, 2003
2.Understanding Delta-Sigma Data converters-Richard Schreier, Wiley Interscience, 2005
3.CMOS Mixed-Signal Circuit Design - R. Jacob Baker, Wiley Interscience, 2009.
Signature of the Faculty
Signature of the HoD
UNIVERSAL COLLEGE OF ENGINEERING & TECHNOLOGY
DOKIPARRU (V), MEDIKONDURU (M), GUNTUR-522438
Affiliated to JNTU, Kakinada & Approved by AICTE, New Delhi
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
Instructional Methodology – Pedagogical Initiatives and Innovation
NAME OF THE FACULTY: Mr. Dr.Tejavath
DESIGINATION: PROFESSOR.
ACADEMIC YEAR: 2018-19
REGULATION: R16
COURSE, BRANCH: M.Tech VLSID
YEAR&SEM: I & II
SUBJECT: CMSCD
CODE: J6802
S.NO
1
2
3
4
5
6
1
2
3
4
5
6
7
1
2
3
4
5
6
NAME OF THE TOPIC
UNIT-1 Switched Capacitor Circuits
Introduction to Switched Capacitor circuits- basic building
blocks
Operation and Analysis
Non- ideal effects in switched capacitor circuits
Switched capacitor integrators first order filters
Switch sharing
biquad filters
UNIT-2 Phased Lock Loop (PLL)
Basic PLL topology, Dynamics of simple PLL
Charge pump PLLs-Lock acquisition
Phase/Frequency detector and charge pump
Basic charge pump PLL
Non-ideal effects in PLLs- PFD/CP non-idealities
Jitter in PLLs
Delay locked loops, applications
UNIT-3 Data Converter Fundamentals
DC and dynamic specifications
Quantization noise,
Nyquist rate D/A converters- Decoder based converters
Binary-Scaled converters
Thermometer-code converters
Hybrid converters
Instructional
Methodology
Black Board & Chalk,PPT
Black Board & Chalk,PPT
Black Board & Chalk,PPT
Black Board & Chalk,PPT
Black Board & Chalk,PPT
Black Board & Chalk,PPT
Black Board & Chalk,PPT
Black Board & Chalk,PPT
Black Board & Chalk,PPT
Black Board & Chalk,PPT
Black Board & Chalk,PPT
Black Board & Chalk,PPT
Black Board & Chalk,PPT
Black Board & Chalk,PPT
Black Board & Chalk,PPT
Black Board & Chalk,PPT
Black Board & Chalk,PPT
Black Board & Chalk,PPT
Black Board & Chalk,PPT
UNIT-4 Nyquist Rate A/D Converters
1
2
3
4
5
6
Successive approximation converters
Flash converter
Interpolating A/D converters
Folding A/D converters
Pipelined A/D converters
Time-interleaved converters
Black Board & Chalk,PPT
Black Board & Chalk,PPT
Black Board & Chalk,PPT
Black Board & Chalk,PPT
Black Board & Chalk,PPT
Black Board & Chalk,PPT
UNIT-5 Oversampling Converters
1 Noise shaping modulators
Black Board & Chalk,PPT
2
3
4
5
Black Board & Chalk,PPT
Black Board & Chalk,PPT
Black Board & Chalk,PPT
Black Board & Chalk,PPT
Decimating filters and interpolating filters
Higher order modulators
Delta sigma modulators with multibit quantizers
Delta sigma D/A
Total Classes Required
Signature of the Faculty
45
Signature of the HoD
UNIVERSAL COLLEGE OF ENGINEERING & TECHNOLOGY
DOKIPARRU (V), MEDIKONDURU (M), GUNTUR-522438
Affiliated to JNTU, Kakinada & Approved by AICTE, New Delhi
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
ASSESSMET OF ATTAINMENT OF COs PLAN – DIRECT & INDIRECT
Evaluation of Course outcomes procedure (Direct):
The affiliating University – JNTUK is not providing the average marks for defining the
Targets. The PAC collects the assessment data and conducts meetings with the course
coordinators and proposes the targets. The set targets and set attainment levels of the program
are approved by the DAB.
The course outcomes are evaluated using Internal and External assessments as per the
following:
Regulation
Internal Assessment
– Set Target
External Assessment – Set
Target
R16
40 % Marks
60 % Marks
The attainment levels are as per the following
Sl.
No
Attainment
Level
% of students attaining the Set-Target
1
3
80 % of students Scoring more than the Set Target
2
2
60 % of students Scoring more than the Set Target
3
1
40 % of students Scoring more than the Set Target
4
0
Less than 40 % of students Scoring more than the Set
Target
Evaluation of Attainment Level - CO
CO Attainment level = 40% of Internal Attainment level + 60% of External Attainment level
For R16 regulations:
Weightages for different internal assessment tools are based on % of total marks.
Theory Courses: Internal attainment level = (40% of DESCRIPTIVE )
Project Work: Internal attainment level = (50% of Review 1 + 50% of Review 2) attainment
levels
Evaluation of Course outcomes procedure (Indirect):
The CO indirect attainment values are calculated using course end survey. A survey
has been conducted at the end of every semester through online mode. All the students will
participate in surveys and give rating (0: disagree, 1: fairly agree, 2: agree and 3: strongly
agree) to course outcomes that how much they really achieved during course work. The
format is shown below.
UNIVERSAL COLLEGE OF ENGINEERING AND TECHNOLOGY
DEPARTMENT OF ECE
COURSE END SURVEY
Please take time to complete this survey in the class. Your thoughtful objective responses to
each question are highly valued part of the teaching and learning improvement process.
Academic Year: 2018-19
Class: M.Tech.(ES) I YEAR II SEM
Name:
Roll No:
Section:
The following survey is an indirect assessment of your technical abilities with respect to
subject mentioned above. Please read the following carefully and based on self-assessment of
your own capabilities and give the appropriate level from the following.
Disagree
0
Fairly Agree
1
Agree
2
Strongly Agree
3
Sl.
Assessment
No CMOS MIXED SIGNAL CIRCUIT DESIGN (J6802)
Level
of
CO
I have ability to:
Identify the significance of Switched capacitor integrators first order
3
1
filters
2
3
4
5
Analyze various Charge pump PLLs, Jitter in PLLs and Delay locked
loops
Analyze various Nyquist rate D/A converters: Thermometer-code
converters, Hybrid converters
Design A/D converters, Folding A/D converters, Pipelined A/D
converters Waveforms using Op-Amp 741
Analyze Delta sigma modulators with multibit quantizers
Average
Signature of the Faculty
Signature of the HoD
3
3
3
3
3
UNIVERSAL COLLEGE OF ENGINEERING & TECHNOLOGY
DOKIPARRU (V), MEDIKONDURU (M), GUNTUR-522438
Affiliated to JNTU, Kakinada & Approved by AICTE, New Delhi
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
UNIVERSITY RESULT
NAME OF THE FACULTY: Mr. Dr.Tejavath
DESIGINATION: PROFESSOR.
ACADEMIC YEAR: 2018-19
REGULATION: R16
COURSE, BRANCH: M.Tech VLSID
YEAR&SEM: I & II
SUBJECT: CMSCD
CODE: J6802
A.Y=2018-19
Regular Exams
S.No
Subject
1
CMSCD
S.No
Subject
1
CMSCD
No. of students
No. of students
Attended
passed
4
4
Revaluation
No. of students
Failed
0
Pass
Percentage
100%
No. of students
Attended
No. of students
Failed
Pass
Percentage
No. of students
Failed
Pass
Percentage
No. of students
passed
Supplementary Exams
S.No
Subject
1
CMSCD
Signature of the Faculty
No. of students
Attended
No. of students
passed
Signature of the HoD
UNIVERSAL COLLEGE OF ENGINEERING & TECHNOLOGY
DOKIPARRU (V), MEDIKONDURU (M), GUNTUR-522438
Affiliated to JNTU, Kakinada & Approved by AICTE, New Delhi
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
UNIVERSAL COLLEGE OF ENGINEERING & TECHNOLOGY
MTECH II Sem Result (2018 Batch) - VLSID
S.No.
H.T.No
Name of the Student
SCD
ESD
CMSCD
DFT
DSP&A
LPVD
VLSI Lab
J5702
J6801
J6802
J6804
J6805
J6806
J5704
EXT INT TOT EXT INT TOT EXT INT TOT EXT INT TOT EXT INT TOT EXT INT TOT EXT INT TOT
1
2
3
4
18NF1D7201
18NF1D7202
18NF1D7203
18NF1D7204
A DEVI VIJAYA PRASANTHI
KANCHALA VANDANA
MANISHA GUDIPUDI
MASEED FARHANA
PASS
FAIL
26
24
29
35
36
37
34
37
4
0
62
61
63
72
32
26
28
40
37
37
36
38
4
0
69
63
64
78
41
31
30
50
35
37
33
37
4
0
all pass=4
Signature of faculty
76
68
63
87
33
33
28
36
35
35
36
38
4
0
68
68
64
74
24
29
27
26
pass%age=100%
HOD
35
37
35
36
4
0
59
66
62
62
43
39
47
50
36
36
34
38
4
0
79
75
81
88
55
54
55
58
38
37
37
39
4
0
93
91
92
97
UNIVERSAL COLLEGE OF ENGINEERING & TECHNOLOGY
MTECH II Sem Result (2018 Batch) - VLSID
S.No.
H.T.No
Name of the Student
SCD
ESD
CMSCD
DFT
DSP&A
LPVD
VLSI Lab
J5702
J6801
J6802
J6804
J6805
J6806
J5704
EXT INT TOT EXT INT TOT EXT INT TOT EXT INT TOT EXT INT TOT EXT INT TOT EXT INT TOT
1
2
3
4
18NF1D7201
18NF1D7202
18NF1D7203
18NF1D7204
A DEVI VIJAYA PRASANTHI
KANCHALA VANDANA
MANISHA GUDIPUDI
MASEED FARHANA
PASS
FAIL
26
24
29
35
36
37
34
37
4
0
62
61
63
72
32
26
28
40
37
37
36
38
4
0
69
63
64
78
41
31
30
50
35
37
33
37
4
0
all pass=4
Signature of faculty
76
68
63
87
33
33
28
36
35
35
36
38
4
0
68
68
64
74
24
29
27
26
pass%age=100%
HOD
35
37
35
36
4
0
59
66
62
62
43
39
47
50
36
36
34
38
4
0
79
75
81
88
55
54
55
58
38
37
37
39
4
0
93
91
92
97
UNIVERSAL COLLEGE OF ENGINEERING & TECHNOLOGY
DOKIPARRU (V), MEDIKONDURU (M), GUNTUR-522438
Affiliated to JNTU, Kakinada & Approved by AICTE, New Delhi
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
w.e.f: 30.1.2019
CLASS TIME TABLE : 2018– 19
M.TECH II SEM (R 16) --- VLSID
D/T
MON
10:50-11:40
11:40-12:30
12:30-1:20
B
CPLD & FPGA
WLP
EN
EN
R
CMOS MSCD
HSD
SEMINAR
EN
CPLD & FPGA
E
WLP
HSD
CMOS MSCD
THU
DSPA
CMOS MSCD
A
EN
CPLD & FPGA
SEMINAR
FRI
< ----------- Embedded System Design Lab ---------- >
WLP
DSPA
HSD
SEMINAR
TUE
WED
SAT
9:00-9:50
9:50-10:40
HSD
DSPA
DSPA
CPLD & FPGA
WLP
K
CMOS MSCD
List of Faculty:
THEORY:
1. Hardware Software Co-Design
: Ms. K.Vijay Kumar
2. Digital Signal Processors and Architec
: Mr. T. Rajesh
3. Embedded Networking
: Mrs.B.Sujatha
4. CPLD and FPGA Architectures and Application: Mr.K.Sampath Singh
5. CMOS Mixed Signal Circuit Design
: Dr.Tejavath
6. Wireless LAN’s And PAN’s
: Dr.C.Karthik
LABS:
Embedded System Design Laboratory
Signature of the Faculty
:1. Mr. T. Rajesh
Signature of the HoD
UNIVERSAL COLLEGE OF ENGINEERING & TECHNOLOGY
DOKIPARRU (V), MEDIKONDURU (M), GUNTUR-522438
Affiliated to JNTU, Kakinada & Approved by AICTE, New Delhi
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
NAME OF THE FACULTY: Mr. Dr.Tejavath
DESIGINATION: PROFESSOR.
ACADEMIC YEAR: 2018-19
REGULATION: R16
COURSE, BRANCH: M.Tech VLSID
YEAR&SEM: I & II
SUBJECT: CMSCD
CODE: J6802
INDIVIDUAL TIME TABLE
D/T
MON
9:00-9:50
9:50-10:40
10:50-11:40
12:30-1:20
B
TUE
R
WED
E
THU
11:40-12:30
CMOS MSCD
CMOS MSCD
CMOS MSCD
A
FRI
SAT
Signature of the Faculty
K
CMOS MSCD
Signature of the HoD
UNIVERSAL COLLEGE OF ENGINEERING & TECHNOLOGY
DOKIPARRU (V), MEDIKONDURU (M), GUNTUR-522438
Affiliated to JNTU, Kakinada & Approved by AICTE, New Delhi
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
STUDENT ROLL LIST-MTECH (VLSID)
S.NO
ROLL NO
NAME OF THE STUDENT
1
18NF1D7201
AMULOTHU DEVI VIJAYA PRASANTHI
2
18NF1D7202
KANCHALA VANDANA
3
18NF1D7203
MANISHA GUDIPUDI
4
18NF1D7204
MASEED FARHANA
Signature of the Faculty
Signature of the HoD
UNIVERSAL COLLEGE OF ENGINEERING & TECHNOLOGY
DOKIPARRU (V), MEDIKONDURU (M), GUNTUR-522438
Affiliated to JNTU, Kakinada & Approved by AICTE, New Delhi
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
QUESTION BANK
NAME OF THE FACULTY: Mr. Dr.Tejavath
DESIGINATION: PROFESSOR.
ACADEMIC YEAR: 2018-19
REGULATION: R16
COURSE, BRANCH: M.Tech VLSID
YEAR&SEM: I & II
SUBJECT: CMSCD
CODE: J6802
UNIT-I
1. What is switched capacitor? What is its significance in the CMOS technology?
2. If C1 = C2 = C, find the value of C that will emulate a 1MΩ resistor if the clock
Frequency is 200 KHz.
3. Explain the non-ideal characteristics of a switched capacitor integrator.
4. For the above circuit, if clock frequency is 100kHz, find the capacitor value that
will minimize1M ohm resistor.
5. Draw the basic circuit of a switched capacitor, its equivalent circuit , explain its
operation and derive its equivalent resistor value.
6. Explain the techniques that are adopted in a switched capacitor integrator circuit
to minimize charge injection issues.
UNIT-2
1. Explain about the basic charge pump PLL with a neat figure.
2. With the help of necessary waveforms, explain about the non-ideal effects in PLLs.
3. Derive an integrator using switched capacitor circuit.
4. Explain the techniques that are adopted in a switched capacitor integrator circuit
to minimizecharge injection issues.
5. Explain the basic charge pump PLL and non-ideal effects in PLLs.
6. Explain the Jitter in PLLs and delay locked loops.
UNIT-3
1. What are the dynamic characteristics that influence the performance of DACs?
2. Design a decoder based DAC with a detailed explanation.
3. Give the classification of ADC architectures based on the conversion rate.
4. Explain the static and dynamic characteristics of ADCs.
5. Mention all kinds of medium speed and high speed ADC and explain the operation of
a multiple-bit pipeline ADC.
6. What is a Flash converter? Discuss the working of a 3-bit Flash A/D Converter.
7. Design a 3-bit Flash ADC with quantization error centered about zero LSBs.
8. Explain about deterministic approach and statistic approach of quantization noise in data
converters
UNIT-4
1. What is a flash converter? Explain the function of a 3 bit flash ADC.
2. What is time interleaving? Explain the operation of a time interleaved ADC.
3. Discuss about Delta-Sigma ADC.
4. Explain the block diagram of second order Delta-Sigma modulator.
5. Design a thermometer code charge redistributionD/A converter.
6. Write about hybrid converters.
7. Draw the block diagram of a D-A converter in signal processing applications.
8. Give the classification of a D-A converters.
9. Explain the static and dynamic characteristics of DAC.
10. Design a 3-bit Flash ADC with quantization error centered about zero LSBs
UNIT-5
1. Distinguish between oversampling without noise shaping and with noise shaping.
2. What are biquad filters? Explain about the two switched capacitor biquad
Realizations.
3. Design a switched capacitor realization for a first order, high pass circuit with ahigh
Frequency gain of -10 and a -3dB frequency of 1 kHz using a clock of 100kHz
4. Explain about deterministic approach and statistic approach of quantization noise in
data converters.
5. Design a thermometer code charge redistributionD/A converter.
6. Write about hybrid converters
Signature of the Faculty
Signature of the HoD
UNIVERSAL COLLEGE OF ENGINEERING & TECHNOLOGY
DOKIPARRU (V), MEDIKONDURU (M), GUNTUR-522438
Affiliated to JNTU, Kakinada & Approved by AICTE, New Delhi
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
NAME OF THE FACULTY: Mr. Dr.Tejavath
DESIGINATION: PROFESSOR.
ACADEMIC YEAR: 2018-19
REGULATION: R16
COURSE, BRANCH: M.Tech VLSID
YEAR&SEM: I & II
SUBJECT: CMSCD
CODE: J6802
Mid Question Papers
UNIVERSAL COLLEGE OF ENGINEERING & TECHNOLOGY
I M.Tech II Sem (R16) MID - I EXAMINATION
Subject: CMOSMSCD Time : 10:00 to 12:00 Noon
Date : 04.04.2019
Answer the following questions
Section : ES
Max. Marks : 40
1. a) Explain the basic building blocks of a Switched Capacitor Circuit?
b)What is the equivalent resistance of a 5pF capacitance sampled at a clock frequency of 100 kHz?
2. Explain the Non-ideal effects in PLLs
3. a) Explain the following related to quantization noise:
i) Deterministic approach
ii) Stochastic approach
b) A 100-mVpp sinusoidal signal is applied to an ideal 12-bit A/D converter for which Vref =5V. Find the
SNR of the digitized output signal.
4.a) Explain whether a master slave D flip flop can operate as a phase detector or a frequency
detector.Assume that the flip flop provides differential outputs.
b)Calculate the change in the phase error if type I PLL experience a frequency step ∆ω at t=0.
UNIVERSAL COLLEGE OF ENGINEERING & TECHNOLOGY
M.Tech II Sem MID - II EXAMINATION
Subject: CMSCD
Time : 10.00 AM to 12.00 Noon Date : 10.07.2019
Answer the following questions
Section : ES
Max. Marks : 40
1. Explain about
a) Resistor-capacitor hybrid connector
b) Segmented hybrid connector.
2. Write short notes on
a) Pipelined A/D Coverters b) Time-interlaeved A/D Coverters
3. Explain the multi-stage and single-stage decimating filters.
4.a)What is the need for Oversampling Converters?
b) Explain the second-order Delta-Sigma Modulator?
UNIVERSAL COLLEGE OF ENGINEERING & TECHNOLOGY
DOKIPARRU (V), MEDIKONDURU (M), GUNTUR-522438
Affiliated to JNTU, Kakinada & Approved by AICTE, New Delhi
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
NAME OF THE FACULTY: Mr. Dr.Tejavath
DESIGINATION: PROFESSOR.
ACADEMIC YEAR: 2018-19
REGULATION: R16
COURSE, BRANCH: M.Tech VLSID
YEAR&SEM: I & II
SUBJECT: CMSCD
CODE: J6802
MID-I QUESTION PAPER EVALUATION
Q.No Scheme
a)Explain the basic building blocks of a Switched
Capacitor Circuit?
1
2
b)What is the equivalent resistance of a 5pF
capacitance sampled at a clock frequency of 100
kHz
Explain the Non-ideal effects in PLLs
Total
Evaluation Marks
5M
10M
5M
2.5M
10M
a) Explain the following related to quantization
noise:
i) Deterministic approach ii) Stochastic approach
3
4
5M
b) A 100-mVpp sinusoidal signal is applied to an
ideal 12-bit A/D converter for which Vref =5V.
Find the SNR of the digitized output signal.
a)Explain whether a master slave D flip flop can
operate as a phase detector or a frequency
detector.Assume that the flip flop provides
differential outputs.
b)Calculate the change in the phase error if type I
PLL experience a frequency step ∆ω at t=0.
Signature of the Faculty
10M
5M
5M
10M
5M
Signature of the HoD
UNIVERSAL COLLEGE OF ENGINEERING & TECHNOLOGY
DOKIPARRU (V), MEDIKONDURU (M), GUNTUR-522438
Affiliated to JNTU, Kakinada & Approved by AICTE, New Delhi
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
NAME OF THE FACULTY: Mr. Dr.Tejavath
DESIGINATION: PROFESSOR.
ACADEMIC YEAR: 2018-19
REGULATION: R16
COURSE, BRANCH: M.Tech VLSID
YEAR&SEM: I & II
SUBJECT: CMSCD
CODE: J6802
MID-2 QUESTION PAPER EVALUATION
Q.No Scheme
a) Resistor-capacitor hybrid connector
1
b) Segmented hybrid connector
a) Pipelined A/D Coverters
2
b) Time-interlaeved A/D Coverters
Explain the multi-stage and single-stage
3
decimating filters.
a)What is the need for Oversampling Converters?
4
b)Explain the second-order Delta-Sigma
Modulator?
Signature of the Faculty
Total
Evaluation Marks
5M
5M
5M
5M
10M
5M
10M
10M
10M
10M
5M
Signature of the HoD
UNIVERSAL COLLEGE OF ENGINEERING & TECHNOLOGY
DOKIPARRU (V), MEDIKONDURU (M), GUNTUR-522438
Affiliated to JNTU, Kakinada & Approved by AICTE, New Delhi
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
SYLLABUS COVERAGE
NAME OF THE FACULTY: Mr. Dr.Tejavath
DESIGINATION: PROFESSOR.
ACADEMIC YEAR: 2018-19
REGULATION: R16
COURSE, BRANCH: M.Tech VLSID
YEAR&SEM: I & II
SUBJECT: CMSCD
CODE: J6802
Start
Remarks
Date
Completion
Date
Unit 1
19/11/18
20/12/18
-
Unit 2
21/12/18
3/1/19
-
Unit 3
12/1/19
13/2/19
-
Unit 4
04/1/19
24/1/19
Unit 5
14/2/19
28/2/19
-
Unit 6
01/3/19
23/3/19
-
Unit
Signature of the Faculty
-
Signature of the HoD
UNIVERSAL COLLEGE OF ENGINEERING & TECHNOLOGY
DOKIPARRU (V), MEDIKONDURU (M), GUNTUR-522438
Affiliated to JNTU, Kakinada & Approved by AICTE, New Delhi
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
\
MTECH (VLSID) I-II
S.NO
ROLL NO
MID-1 CONSODILATE MARKS
NAME OF THE STUDENT
MARKS
1
18NF1D7201
AMULOTHU DEVI VIJAYA PRASANTHI
35
2
18NF1D7202
KANCHALA VANDANA
37
3
18NF1D7203
MANISHA GUDIPUDI
33
4
18NF1D7204
MASEED FARHANA
37
Signature of the Faculty
HOD
UNIVERSAL COLLEGE OF ENGINEERING & TECHNOLOGY
DOKIPARRU (V), MEDIKONDURU (M), GUNTUR-522438
Affiliated to JNTU, Kakinada & Approved by AICTE, New Delhi
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
MTECH (VLSID) I-II
S.NO
ROLL NO
MID-2 CONSODILATE MARKS
NAME OF THE STUDENT
MARKS
1
18NF1D7201
AMULOTHU DEVI VIJAYA PRASANTHI
35
2
18NF1D7202
KANCHALA VANDANA
37
3
18NF1D7203
MANISHA GUDIPUDI
33
4
18NF1D7204
MASEED FARHANA
37
Signature of the Faculty
HOD
UNIVERSAL COLLEGE OF ENGINEERING & TECHNOLOGY
DOKIPARRU (V), MEDIKONDURU (M), GUNTUR-522438
Affiliated to JNTU, Kakinada & Approved by AICTE, New Delhi
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
COURSE CLOSURE REPORT
Name of the Course Coordinator
Mr. Dr.Tejavath
Course Code
J6802
Course Title
CMOSMIXEDSIGNALCIRCUITDESIGN
Class Year/Sem
MTECH(VLSI) I-II
Academic Year
2018-19
Conducted Hours
45
No. of Students
4
University Results:
Pass % of Students
% Average Marks
Minimum / Maximum marks
100%
A. Course Outcome Attainments – Targets
Sl.
Description
No
Tools
1
Internal
Assessment
Descriptive
2
External
Assessment
University
examinations
3
Indirect
Assessment
Course Exit
Survey
CO Targets Attainments Remarks
1
2
3
4
5
6
1
2
3
4
5
6
1
2
3
4
5
6
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
3
3
3
3
3
3
3
2
2.5
2.5
2.5
3
2
2
B. Action Taken to Improve the Performance in the current Semester (based on the
course closure report in the previous AY):
C. The student performance has been consistently poor with respect to some COs.
Analysis of answer scripts, exit survey and interaction with the students revealed that
this could be attributed to:
 Poor in Listening skills due to insufficient in basic Fourier series Knowledge.
 They feel difficult to draw o/p waveforms particularly 3-pahse graphs.
 50% of strength has worst paper presentation skills.
 25% of students are irregular to class work
D. Course Outcome – Suggestions – Justification
Sl. Current COs
No
1
2
3
CO.1:
Identify the significance of Switched
capacitor integrators first order filters
CO.2: Analyze various Charge pump PLLs, Jitter in
PLLs and Delay locked loops
CO.3: Analyze various Nyquist rate D/A converters:
Thermometer-code converters, Hybrid converters.
Design A/D converters, Folding A/D
converters, Pipelined A/D converters Waveforms
using Op-Amp 741
CO.4:
4
Justification
CO1 is strongly mapped with
PO1,Moderately mapped to PO3,
lightlymapped with PO2,PO4and
strongly mapped with PSO2,
Moderately mapped with PSO1
To introduce the concept of
Switched Capacitor circuits- basic
building blocks and types to
analyze the Switched capacitor
integrators first order filters to
student.
CO2 is strongly mapped with
PO3,
lightly
mapped
toPO2,PO4,Moderately mapped
to PO2 and strongly mapped
with PSO2, Moderately mapped
with PSO1
To distinguish between Charge
pump PLLs and Basic charge pump
PLL
and
understand
the
significance of Non-ideal effects in
PLLs.
CO3 is strongly mapped with
PO3, lightly mapped to PO1,
Moderately mapped to PO2 and
strongly mapped with PSO2,
Moderately mapped with PSO1
To analyze the characteristics of
Nyquist rate D/A convertersDecoder based converters, BinaryScaled converters.
CO4is strongly mapped with
PO1, lightly mapped to PO2,
Moderately mapped to PO3 and
strongly mapped with PSO2,
Moderately mapped with PSO1
To conceptually understand the
Interpolating
A/D
converters,
Folding A/D converters, Pipelined
A/D converters, Time-interleaved
converters.
5
CO5 is strongly mapped with
PO1,
lightly
mapped
to
PO2,PO4, Moderately mapped to
PO3 and strongly mapped with
CO.5: Analyze Delta sigma modulators with multibit
PSO2, Moderately mapped with
quantizers
PSO1
To determine the Delta sigma
modulators
with
multibit
quantizers, Delta sigma D/A
E. Mapping of COs (Modified) with POs – Suggestive and Justification
F. Action proposed to Improve the Performance:
 Conduct weekly tests for each unit.
 Practice previous year question papers.
 Solve more problems
 Need to provide formulas required for each unit
Signature of the Faculty
HOD
PRINCIPAL