Synchronization of complex systems Jordi Cortadella Universitat Politecnica de Catalunya Barcelona, Spain Thanks to A. Chakraborty, T. Chelcea, M. Greenstreet and S. Nowick 1 Single clock (Mesochronous) f3/f0 Rational clock frequencies CLK0 f2/f0 CLK2 CLK CLK (f0) CLK3 f1/f0 CLK1 Multiple clock domains Independent clocks (plesiochronous if frequencies closely match) 2 The problem: metastability D Q ФT D ФR Q ФR setup hold D Q ? 3 Classical “synchronous” solution D Q D Q D Q D Q ФT ФR Mean Time Between Failures fФ: frequency of the clock fD: frequency of the data tr: resolve time available W: metastability window : resolve time constant MTBF e tr 2 f f D W Example # FFs MTBF 1 FF 15 min 2 FF 9 days 3 FF 23 years 4 How to live with metastability ? Metastability cannot be avoided, it must be tolerated. Having a decent MTBF ( years) may result in a tangible impact in latency Purely asynchronous systems can be designed failure-free Synchronous and mixed synchronous-asynchronous systems need mechanisms with impact in latency But latency can be hidden in many cases … 5 Different approaches Pausible Clocks (Yun & Donohue 1996) Predict metastability-free transmission windows for domains with related clocks (Chakraborty & Greenstreet 2003) Use the waiting time in FIFOs to resolve metastability (Chelcea & Nowick 2001) And others … The term “Globally Asynchronous, Locally Synchronous” is typically used for these systems (Chapiro 1984) 6 Mutual exclusion element req1 req2 0 1 0 ack1 0 1 0 ack2 7 Metastability 8 Mutual exclusion element req1 0 req2 0 1 1 Metastability resolver 0 0 ack2 ack1 An asynchronous data latch with MS resolver can be built similarly 9 Abstraction of the MUTEX R1 G1 MUTEX R2 G2 10 A pausible clock generator Environment MUTEX [δ1, δ2] delay 11 Pausible clocks Req Ack Cntr FF ME MUTEX [δ1, δ2] delay CLK Yun & Dooply, IEEE Trans. VLSI, Dec. 1999 Moore et al., ASYNC 2002 12 STARI (Self-Timed At Receiver’s Input) Both clocks are generated from the same source The FIFO compensates for skew between transmitter and receiver M. Greenstreet, 1993 13 A Minimalist Interface FIFO reduces to latch-X and a latch controller Φx can always be generated in such a way as to reliably transfer data from input to output Chakraborty & Greenstreet, 2002 14 A Minimalist Interface: 3 scenarios Latch-X setup & hold Latch-R setup & hold Фx Permitted The scenario is chosen at initialization 15 A Minimalist Interface: latch controller The controller detects which transition arrives first (from ΦT and ΦR) and generates ΦX accordingly 16 A Minimalist Interface: rational clocks 17 A Minimalist Interface: arbitrary clocks Assumption: clocks are stable Each domain estimates the other’s frequency Residual error corrected using stuff bits 18 Sync-Async FIFO Async-Sync FIFO Mixed-Timing Interfaces Async-Sync FIFO Asynchronous Domain Synchronous Domain 2 Synchronous Domain 1 Mixed-Clock FIFO’s Chelcea & Nowick, 2001 19 full synchronous put inteface req_put data_put CLK_put Mixed-Clock FIFO Mixed-Clock FIFO: Block Level req_get valid_get empty data_get CLK_get synchronous get interface 20 Mixed-Clock FIFO: Block Level Initiates put operations Bus for data items Initiates get operations full synchronous put inteface req_put data_put CLK_put Controls put operations Mixed-Clock FIFO Bus for data items req_get valid_get empty data_get CLK_get synchronous get interface Controls get operations 21 Mixed-Clock FIFO: Block Level full synchronous put inteface req_put data_put CLK_put Mixed-Clock FIFO Indicates when FIFO full Indicates data items validity (always 1 in this design) req_get valid_get empty data_get CLK_get synchronous get interface Indicates when FIFO empty 22 Mixed-Clock FIFO: Architecture full req_put Full Detector Put Controller data_put CLK_put cell cell cell cell cell req_get valid_get empty Get Controller CLK_get data_get Empty Detector 23 Mixed-Clock FIFO: Cell Implementation CLK_put en_put req_put data_put ptok_out ptok_in En f_i e_i gtok_out REG SR En CLK_get gtok_in en_get valid data_get 24 Mixed-Clock FIFO: Cell Implementation CLK_put en_put req_put data_put ptok_out ptok_in En PUT INTERFACE f_i e_i REG SR GET INTERFACE gtok_out En CLK_get gtok_in en_get valid data_get 25 Synchronization: summary Resolving metastability implies latency Latency can be often hidden (FIFOs, Chelcea & Nowick) Clock frequencies can be estimated and clock edges predicted under the assumption of stable clocks (Chakraborty & Greenstreet) Pausible clocks are also possible (Yun & Donohue 1996) But still the nicest solutions are totally asynchronous As presented by Fulcrum Microsystems in the last lecture 26
