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TPS25942A, TPS25942L, TPS25944A, TPS25944L
SLVSCE9D – JUNE 2014 – REVISED OCTOBER 2017
TPS25942x/44x 2.7 V-18 V, 5-A eFuse Power MUX With Multiple Protection Modes
1 Features
3 Description
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The TPS25942, TPS25944 eFuse Power MUX is a
compact, feature rich power management device with
a full suite of protection functions. The wide operating
range allows control of many popular DC bus
voltages. Integrated back-to-back FETs provide
bidirectional current control making the device well
suited for power muxing and systems with multiple
power sources.
PART NUMBER
EN/UVLO
FLT
DMODE
PGTH
dVdT
IMON
GND
TPS25942x
TPS25944x
3.00 mm x 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet
(2) TPS2594xL = Latched, TPS2594xA = Auto Retry
C3
2V/div
To Load
PGOOD
OVP
WQFN (20)
Failover of V(MAIN) = 12 V to V(AUX) = 12.3 V
Using Diode Mode Control
OUT
RTOTAL =
42 m:
BODY SIZE (NOM)
TPS25944A
Simplified Schematic
IN
PACKAGE
TPS25942L
TPS25944L
Power Path Management
Redundant Power Supply Systems
PCIe cards, NICs and RAID Systems
USB Power Banks, Power MUXes
SSDs and HDDs
Tablets and Notebooks
Adapter Power Devices
PLCs, SS Relays and Fan Control
2.7 to 18 V
V(IN)
Device Information(1)
(2)
TPS25942A
2 Applications
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The TPS25942, TPS25944 monitor V(IN) and V(OUT) to
provide true reverse blocking from output when V(IN) <
(V(OUT) – 10 mV). The device can be configured to
assign Main/Auxiliary supply priority using the FLT
and DMODE pins.
C2
5V/div
•
Load, source and device protection are provided with
many programmable features. Thresholds for
undervoltage, overvoltage, overcurrent, dVo/dt ramp
rate, power good, and in-rush current protection are
all
programmable
to
suit
specific
system
requirements. For system status monitoring and
downstream load control, the device provides
PGOOD, FLT and precise current monitor output.
C4
500mA/div
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•
2.7 V to 18 V Operating Voltage, 20 V (Maximum)
42-mΩ RON (Typical)
0.6 A to 5.3 A Adjustable Current Limit (±8%)
IMON Current Indicator Output (±8%)
200-µA Operating IQ (Typical)
15-µA Disabled IQ (Typical)
±2% Overvoltage, Undervoltage Thresholds
Reverse Current Blocking
1-µs Reverse Voltage Shutoff
Programmable dVo/dt Control
Power Good and Fault Outputs
Two Overcurrent Fault Response Options
– TPS25942: I(LIMIT) with Thermal Shutdown
– TPS25944: 4 ms Fault Timer then Shutoff
–40°C to +125°C Junction Temperature Range
UL 2367 Recognized
– File No. 169910
– RILIM ≥ 20 kΩ (4.81 A Maximum)
UL60950 Safe during Single Point Failure
– Open-Short ILIM detection
C1
5V/div
1
ILIM
COUT = 150 mF, RL = 4 W
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
TPS25942A, TPS25942L, TPS25944A, TPS25944L
SLVSCE9D – JUNE 2014 – REVISED OCTOBER 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8
9
1
1
1
2
4
4
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Electrical Characteristics........................................... 7
Timing Requirements ................................................ 9
Typical Characteristics ............................................ 10
Parameter Measurement Information ................ 18
Detailed Description ............................................ 19
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
19
20
22
26
10 Application and Implementation........................ 29
10.1 Application Information.......................................... 29
10.2 Typical Application ................................................ 29
10.3 System Examples ................................................ 37
11 Power Supply Recommendations ..................... 44
11.1 Transient Protection .............................................. 44
11.2 Output Short-Circuit Measurements ..................... 45
12 Layout................................................................... 46
12.1 Layout Guidelines ................................................. 46
12.2 Layout Example .................................................... 47
13 Device and Documentation Support ................. 48
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
48
48
48
48
48
48
48
49
14 Mechanical, Packaging, and Orderable
Information ........................................................... 49
4 Revision History
Changes from Revision C (January 2017) to Revision D
•
Page
Added section 9.3.5 Reverse Current Protection to Feature Description ............................................................................ 25
Changes from Revision B (October 2017) to Revision C
•
Page
Changed internal ramp rate of 12 V/ms for output to 30 V/ms in the Hot Plug-In and In-Rush Current Control section..... 23
Changes from Revision A (March 2015) to Revision B
•
Page
Changed Figure 49: Added Logic Inversion ......................................................................................................................... 21
Changes from Original (June 2014) to Revision A
Page
•
Changed Features From: UL2367 Recognition Pending To: UL 2367 Recognized, RILIM ≥ 20 kΩ (4.81 A max), File
No. 169910 ............................................................................................................................................................................. 1
•
Changed text in the Description From: FLT and ENBLK pins To: FLT and DMODE pins..................................................... 1
•
Deleted Note "Product Preview" from the Device Information table ...................................................................................... 1
•
Changed Pin 1 From ENBLK To: DMODE throughout the data sheet .................................................................................. 4
•
Changed ENBLK To: DMODE in the Pin Functions table and updated the DESCRIPTION ................................................ 4
•
Moved the Storage Temperature From the Handling Ratings table To Absolute Maximum Ratings table .......................... 6
•
Changed the Handling Ratings table To: ESD Ratings table ................................................................................................ 6
•
Changed DIODE MODE INPUT (ENBLK): ACTIVE LOW To: DIODE MODE INPUT (DMODE): ACTIVE HIGH in the
Electrical Characteristics ........................................................................................................................................................ 7
•
Added Test Condition to I(LIM): "R(ILIM) = 20 kΩ" in the Electrical Characteristics .................................................................. 8
•
Changed Test Condition in I(LIM) From: "ENBLK = High; Diode Mode" To: "DMODE = High; Non-ideal Diode Mode"
in the Electrical Characteristics ............................................................................................................................................. 8
2
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Copyright © 2014–2017, Texas Instruments Incorporated
Product Folder Links: TPS25942A TPS25942L TPS25944A TPS25944L
TPS25942A, TPS25942L, TPS25944A, TPS25944L
www.ti.com
SLVSCE9D – JUNE 2014 – REVISED OCTOBER 2017
•
Changed "DIODE MODE INPUT: ACTIVE LOW (ENBLK)" To: DIODE MODE INPUT: ACTIVE HIGH (DMODE)" in
the Timing Requirements ...................................................................................................................................................... 9
•
Changed Figure 22............................................................................................................................................................... 12
•
Added condition R(ILIM) = 17.8 KΩ to Figure 39 and Figure 40 ............................................................................................ 15
•
Changed Figure 43. Added Figure 44, Figure 45, and Figure 46 ........................................................................................ 16
•
Changed Figure 48: ENBLK To: DMODE and Diode Mode To: Non-Ideal Diode Mode ..................................................... 20
•
Changed Figure 49: ENBLK To: DMODE and Diode Mode To Non-Ideal Diode Mode ...................................................... 21
•
Changed Equation 6 to include I(IMON_OS).............................................................................................................................. 25
•
Change text in Diode Mode From:" ENBLK...active low terminal" To: "DMODE ...active high terminal"............................. 26
•
Changed text in the last sentence of Diode Mode From: "In this mode, the overload current..." To:"In this mode, the
circuit breaker functionality.."................................................................................................................................................ 26
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Added the NOTE to Application and Implementation .......................................................................................................... 29
•
Added Note A to Figure 60 .................................................................................................................................................. 33
•
Changed Equation 37 From: V(IN) x I(LOAD) To: V(IN) + I(LOAD) ................................................................................................. 44
Copyright © 2014–2017, Texas Instruments Incorporated
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Product Folder Links: TPS25942A TPS25942L TPS25944A TPS25944L
3
TPS25942A, TPS25942L, TPS25944A, TPS25944L
SLVSCE9D – JUNE 2014 – REVISED OCTOBER 2017
www.ti.com
5 Device Comparison Table
DEVICE
TJ
OPERATION (1)
TYPE
Current limiter
Auto retry
Current limiter
Latched
Circuit breaker
Auto retry
Circuit breaker
Latched
TPS25942A
TPS25942L
–40°C to +125°C
TPS25944A
TPS25944L
(1)
See the Operational Differences Between the TPS25942 and TPS25944 section for detailed information.
6 Pin Configuration and Functions
RVC Package
20-Pin WQFN
Top View
FLT
IMON
dVdT
ILIM
20
19
18
17
DMODE
1
16
GND
PGOOD
2
15
OVP
PGTH
3
14
EN
OUT
4
13
IN
12
IN
11
IN
OUT
5
OUT
6
Thermal
Pad
8
9
OUT
OUT
IN
10 IN
7
Pin Functions
PIN
NO.
I/O
NAME
DESCRIPTION
1
DMODE
I
Diode Mode control pin. A high at this pin activates the non-ideal diode mode
2
PGOOD
O
Active High. A high indicates PGTH has crossed the threshold value. It is an open drain
output
3
PGTH
I
Positive input of PGOOD comparator
OUT
O
Power output of the device
IN
I
Power input and supply voltage
14
EN/UVLO
I
Input for setting programmable undervoltage lockout threshold. An undervoltage event opens
internal FET and assert FLT to indicate power-failure. When pulled to GND, resets the fault
latch in TPS25942L, TPS25944L
15
OVP
I
Input for setting programmable overvoltage protection threshold. An overvoltage event opens
the internal FET and assert FLT to indicate overvoltage
16
GND
—
4
5
6
7
8
9
10
11
12
13
4
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Ground
Copyright © 2014–2017, Texas Instruments Incorporated
Product Folder Links: TPS25942A TPS25942L TPS25944A TPS25944L
TPS25942A, TPS25942L, TPS25944A, TPS25944L
www.ti.com
SLVSCE9D – JUNE 2014 – REVISED OCTOBER 2017
Pin Functions (continued)
PIN
NO.
I/O
NAME
DESCRIPTION
17
ILIM
I/O
A resistor from this pin to GND sets the overload and short-circuit current limit
18
dVdT
I/O
A capacitor from this pin to GND sets the ramp rate of output voltage
19
IMON
O
This pin sources a scaled down ratio of current through the internal FET. A resistor from this
pin to GND converts current to proportional voltage, used as analog current monitor
20
FLT
O
Fault event indicator, goes low to indicate fault condition due to undervoltage, pvervoltage,
reverse voltage, circuit breaker timeout (TPS25944 only) and thermal shutdown events. It is
an open drain output
—
PowerPADTM
—
The GND terminal must be connected to the exposed PowerPAD. This PowerPAD must be
connected to a PCB ground plane using multiple vias for good thermal performance
Copyright © 2014–2017, Texas Instruments Incorporated
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5
TPS25942A, TPS25942L, TPS25944A, TPS25944L
SLVSCE9D – JUNE 2014 – REVISED OCTOBER 2017
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)
(1)
MIN
MAX
–0.3
20
dVdT, ILIM
–0.3
3.6
IMON
–0.3
7
IN, OUT, PGTH, PGOOD, EN, OVP, DMODE, FLT
IN (10-ms transient)
Input voltage
Sink current
PGOOD, FLT, dVdT
Source current
dVdT, ILIM, IMON
UNIT
22
V
10
mA
Internally Limited
See the Thermal
Information
Continuous power dissipation
TJ
Maximum junction temperature
–40
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
VESD
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001s (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM MAX
2.7
18
EN, OVP, DMODE, OUT, PGTH, PGOOD, FLT
0
18
dVdT, ILIM
0
3
IN
Input voltage
IMON
Resistance
External capacitance
TJ
ILIM
IMON
0
6
16.9
150
1
OUT
0.1
–40
V
kΩ
µF
dVdT
Operating junction temperature
UNIT
25
470
nF
125
°C
7.4 Thermal Information
TPS25942
TPS25944
THERMAL METRIC (1)
RVC (WQFN)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
38.1
°C/W
RθJCtop
Junction-to-case (top) thermal resistance
40.5
°C/W
RθJB
Junction-to-board thermal resistance
13.6
°C/W
ψJT
Junction-to-top characterization parameter
0.6
°C/W
ψJB
Junction-to-board characterization parameter
13.7
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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TPS25942A, TPS25942L, TPS25944A, TPS25944L
www.ti.com
SLVSCE9D – JUNE 2014 – REVISED OCTOBER 2017
Thermal Information (continued)
THERMAL METRIC
TPS25942
TPS25944
(1)
UNIT
RVC (WQFN)
20 PINS
RθJCbot
Junction-to-case (bottom) thermal resistance
3.4
°C/W
7.5 Electrical Characteristics
Conditions are –40°C ≤ TJ = TA ≤ +125°C, 2.7 V ≤ V(IN) ≤ 18 V, V(EN/UVLO) = 2 V, V(OVP) = V(DMODE) = V(PGTH) = 0 V, R(ILIM) = 150
kΩ, C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. Positive current into terminals. All voltages referenced to
GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE AND INTERNAL UNDERVOLTAGE LOCKOUT
V(IN)
Operating input voltage
2.7
V(UVR)
Internal UVLO threshold, rising
2.2
2.3
2.4
V
V(UVRhys)
Internal UVLO hysteresis
105
116
125
mV
V(EN/UVLO) = 2 V, V(IN) = 3 V
140
210
300
IQ(ON)
Supply current, enabled
V(EN/UVLO) = 2 V, V(IN) = 12 V
140
199
260
V(EN/UVLO) = 2 V, V(IN) = 18 V
140
202
270
V(EN/UVLO) = 0 V, V(IN) = 3 V
4
8.6
15
V(EN/UVLO) = 0 V, V(IN) = 12 V
6
15
20
V(EN/UVLO) = 0 V, V(IN) = 18 V
8
18.5
25
IQ(OFF)
Supply current, disabled
18
V
µA
µA
ENABLE AND UNDERVOLTAGE LOCKOUT (EN/UVLO) INPUT
V(ENR)
EN/UVLO threshold voltage, rising
0.97
0.99
1.01
V
V(ENF)
EN/UVLO threshold voltage, falling
0.9
0.92
0.94
V
V(SHUTF)
EN threshold voltage for Low IQ
shutdown, falling
0.3
0.47
0.63
V
V(SHUTFhys)
EN hysteresis for low IQ shutdown,
hysteresis (1)
IEN
EN input leakage current
66
0 V ≤ V(EN/UVLO) ≤ 18 V
mV
–100
0
100
nA
OVER VOLTAGE PROTECTION (OVP) INPUT
V(OVPR)
Overvoltage threshold voltage,
rising
0.97
0.99
1.01
V
V(OVPF)
Overvoltage threshold voltage,
falling
0.9
0.92
0.94
V
I(OVP)
OVP input leakage current
–100
0
100
nA
DMODE threshold voltage, rising
1.6
1.85
2
V
DMODE threshold voltage, falling
0.8
0.96
1.1
V
0.6
1
1.25
µA
0 V ≤ V(OVP) ≤ 5 V
DIODE MODE INPUT (DMODE)—ACTIVE HIGH
V(DMODE)
I(DMODE)
DMODE input leakage current
0.2 V ≤ V(DMODE) ≤ 18 V
OUTPUT RAMP CONTROL (dVdT)
I(dVdT)
dVdT charging current
V(dVdT) = 0 V
R(dVdT)
dVdT discharging resistance
EN/UVLO = 0 V, I(dVdT) = 10 mA sinking
V(dVdTmax)
dVdT maximum capacitor voltage
GAIN(dVdT)
dVdT to OUT gain
ΔV(OUT)/ΔV(dVdT)
0.85
1
1.15
µA
16
24
Ω
2.6
2.88
3.1
11.65
11.9
12.05
V
V/V
CURRENT LIMIT PROGRAMMING (ILIM)
V(ILIM)
(1)
ILIM bias voltage
0.87
V
These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
Copyright © 2014–2017, Texas Instruments Incorporated
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TPS25942A, TPS25942L, TPS25944A, TPS25944L
SLVSCE9D – JUNE 2014 – REVISED OCTOBER 2017
www.ti.com
Electrical Characteristics (continued)
Conditions are –40°C ≤ TJ = TA ≤ +125°C, 2.7 V ≤ V(IN) ≤ 18 V, V(EN/UVLO) = 2 V, V(OVP) = V(DMODE) = V(PGTH) = 0 V, R(ILIM) = 150
kΩ, C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. Positive current into terminals. All voltages referenced to
GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.53
0.58
0.63
R(ILIM) = 88.7 kΩ, (V(IN) – V(OUT)) = 1 V
0.9
0.99
1.07
R(ILIM) = 42.2 kΩ, (V(IN) – V(OUT)) = 1 V
1.92
2.08
2.25
R(ILIM) = 24.9 kΩ, (V(IN) – V(OUT)) = 1 V
3.25
3.53
3.81
R(ILIM) = 20 kΩ, (V(IN) – V(OUT)) = 1 V
4.09
4.45
4.81
R(ILIM) = 16.9 kΩ, (V(IN) – V(OUT)) = 1 V
4.78
5.2
5.62
R(ILIM) = OPEN, open resistor current limit (single point
failure test: UL60950)
0.35
0.45
0.55
R(ILIM) = SHORT, shorted resistor current limit (single point
failure test: UL60950)
0.55
0.67
0.8
R(ILIM) = 150 kΩ, (V(IN) – V(OUT)) = 1 V
Current limit
I(LIM) for TPS25942 (2)
I(FAULT) forTPS25944 (2) (3)
I(LIM)
Short-circuit current limit
R(ILIM) = 42.2 kΩ, V(VIN) = 12 V, (V(IN) – V(OUT)) = 5 V
1.91
2.07
2.24
R(ILIM) = 24.9 kΩ, V(VIN) = 12 V, (V(IN) – V(OUT)) = 5 V
3.21
3.49
3.77
R(ILIM) = 16.9 kΩ, V(VIN) = 12 V, (V(IN) – V(OUT)) = 5 V,
–40°C ≤ TJ ≤ +85°C
4.7
5.11
5.52
A
1.5 ×
I(LIM) +
0.375
Fast-trip comparator threshold (1) (2)
I(FASTRIP)
A
0.5 ×
I(LIM)
DMODE = High; Non-ideal diode mode (1)
I(OS)
UNIT
A
CURRENT MONITOR OUTPUT (IMON)
GAIN(IMON)
Gain factor I(IMON):I(OUT)
1 A ≤ I(OUT) ≤ 5 A
47.78
52.3
57.23
1 A ≤ I(OUT) ≤ 5 A, TJ = 25°C
34
42
49
1 A ≤ I(OUT) ≤ 5 A, –40°C ≤ TJ ≤ +85°C
26
42
58
1 A ≤ I(OUT) ≤ 5 A, –40°C ≤ TJ ≤ +125°C
26
42
64
V(IN) = 18 V, V(EN/UVLO) = 0 V, V(OUT) = 0 V (sourcing)
–2
0
2
V(IN) = 2.7 V, V(EN/UVLO) = 0 V, V(OUT) = 18 V (sinking)
6
13
20
µA/A
MOSFET—POWER SWITCH
RON
IN to OUT - ON resistance
mΩ
PASS FET OUTPUT (OUT)
Ilkg(OUT)
OUT leakage current in off state
µA
V(REVTH)
V(IN) – V(OUT) threshold for reverse
protection comparator, falling
–15
–9.3
–3
mV
V(FWDTH)
V(IN) – V(OUT) threshold for reverse
protection comparator, rising
86
100
114
mV
FAULT FLAG (FLT)—ACTIVE LOW
R(FLT)
FLT internal pull-down resistance
V(OVP) = 2 V, I(FLT) = 5 mA sinking
10
18
30
Ω
I(FLT)
FLT input leakage current
0 V ≤ V(FLT) ≤ 18 V
–1
0
1
µA
V
POSITIVE INPUT for POWER-GOOD COMPARATOR (PGTH)
V(PGTHR)
PGTH threshold voltage, rising
0.97
0.99
1.01
V(PGTHF)
PGTH threshold voltage, falling
0.9
0.92
0.94
V
I(PGTH)
PGTH input leakage current
–100
0
100
nA
0 V ≤ V(PGTH) ≤ 18 V
POWER-GOOD COMPARATOR OUTPUT (PGOOD): ACTIVE HIGH
R(PGOOD)
PGOOD internal pull-down
resistance
V(PGTH) = 0V, I(PGOOD) = 5 mA sinking
10
20
35
Ω
I(PGOOD)
PGOOD input leakage current
0 V ≤ V(PGOOD) ≤ 18 V
–1
0
1
µA
THERMAL SHUT DOWN (TSD)
T(TSD)
TSD threshold (1)
160
°C
T(TSDhys)
TSD hysteresis (1)
12
°C
Thermal fault: (latched or auto-retry)
(2)
(3)
8
TPS25942L, TPS25944L
Latched
TPS25942A, TPS25944A
Auto-retry
Pulse-testing techniques maintain junction temperature close to ambient temperature. Thermal effects must be taken into account
separately.
The TPS25942 limits current to the programmed I(LIM) level. TPS25944 does not limit current but runs the fault timer when I(LOAD) >
I(LIM).
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TPS25942A, TPS25942L, TPS25944A, TPS25944L
www.ti.com
SLVSCE9D – JUNE 2014 – REVISED OCTOBER 2017
7.6 Timing Requirements
Conditions are –40°C ≤ TJ = TA ≤ +125°C, 2.7 V ≤ V(IN) ≤ 18 V, V(EN/UVLO) = 2 V, V(OVP) = V(DMODE) = V(PGTH) = 0 V, R(ILIM) = 150
kΩ, C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. Positive current into terminals. All voltages referenced to
GND (unless otherwise noted). See Figure 47 for timing diagrams.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ENABLE AND UVLO INPUT
tON(dly)
tOFF(dly)
EN/UVLO ↑ (100 mV above V(ENR)) to V(OUT) = 100 mV,
C(dVdT) < 0.8 nF
220
µs
EN/UVLO ↑ (100 mV above V(ENR)) to V(OUT) = 100 mV,
C(dVdT) ≥ 0.8 nF, see , [C(dVdT) in nF]
100 + 150
× C(dVdT)
µs
EN/UVLO ↓ (100 mV below V(ENF)) to FLT↓
2
µs
OVP↑ (100 mV above V(OVPR)) to FLT↓
2
µs
DMODE turnon delay
DMODE↓ to (V(IN) – V(OUT)) ≤ 200 mV, with 1 A resistive load at
OUT
2
µs
DMODE turnoff delay
DMODE↑ to (V(IN) – V(OUT)) > 200 mV, 1 A resistive load at OUT
220
ns
EN turnon delay
EN turnoff delay
OVERVOLTAGE PROTECTION INPUT (OVP)
tOVP(dly)
OVP disable delay
DIODE MODE INPUT: ACTIVE HIGH (DMODE)
tDMODE
OUTPUT RAMP CONTROL (dVdT)
EN/UVLO ↑ to V(OUT) = 4.5 V, with C(dVdT) = open
tdVdT
EN/UVLO ↑ to V(OUT) = 11 V, with C(dVdT) = open
Output ramp time
0.12
0.25
0.37
EN/UVLO↑ to V(OUT) = 11 V, with C(dVdT) = 1 nF
0.97
I(OUT) > I(FASTRIP)
200
0.5
ms
CURRENT LIMIT
tFASTRIP(dly)
Fast-trip comparator delay
ns
REVERSE PROTECTION COMPARATOR
tREV(dly)
(V(IN) – V(OUT))↓ (1 mV overdrive below V(REVTH)) to FLT↓
Reverse protection
comparator delay
tFWD(dly)
10
(V(IN) – V(OUT))↓ (10 mV overdrive below V(REVTH)) to FLT↓
1
(V(IN) – V(OUT))↑ (10 mV overdrive above V(FWDTH)) to FLT↑
3.1
µs
POWER-GOOD COMPARATOR OUTPUT (PGOOD): ACTIVE HIGH
tPGOODR
TPS25942: rising edge
PGOOD delay (de-glitch) time
tPGOODF
0.42
TPS25944: rising edge
0.54
0.66
4
TPS25942 and TPS25944: falling edge
ms
10
µs
FAULT FLAG (FLT)
tCB(dly)
FLT assertion delay in circuit
breaker mode
TPS25944 only; delay from I(OUT) > I(LIM) to FLT↓ (and internal
FET turned off)
4
ms
tCB(Retrydly)
Retry delay in circuit breaker
mode
TPS25944A only; circuit breaker fault asserted, delay from to
FLT↓ to FLT↑ edge
128
ms
TPS25942A and TPS25944A only
128
ms
THERMAL SHUT DOWN (TSD)
Retry delay in TSD
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7.7 Typical Characteristics
Conditions are –40°C ≤ TJ = TA ≤ +125°C, V(IN) = 12 V, V(EN/UVLO) = 2 V, V(OVP) = V(DMODE) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ,
C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. (unless stated otherwise)
300
2.30
2.25
Supply Current, IQ(ON) (PA)
Internal UVLO Threshold Voltage (V)
2.35
R
VUVLO
(UVR)
VUVLO
(UVF) F
2.20
2.15
250
200
150
100
TA = -40qC
TA = 25qC
TA = 85qC
TA = 125qC
50
2.10
±50
±20
10
40
70
100
0
130
0
Temperature (oC)
Figure 1. Internal UVLO Threshold Voltage vs Temperature
EN/UVLO Threshold Voltage (V)
Supply Current, IQ(OFF) (PA)
15
20
D002
1.00
20
15
10
TA = -40qC
TA = 25qC
TA = 85qC
TA = 125qC
5
0.98
0.96
0
5
10
Input Voltage (V)
15
EN Ris
V(ENR)
V(ENF)
EN Fall
0.94
0.92
0.90
0
±50
20
±20
10
40
70
100
130
Temperature (oC)
C014
D003
Figure 4. EN Threshold Voltage vs Temperature
Figure 3. Input Supply Current vs Supply Voltage at
Shutdown
1.00
0.98
0.96
OVP
Rising
V(OVPR)
V
(OVPF)
OVP
Falling
0.94
0.92
PGTH Threshold Voltage (V)
1.00
OVP Threshold Voltage (V)
10
Input Voltage (V)
Figure 2. Input Supply Current vs Supply Voltage During
Normal Operation
25
0.98
0.96
PGTH
Rising
V
(PGTHR)
V
PGTH
(PGHTF)Falling
0.94
0.92
0.90
0.90
±50
±20
10
40
Temperature (oC)
70
100
130
C014
Figure 5. OVP Threshold Voltage vs Temperature
10
5
C014
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±50
±20
10
40
Temperature (oC)
70
100
130
C014
Figure 6. PGTH Threshold Voltage vs Temperature
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Typical Characteristics (continued)
0.60
300
EN
Rising
V(SHUTR)
Enalbe Turn ON delay tON(dly) (µs)
EN Threshold Voltage for Low IQ Mode (V)
Conditions are –40°C ≤ TJ = TA ≤ +125°C, V(IN) = 12 V, V(EN/UVLO) = 2 V, V(OVP) = V(DMODE) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ,
C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. (unless stated otherwise)
V(SHUTF)
EN
Falling
0.55
0.50
0.45
250
200
150
100
0.40
50
±50
±20
10
40
70
100
130
Temperature (oC)
±50
40
70
100
130
C014
Figure 8. Enable Turnon Delay vs Temperature
3.0
OVP Disable Delay, tOVP(dly) (Ps)
3.0
Enalbe Turn OFF Delay tOFF(dly) (µs)
10
Temperature (oC)
Figure 7. EN Threshold Voltage for Low IQ Mode vs
Temperature
2.6
2.2
1.8
1.4
2.6
2.2
1.8
1.4
1.0
1.0
±50
±20
10
40
70
100
130
Temperature (oC)
±50
10
40
70
100
130
Temperature (oC)
Figure 9. Enable Turnoff Delay vs Temperature
C014
Figure 10. OVP Disable Delay vs Temperature
1.7
1.5
V(DMODER)
V(DMODEF)
1.3
1.1
-20
10
40
70
Temperature (qC)
100
130
Figure 11. DMODE Threshold Voltage vs Temperature
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DMODE Pulldown Current, I(DMODE) (PA)
1.2
1.9
0.9
-50
±20
C014
2.1
DMODE Threshold Voltage (V)
±20
C014
1.1
1.0
0.9
-50
-20
10
40
70
Temperature (qC)
100
130
Figure 12. DMODE Pulldown Current vs Temperature
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Typical Characteristics (continued)
Conditions are –40°C ≤ TJ = TA ≤ +125°C, V(IN) = 12 V, V(EN/UVLO) = 2 V, V(OVP) = V(DMODE) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ,
C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. (unless stated otherwise)
1000
11.90
Output Ramp Time, t(dVdT) (ms)
11.89
Gain(dVdT)
11.88
11.87
11.86
11.85
11.84
11.83
100
10
1
0
11.82
±50
±20
10
40
70
100
Temperature (oC)
1
130
Figure 13. GAIN(dVdT) vs Temperature
Accuracy (%)
(Process, Voltage, Temperature)
Current Limit, I(LIM) (A)
9.0
8.5
8.0
7.5
10
100
R(ILIM) Resistor (k:)
0
1
2
3
4
5
6
Current Limit(A)
C014
C014
Figure 16. Current Limit Accuracy vs Current Limit
Figure 15. Current Limit vs Current Limit Resistor
2%
6
150 kO
88.6 kO
42.4 kO
24.9 kO
16.9 kO
1.5%
I(LIM) (% Normalized)
5
Current Limit, I(LIM) (A)
C014
9.5
0
4
150 k:
88.6 k:
42.4 k:
24.9 k:
16.9 k:
2
1
1%
0.5%
0
-0.5%
-1%
-1.5%
0
50
Temperature (qC)
100
150
D017
Figure 17. Current Limit vs Temperature Across R(ILIM)
12
1000
Figure 14. Output Ramp Time vs C(dVdT)
1
0
-50
100
C(dVdT) (nF)
10
3
10
C014
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-2%
-50
0
50
Temperature (qC)
100
150
D018
Figure 18. Current Limit (% Normalized) vs Temperature
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SLVSCE9D – JUNE 2014 – REVISED OCTOBER 2017
Typical Characteristics (continued)
Conditions are –40°C ≤ TJ = TA ≤ +125°C, V(IN) = 12 V, V(EN/UVLO) = 2 V, V(OVP) = V(DMODE) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ,
C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. (unless stated otherwise)
0.5%
0.70
I(LIM) = 1 A
I(LIM) = 2.1 A
I(LIM) = 3.6 A
I(LIM) = 5.3 A
-0.5%
0.65
Current Limit, I(LIM) (A)
I(LIM) Normalized (%)
0
-1%
-1.5%
-2%
0.60
R(ILIM)
Short
R(ILIM) ==Short
R(ILIM) ==Open
R(ILIM)
Open
0.55
0.50
0.45
-2.5%
0.40
-3%
0
2
4
6
8
V(IN) - V(OUT) (V)
10
0
±50
12
50
100
150
Temperature (oC)
C014
D030
For I(LIM) = 5.3 A, device goes into thermal shutdown for
[V(IN) – V(OUT)] > 8 V
Figure 20. Current Limit for R(ILIM) = Open and Short vs
Temperature
Figure 19. Current Limit Normalized (%) vs V(IN) – V(OUT)
1.2
8
1.1
7
IMON Offset (PA)
Fast Trip Current, I(FASTTRIP) (A)
9
6
5
4
3
1
0.9
0.8
2
0.7
1
0
0
1
2
3
4
5
Current Limit I(LIM) (A)
6
0.6
-50
C014
Figure 21. Fast Trip Threshold vs Current Limit
10
40
70
Temperature (qC)
100
130
D022
Figure 22. IMON Offset vs Temperature
500
Current Monitor Output I(MON) (µA)
54.0
53.5
GAIN, I(MON) (µA/A)
-20
53.0
52.5
52.0
51.5
50
o 0C
= -40
TATA
= -40
C
o
TATA
= 25
= 25C 0C
o
TATA
= 85
= 85C 0C
o
TATA
= 125
= 125C 0C
5
51.0
±50
±20
10
40
70
100
Temperature (oC)
Figure 23. GAIN(IMON) vs Temperature
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130
C014
0.1
1.0
Output Current , IOUT (A)
10.0
C014
Figure 24. Current Monitor Output vs Output Current
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Typical Characteristics (continued)
Conditions are –40°C ≤ TJ = TA ≤ +125°C, V(IN) = 12 V, V(EN/UVLO) = 2 V, V(OVP) = V(DMODE) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ,
C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. (unless stated otherwise)
60
OUT Pin Leakage Current, Ilkg(out) (µA)
16
55
RON (m:)
50
45
40
1A
2A
3A
4A
5A
35
30
12
10
vout==00V
V(OUT)
V
8
V(OUT)
18V= 18 V
6
4
2
0
±2
25
-50
0
50
Temperature (qC)
100
±50
150
0
50
100
150
Temperature (oC)
C014
D025
Figure 26. OUT Leakage Current in Off State vs Temperature
Figure 25. RON vs Temperature Across Load Current
±9.0
102.0
±9.1
101.5
±9.2
101.0
V(FWDTH) (mV)
±9.3
V(REVTH) (mV)
14
±9.4
±9.5
±9.6
±9.7
100.5
100.0
99.5
99.0
±9.8
98.5
±9.9
98.0
±10.0
±50
0
50
100
Temperature (oC)
±50
150
Figure 27. V(REVTH) vs Temperature
50
100
150
C014
Figure 28. V(FWDTH) vs Temperature
100000
5.0
Thermal Shutdown Time (ms)
4.9
4.8
tCB(dly) (ms)
0
Temperature (oC)
C014
4.7
4.6
4.5
4.4
4.3
TA -40C
= -40oC
TA 25C
= 25oC
10000
TA 85C
= 85oC
TA 125C
= 125oC
1000
100
10
1
0.1
4.2
±50
0
50
Temperature (oC)
100
150
C014
1
10
100
Power Dissipation (W)
C014
Taken on 2-Layer board, 2oz.(0.08-mm thick) with GND plane
area: 14 cm2 (Top) and 20 cm2 (Bottom)
Figure 29. Circuit Breaker Timer Fault Assertion Delay vs
Temperature
14
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Figure 30. Thermal Shutdown Time vs Power Dissipation
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Typical Characteristics (continued)
Conditions are –40°C ≤ TJ = TA ≤ +125°C, V(IN) = 12 V, V(EN/UVLO) = 2 V, V(OVP) = V(DMODE) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ,
C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. (unless stated otherwise)
V(IN) = 4.5 V
V(IN) = 11 V
Figure 31. Turnon With Enable
Figure 32. Turnon and Turnoff With Enable
R(FLT) = 100 kΩ
R(FLT) = 100 kΩ
Figure 33. EN Turnon Delay : EN ↑ to Output Ramp ↑
V(IN) = 12 V
RL = 12 Ω
R(FLT) = 100 kΩ
Figure 35. OVP Turnoff Delay: OVP ↑ to Fault ↓
Copyright © 2014–2017, Texas Instruments Incorporated
Figure 34. EN Turnoff Delay : EN ↓ to Fault ↓
V(IN) = 12 V
RL = 12 Ω
R(FLT) = 100 kΩ
Figure 36. OVP Turnon Delay: OVP ↓ to Output Ramp ↑
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Typical Characteristics (continued)
Conditions are –40°C ≤ TJ = TA ≤ +125°C, V(IN) = 12 V, V(EN/UVLO) = 2 V, V(OVP) = V(DMODE) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ,
C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. (unless stated otherwise)
V(IN) = 12 V
RL = 12 Ω
R(FLT) = 100 kΩ
R(PGOOD) = 100 kΩ
V(IN) = 12 V
Figure 37. Power Good Delay (Rising)
V(IN) = 12 V
R(IMON) = 16.9 kΩ
R(FLT) = 100 kΩ
R(ILIM) = 17.8 KΩ
Figure 39. Hot-Short: Fast Trip Response and Current
Regulation
RL = 12 Ω
R(FLT) = 100 kΩ
R(PGOOD) = 100 kΩ
Figure 38. Power Good Delay (Falling)
V(IN) = 12 V
R(IMON) = 16.9 kΩ
R(FLT) = 100 kΩ
R(ILIM) = 17.8 KΩ
Figure 40. Hot-Short: Fast Trip Response (Zoomed)
Figure 42. Transition from Non-Ideal Diode Mode to Normal
Mode
Figure 41. Transition from Normal Mode to Non-Ideal Diode
Mode
16
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Typical Characteristics (continued)
Conditions are –40°C ≤ TJ = TA ≤ +125°C, V(IN) = 12 V, V(EN/UVLO) = 2 V, V(OVP) = V(DMODE) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ,
C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. (unless stated otherwise)
V(IN) = 12 V
RL = 3 Ω to 2 Ω
R(ILIM) = 17.8 KΩ
R(IMON) = 16.9 kΩ
R(FLT) = 100 kΩ
Figure 43. Overload: TPS25944A Circuit Break Function
V(IN) = 5 V
R(IMON) = 16.9 kΩ
R(FLT) = 100 kΩ
R(ILIM) = 17.8 KΩ
Figure 45. Hot Short Response: TPS25944A
Device Turns Off after the Fault Timer tCB(dly) (4 ms) Expires
Copyright © 2014–2017, Texas Instruments Incorporated
Figure 44. Overload: Zoomed In (First Cycle)
V(IN) = 12
V
R(IMON) =
16.9 kΩ
R(FLT) = 100 kΩ
R(ILIM) = 17.8 KΩ
Figure 46. Hot Short Response: TPS25944A
Device Turns Off When TJ > T(TSD) Before Timer Expires
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8 Parameter Measurement Information
V(OUT)
VEN
V(ENF)-0.1V
0.1V
VEN
FLT
V(ENR)+0.1V
0
10%
time
0
time
tON(dly)
tOFF(dly)
-20mV
V(IN)-V(OUT)
110mV
V(IN)-V(OUT)
90%
FLT
FLT
10%
0
time
tREV(dly)
I(FASTRIP)
0
tFWD(dly)
time
V(OVPR) + 0.1V
V(OVP)
I(LIM)
I(OUT)
FLT
10%
0
time
tFASTRIP(dly)
0
tOVP(dly)
time
Figure 47. Timing Diagrams
18
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9 Detailed Description
9.1 Overview
The TPS25942, TPS25944 is an eFuse Power Mux with integrated back-to-back FETs and enhanced built-in
protection circuitry. It provides robust protection for all systems and applications powered from 2.7 V to 18 V.
For hot-plug-in boards, the device provides hot-swap power management with in-rush current control and
programmable output ramp-rate. The device integrates overcurrent and short circuit protection. The precision
overcurrent limit helps to minimize over design of the input power supply, while the fast response short circuit
protection immediately isolates the load from input when a short circuit is detected. The device allows the user to
program the overcurrent limit threshold between 0.6 A and 5.3 A via an external resistor.
The device provides precise monitoring of voltage bus for brown-out and overvoltage conditions and asserts fault
for downstream system. Its overall threshold accuracy of 2% ensures tight supervision of bus, eliminating the
need for a separate supply voltage supervisor chip. The TPS25942, TPS25944 is designed to control redundant
power supply systems. The devices monitor V(IN) and V(OUT) to provide true reverse blocking from output when
reverse condition or input power fail condition is detected. Also, a pair of the TPS25942 or TPS25944 devices
can be configured to assign priority to the main power supply over the auxiliary power supply.
The additional features include:
•
•
•
•
•
•
Precise current monitor output for health monitoring of the system
Additional power good comparator with precision internal reference for output or any other rail voltage
monitoring
Electronic circuit breaker operation with overload timeout – TPS25944 only
Over temperature protection to safely shutdown in the event of an overcurrent event
De-glitched fault reporting for brown-out and overvoltage faults
A choice of latched or automatic restart mode
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9.2 Functional Block Diagram
9-13
4-8
+
0.99 V
0.92 V
OVP
15
0.99 V
0.92 V
DMODE
1
0.92 V
Current
Sense
19
SWEN
±
Gate Control Logic
Thermal TSD
Shutdown
Current Limit Amp
Fast-Trip Comp
±
Shutdown
1 µA
0.87 V
EN/
UVLO
+
±
Ramp Control
17
20
18
S
12x
16 Ÿ
GND
SET
UVLO
EN
TSD
R
CLR
Q
SWEN
18 Ÿ
2
Fault Latch
+
0.99 V
0.92 V
TPS25942A/L
±
dVdt
over
FLT
Q
UVLO
16
ILIM
Short Detect
1 µA
dVdt
IMON
Non-ideal Diode Mode
+
0.96 V
x52 µ
CP
REVERSE
OVP
OUT
42 PŸ
Charge
Pump
EN
±
+
+100 mV
+
EN/UVLO
±
±
2.18 V
14
UVLO
±
+
2.30 V
-10 mV
+
IN
PGOOD
0.5 ms
10 µs
20 Ÿ
3
PGTH
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Figure 48. TPS25942A/L Block Diagram
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Functional Block Diagram (continued)
9-13
4-8
+
0.99 V
0.92 V
OVP
15
0.99 V
0.92 V
DMODE
1
0.96 V
Current
Sense
19
SWEN
±
Thermal
Shutdown
Gate Control Logic
Current Limit Amp
Non-ideal Diode Mode
Fast-Trip Comp
±
Shutdown
1 µA
0.87 V
EN/
UVLO
dVdt
Ramp Control
17
20
16 Ÿ
EN
TSD
UVLO
16
0.99 V
0.92 V
TPS25942A/L
S
SET
R
CLR
FLT
Q
UVLO
Timer
(4 ms)
ILIM
Short Detect
12x
I(ILIM) > I(LIM) Timeout
GND
+
±
1 µA
18
IMON
TSD
+
1.85 V
x52 µ
CP
REVERSE
OVP
OUT
42 PŸ
Charge
Pump
EN
±
+
+100 mV
+
EN/UVLO
±
2.18 V
14
UVLO
±
±
+
2.30 V
-10 mV
+
IN
Q
SWEN
18 Ÿ
Fault Latch
2
+
4 ms
±
10 µs
PGOOD
20 Ÿ
3
PGTH
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Figure 49. TPS25944A/L Block Diagram
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9.3 Feature Description
9.3.1 Enable and Adjusting Undervoltage Lockout
The EN/UVLO pin controls the ON and OFF state of the internal FET. A voltage V(EN/UVLO) < V(ENF) on this pin
turns off the internal FET, thus disconnecting IN from OUT, while voltage below 0.6 V takes the device into
shutdown mode, with IQ less than 20 µA to ensure minimal power loss. Cycling EN/UVLO low and then back high
resets the TPS2594xL that has latched off due to a fault condition.
The internal de-glitch delay on EN/UVLO falling edge is kept low for quick detection of power failure. For
applications where a higher de-glitch delay on EN/UVLO is desired, or when the supply is particularly noisy, it is
recommended to use an external bypass capacitor from EN/UVLO terminal to GND.
The undervoltage lock out can be programmed by using an external resistor divider from supply IN terminal to
EN/UVLO terminal to GND as shown in Figure 50. When an undervoltage or input power fail event is detected,
the internal FET is quickly turned off, and FLT is asserted. If the Under-Voltage Lock-Out function is not needed,
the EN/UVLO terminal must be connected to the IN terminal. EN/UVLO terminal must not be left floating.
The device also implements internal undervoltage-lockout (UVLO) circuitry on the IN terminal. The device
disables when the IN terminal voltage falls below internal UVLO Threshold V(UVF). The internal UVLO threshold
has a hysteresis of 115 mV.
V(IN)
IN
TPS25942x/4x
R1
EN/UVLO
+
0.99V
EN
R2
0.92V
OVP
+
OVP
0.99V
R3
GND
0.92V
Figure 50. UVLO and OVP Thresholds Set By R1, R2 and R3
9.3.2 Overvoltage Protection (OVP)
The device incorporates circuit to protect system during overvoltage conditions. A resistor divider connected from
the supply to OVP terminal to GND (as shown in Figure 50) programs the overvoltage threshold. A voltage more
than V(OVPR) on OVP pin turns off the internal FET and protects the downstream load. This pin must be tied to
GND when not used.
9.3.3 Hot Plug-In and In-Rush Current Control
The device is designed to control the in-rush current upon insertion of a card into a live backplane or other "hot"
power source. This limits the voltage sag on the backplane’s supply voltage and prevents unintended resets of
the system power. A slew rate controlled start-up (dVdT) also helps to eliminate conductive and radiative
interferences. An external capacitor connected from the dVdT pin to GND defines the slew rate of the output
voltage at power-on (as shown in Figure 51). Equation governing slew rate at start-up is shown in Equation 1.
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Feature Description (continued)
TPS25942x/4x
1uA
dVdT
16:
C(dVdT)
SWEN
GND
Figure 51. Output Ramp Up Time tdVdT is Set by C(dVdT)
æ
C(dVdT) ö æ dV(OUT) ö
÷ x ç
÷÷
ç GAIN(dVdT) ÷ ç
dt
ø
è
ø è
I(dVdT) = ç
where
•
I(dVdT) = 1 µA (typical)
dV(OUT)
•
•
= Desired output slew rate
GAIN(dVdT) = dVdT to OUT gain = 12
dt
(1)
The total ramp time (tdVdT) of V(OUT) for 0 to V(IN) can be calculated using Equation 2.
tdVdT = 8.3 x 104 x V(IN) x C(dVdT)
(2)
The inrush current, I(INRUSH) can be calculated as shown in Equation 3.
I(INRUSH) = C(OUT) x V(IN) / tdVdT.
(3)
The dVdT pin can be left floating to obtain a predetermined slew rate (tdVdT) on the output. When terminal is left
floating, the device sets an internal ramp rate of 30 V/ms for output (V(OUT)) ramp.
Figure 61 and Figure 62 illustrate the inrush current control behavior of the TPS25942, TPS25944. For systems
where load is present during start-up, the current never exceeds the overcurrent limit set by R(ILIM) resistor for the
application. For defining appropriate charging time/rate under different load conditions, see the Setting Output
Voltage Ramp Time (tdVdT) section.
9.3.4 Overload and Short Circuit Protection
The device monitors load current by sensing the voltage across the internal sense resistor. The FET current is
monitored at both the start-up and during normal operation. During overload events, the device keeps the over
current limited to the overcurrent limit (I(LIM)) programmed by R(ILIM) resistor as shown in Equation 4.
I(LIM) =
89
R(ILIM)
where
•
•
I(LIM) is overload current limit in Ampere.
R(ILIM) is the current limit resistor in kΩ
(4)
The device incorporates two distinct levels: an overcurrent-limit (I(LIM)) and a fast-trip threshold (I(FASTRIP)). The
illustration of fast trip and current limit operation is shown in Figure 52.
Since the bias current on ILIM pin directly controls the current-limiting behavior of the device, the PCB routing of
this node must be kept away from any noisy (switching) signals.
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Feature Description (continued)
9.3.4.1 Overload Protection
During overload conditions, the internal current-limit amplifier in the TPS25942 regulates the output current to
I(LIM). The output voltage droops during current regulation, resulting in increased device power dissipation. If the
device junction temperature reaches the thermal shutdown threshold (T(TSD)), the internal FET is turned off. Once
in thermal shutdown, The TPS25942L and 44L version stays latched off, whereas the TPS25942A and 44A
commences an auto-retry cycle 128 ms after TJ < [T(TSD) – 12°C]. During thermal shutdown, the fault pin FLT
pulls low to signal a fault condition. Figure 65 and Figure 66 illustrate the behavior of the system for overload
conditions in the TPS25942.
The TPS25944 allows the overload current to flow through the device until I(LOAD) < I(FASTRIP). It starts the timer
when I(LIM) < I(LOAD) < I(FASTRIP), and once the timer exceeds tCB(dly), the internal FET is turned off and FLT is
asserted.
9.3.4.2 Short Circuit Protection
During a transient short circuit event, the current through the device increases very rapidly. As current-limit
amplifier cannot respond quickly to this event due to its limited bandwidth, the device incorporates a fast-trip
comparator, with a threshold I(FASTRIP). This comparator shuts down the pass device within 1 µs, when the current
through internal FET exceeds I(FASTRIP) (I(OUT) > I(FASTRIP)), and terminates the rapid short-circuit peak current. The
trip threshold is set to more than 50% of the programmed overload current limit (I(FASTRIP) = 1.5 × I(LIM) + 0.375).
The fast-trip circuit holds the internal FET off for only a few microseconds, after which the device turns back on
slowly, allowing the current-limit loop to regulate the output current to I(LIM). Then, device behaves similar to
overload condition. Figure 67 through Figure 69 illustrate the behavior of the system when the current exceeds
the fast-trip threshold.
9.3.4.3 Start-Up With Short on Output
During start-up with short, the device limits the current to I(LIM) and behaves similar to the overload condition
afterwards. Figure 70 and Figure 71 illustrate the behavior of the device for start-up with short on the output. This
feature helps in quick isolation of the fault and hence ensures stability of the DC bus.
9.3.4.4 Constant Current Limit Behavior During Overcurrent Faults
If during current limit, power dissipation of the internal FET PD = (V(IN) – V(OUT)) × I(OUT)] exceeds 10 W, there is
an approximately 0% to 5% thermal fold back in the current limit value so that I(LIM) drops to IOS. Eventually, the
device shuts down due to over temperature.
Current Limit
I(FASTRIP)
I(FASTRIP) = 1.5 x I(LIM) + 0.375
Thermal Foldback
0-5%
I(LIM)
IOS
Figure 52. Fast-Trip Current
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Feature Description (continued)
9.3.5 Reverse Current Protection
A fast reverse comparator controls the internal FET and turns off the FET whenever the output voltage V(OUT)
exceeds the input voltage V(IN) by 10 mV (typical) for 1 μs (typical). This prevents damage to the devices on the
input side of the TPS2594xx by preventing significant current from sinking into the input side. However, a reverse
current of (V(OUT) - V(IN))/ RON) should flow from the output to the input to establish reverse voltage V(REVTH) of
–10 mV across the device. The typical value of reverse current, needed for reverse voltage detection is –10 mV/
42 mΩ = –238 mA
In power muxing applications, the reverse current magnitude I(REV) depends on the slew-rate of the output
voltage V(OUT) and the system input capacitance CIN as shown in Equation 5.
I (REV )
§ dV
·
C IN u ¨ (OUT) ¸
© dt ¹
(5)
For example, if the ramp rate of the output voltage is set at 10 mV/ μs then the required input capacitance CIN to
achieve reverse current greater than 238 mA is 23.8 µF. Considering tolerance of ±10% in capacitance and a
standard value, capacitor of 33 µF should be used as CIN in this case.
9.3.6 FAULT Response
The FLT open-drain output is asserted (active low) during undervoltage, overvoltage, reverse voltage-current and
thermal shutdown conditions. Additionally, in the TPS25944, the FLT is asserted when overload condition exists
for more than the fault time period (tCB(dly)). The FLT signal remains asserted until the fault condition is removed
and the device resumes normal operation. The device is designed to eliminate false fault reporting by using an
internal "de-glitch" circuit for undervoltage and overvoltage (2.2-µs typical) conditions without the need for
external circuitry. This ensures that fault is not accidentally asserted during transients on input bus.
Connect FLT with a pull up resistor to Input or Output voltage rail. FLT may be left open or tied to ground when
not used. V(IN) falling below V(UVF) = 2.1 V resets FLT.
9.3.7 Current Monitoring
The current source at IMON terminal is configured to be proportional to the current flowing from IN to OUT. This
current can be converted to a voltage using a resistor R(IMON) from IMON terminal to GND terminal. This voltage,
computed using Equation 7, can be used as a means of monitoring current flow through the system.
The maximum voltage range for monitoring the current (V(IMONmax)) is limited to minimum([V(IN) – 2.2 V], 6 V) to
ensure linear output. This puts limitation on maximum value of R(IMON) resistor and is determined by Equation 6.
R(IMONmax) =
minimum (V(IN) - 2.2, 6)
1.6 x I(LIM) x GAIN(IMON)
(6)
The output voltage at IMON terminal is calculated from Equation 7.
V(IMON) = éëI(OUT) x GAIN(IMON) + I(IMON_OS) ùû x R(IMON)
where
•
•
•
GAIN(IMON) = Gain factor I(IMON):I(OUT) = 52 µA/A
I(OUT) = Load current
I(IMON_OS) = 0.8 µA (typical)
(7)
This pin must not have a bypass capacitor to avoid delay in the current monitoring information.
The voltage at IMON pin can be digitized using an ADC (such as ADS1100, SBAS239) to read the current
monitor information over an I2C bus.
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Feature Description (continued)
9.3.8 Power Good Comparator
The devices incorporate a Power Good comparator for co-ordination of status to downstream DC-DC converters
or system monitoring circuits. The comparator has an internal reference of V(PGTHR) = 0.99 V at negative terminal
and positive terminal PGTH can be utilized for monitoring of either input or output of the device. The comparator
output PGOOD is an open-drain active high signal, which can be used to indicate the status to downstream units.
PGOOD is asserted high when internal FET is fully enhanced and PGTH pin voltage is higher than internal
reference V(PGTHR).
The PGOOD signal has deglitch time incorporated to ensure that internal FET is fully enhanced before heavy
load is applied by downstream converters. Rising deglitch delay is determined by Equation 8.
tPGOOD(degl) = Maximum {(3.5 x 106 x C(dVdT)), tPGOODR}
(8)
Connect the PGOOD pin with a pull up resistor to Input or Output voltage rail. PGOOD may be left open or tied
to ground when not used.
9.3.9 IN, OUT and GND Pins
The device has multiple pins for input (IN) and output (OUT).
All IN pins must be connected together and to the power source. A ceramic bypass capacitor close to the device
from IN to GND is recommended to alleviate bus transients. The recommended operating voltage range is 2.7 V18 V.
Similarly all OUT pins must be connected together and to the load. V(OUT) in the ON condition, is calculated using
Equation 9.
V(OUT) = V(IN) - (RON × I(OUT) )
(9)
where, RON is the total ON resistance of the internal FET.
GND terminal is the most negative voltage in the circuit and is used as a reference for all voltage reference
unless otherwise specified.
9.3.10 Thermal Shutdown
The device has built-in over temperature shutdown circuitry designed to disable the internal FET, if the junction
temperature exceeds 160°C (typical). The TPS25942L, 44L version latches off the internal FET, whereas the
TPS25942A, 44A commences an auto-retry cycle 128 ms after TJ < [T(TSD) – 12°C]. During the thermal
shutdown, the fault pin FLT pulls low to signal a fault condition.
9.4 Device Functional Modes
9.4.1 Diode Mode
The device provides a Diode Mode, where the power path from IN to OUT acts as a non-ideal diode rather than
a FET, as shown in Figure 53. This mode is activated through DMODE terminal. This is an active high terminal
with internal pull-down. The terminal is useful in Power-Mux applications to switch over from master to slave
supplies and vice-versa smoothly, when two supplies are within a diode drop of each other. A high at this
terminal activates the non-ideal diode mode. In this mode, the circuit breaker functionality (TPS25944x) is
disabled and the overload current limit is set to 50 % of current limit determined by R(ILIM) resistor.
IN
OUT
IN
OUT
42m:
Figure 53. Diode Mode: IN to OUT Power Path
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Device Functional Modes (continued)
9.4.2 Shutdown Control
The internal FET and hence the load current can be remotely switched off by taking the UVLO pin below its 0.6 V
threshold with an open collector or open drain device as shown in Figure 54. The device quiescent current is
reduced to less than 20 µA in this state. Upon releasing the UVLO pin the device turns on with soft-start cycle.
V(IN)
IN
TPS25942x/4x
R1
EN/UVLO
from µC
+
0.99V
EN
R2
0.92V
GND
Figure 54. Shutdown Control
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Device Functional Modes (continued)
9.4.3 Operational Differences Between the TPS25942 and TPS25944
The TPS25942 and TPS25944 respond differently to overload and short circuit conditions. The operational
differences are explained in Table 1.
Table 1. Device Operational Differences
TPS25942
(Current Limiter)
Device
TPS25944
(Circuit Breaker)
Inrush ramp controlled by dVdT
Inrush ramp controlled by dVdT
Inrush limited to I(LIM) level as set by R(ILIM)
Inrush limited to I(LIM) level as set by R(ILIM)
Fault Timer runs when current is limited to I(LIM)
Start-up
Fault timer expires after tCB(dly) (4 ms) causing device
shutoff
If TJ > T(TSD) device shuts off
Device turns off if TJ > T(TSD) before timer expires
Current is limited to I(LIM) level as set by R(ILIM)
Current is allowed through the device if I(LOAD) <
I(FASTRIP)
Power dissipation increases as V(IN) – V(OUT) grows
Fault Timer runs when current goes above I(LIM)
Fault timer expires after tCB(dly) (4 ms) causing device
shutoff
Over current response
Short-circuit response
28
Device turns off when TJ > T(TSD)
Device turns off if TJ > T(TSD) before timer expires
‘L' Version remains off
‘L' Version remains off
'A' Version attempts restart 128 ms after TJ < [T(TSD)
–12°C]
'A' Version attempts restart 128 ms after TJ < [T(TSD) –
12°C]
Fast shut off when I(LOAD) > I(FASTRIP)
Fast shut off when I(LOAD) > I(FASTRIP)
Quick restart and current limited to I(LIM), follows
standard TPS25942 start-up
Quick restart and current limited to I(LIM), follows
standard TPS25944 start-up
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The device is a smart eFuse. It is typically used for Active ORing and Power Multiplexing applications. It operates
from 2.7 V to 18 V with programmable current limit, overvoltage and undervoltage protection. The device aids in
controlling the in-rush current and in seamless power path management of multiple voltage rails for systems such
as PCIe cards, Network and Graphic Cards and SSDs. The device also provides robust protection for multiple
faults on the sub-system rail.
The following design procedure can be used to select component values for the TPS25942, TPS25944.
Alternatively, the WEBENCH® software may be used to generate a complete design. The WEBENCH® software
uses an iterative design procedure and accesses a comprehensive database of components when generating a
design. Additionally, a spreadsheet design tool TPS25942_44 Design Calculator is available on web folder.
This section presents a simplified discussion of the design process.
10.2 Typical Application
IN1
2.7 to 18 V
R1
475kO
IN
CIN
0.1µF
(See Note A)
R2
16.7kO
from µC
42mO
R6
EN/UVLO
OVP
DMODE
IN2
A.
CdVdT
1.5nF
R7
COUT
100µF
Health
Monitor
Load Monitor
ILIM
GND
2.7 to 18 V
FLT
PGOOD
PGTH
IMON
R4
475kO
RILIM
TPS25942x 17.8kO
R5
47kO
RIMON
19.1kO
Common Bus
dVdT
R3
31.2kO
OUT
OUT
TPS25942 Circuit
for IN2 Rail
CIN: Optional and only for noise suppression.
Figure 55. Typical Application Schematics: Active ORing Configuration
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Typical Application (continued)
10.2.1 Design Requirements
Table 2 lists the TPS25942, TPS25944 design parameters.
Table 2. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage, V(IN)
12 V
Undervoltage lockout set point, V(UV)
10.8 V
Overvoltage protection set point , V(OV)
16.5 V
Load at start-up , RL(SU)
4.8 Ω
Current limit, I(LIM)
5A
Load capacitance , C(OUT)
100 µF
Maximum ambient temperatures , TA
85°C
10.2.2 Detailed Design Procedure
The following design procedure can be used to select component values for the TPS25942, TPS25944.
10.2.2.1 Step by Step Design Procedure
To
•
•
•
•
•
begin the design process a few parameters must be decided upon. The designer needs to know the following:
Normal input operation voltage
Maximum output capacitance
Maximum current Limit
Load during start-up
Maximum ambient temperature of operation
This design procedure below seeks to control the junction temperature of device under both static and transient
conditions by proper selection of output ramp-up time and associated support components. The designer can
adjust this procedure to fit the application and design criteria.
10.2.2.2 Programming the Current-Limit Threshold: R(ILIM) Selection
R(ILIM) sets the current limit. Using Equation 4.
R(ILIM) =
89
= 17.8kW
5
(10)
Choose the closest standard value: 17.8k, 1% standard value resistor.
10.2.2.3 Undervoltage Lockout and Overvoltage Set Point
The undervoltage lockout (UVLO) and overvoltage trip point are adjusted using the external voltage divider
network of R1, R2 and R3 as connected between IN, EN, OVP and GND pins of the TPS25942, TPS25944
devices. The values required for setting the undervoltage and overvoltage are calculated solving Equation 11 and
Equation 12.
V(OVPR) =
R3
x V(OV)
R1 + R2 + R3
where
•
V(OVPR) = OVP Threshold for rising voltage
(11)
R 2 + R3
V(ENR) =
x V(UV)
R1 + R2 + R3
where
•
V(ENR) = Enable threshold for rising voltage
(12)
For minimizing the input current drawn from the power supply {I(R123) = V(IN)/(R1 + R2 + R3)}, it is recommended to
use higher values of resistance for R1, R2 and R3.
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However, leakage currents due to external active components connected to the resistor string can add error to
these calculations. So, the resistor string current, I(R123) must be chosen to be 20x greater than the leakage
current expected.
From the device electrical specifications, V(OVPR) = 0.99 V and V(ENR) = 0.99 V. For design requirements, V(OV) is
16.5 V and V(UV) is 10.8 V. To solve the equation, first choose the value of R3 = 31.2 kΩ and use Equation 11 to
solve for (R1 + R2) = 488.8 kΩ. Use Equation 12 and value of (R1 + R2) to solve for R2 = 16.47 kΩ and finally R1=
472.33 kΩ.
Using the closest standard 1% resistor values gives R1 = 475 kΩ, R2 = 16.7 kΩ, and R3 = 31.2 kΩ.
The power fail threshold V(PFAIL) is detected on the falling edge of the power supply. The falling voltage threshold
is 7% lower than the rising voltage threshold, so for a set V(UV) the power fail voltage V(PFAIL) is given by
Equation 13.
V(PFAIL) = 0.93 x V(UV)
(13)
10.2.2.4 Programming Current Monitoring Resistor—RIMON
Voltage at IMON pin V(IMON) represents the voltage proportional to load current. This can be connected to an
ADC of the downstream system for health monitoring of the system. The R(IMON) need to be configured based on
the maximum input voltage range of the ADC used. R(IMON) is set using Equation 14.
R(IMON) =
V(IMONmax)
I(LIM) x 52 x 10-6
kW
(14)
For I(LIM) = 5 A, and considering the operating range of ADC from 0 V to 5 V, V(IMONmax) is 5 V and R(IMON) is
determined by Equation 15:
R(IMON) =
5
5 x 52 x 10-6
= 19.23 kW
(15)
Selecting R(IMON) value less than determined by Equation 15 ensures that ADC limits are not exceeded for
maximum value of load current.
If the IMON pin voltage is not being digitized with an ADC, R(IMON) can be selected to produce a 1V/1A voltage at
the IMON pin, using Equation 14.
Choose closest 1 % standard value: 19.1 kΩ.
If current monitoring up to I(FASTRIP) is desired, R(IMON) can be reduced by a factor of 1.6, as in Equation 6.
10.2.2.5 Setting Output Voltage Ramp Time (tdVdT)
For a successful design, the junction temperature of device must be kept below the absolute-maximum rating
during both dynamic (start-up) and steady state conditions. Dynamic power stresses often are an order of
magnitude greater than the static stresses, so it is important to determine the right start-up time and in-rush
current limit required with system capacitance to avoid thermal shutdown during start-up with and without load.
The ramp-up capacitor C(dVdT) needed is calculated considering the two possible cases:
10.2.2.5.1 Case1: Start-Up Without Load: Only Output Capacitance C(OUT) Draws Current During Start-Up
During start-up, as the output capacitor charges, the voltage difference across the internal FET decreases, and
the power dissipated decreases as well. Typical ramp-up of output voltage V(OUT) with inrush current limit of 1.2 A
and power dissipated in the device during start-up is shown in Figure 56. The average power dissipated in the
device during start-up is equal to area of triangular plot (red curve in Figure 57) averaged over tdVdT.
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16
Input Current (A)
Power Dissioation (W)
Output Voltage (V)
14
16
14
12
12
10
10
8
8
6
6
4
4
2
2
Output Voltage (V)
Input Current (A), Power Dissipation (W)
SLVSCE9D – JUNE 2014 – REVISED OCTOBER 2017
0
0
0
20
40
60
80
100
Start-Up Time, tdVdt (%)
V(IN) = 12 V
C(dVdT) = 1 nF
C(OUT) = 100 µF
Figure 56. Typical Start-Up Without Load
V(IN) = 12 V
C(dVdT) = 1 nF
C013
C(OUT) = 100 µF
Figure 57. PD(INRUSH) Due to Inrush Current
For the TPS25944, TPS25944 device, the inrush current is determined as shown in Equation 16.
I=C x
V(IN)
dV
=> I(INRUSH) = C(OUT) x
dT
t dVdT
(16)
Power dissipation during start-up is given by Equation 17.
PD(INRUSH) = 0.5 x V(IN) x I(INRUSH)
(17)
Equation 17 assumes that load does not draw any current until the output voltage has reached its final value.
10.2.2.5.2 Case 2: Start-Up With Load: Output Capacitance C(OUT) and Load Draws Current During Start-Up
When load draws current during the turn-on sequence, there is additional power dissipated. Considering a
resistive load RL(SU) during start-up, load current ramps up proportionally with increase in output voltage during
tdVdT time. Typical ramp-up of output voltage, load current and power dissipated in the device is shown in
Figure 58 and power dissipation with respect to time is plotted in Figure 59. The additional power dissipation
during start-up phase is calculated as follows shown in Equation 18 and Equation 19.
æ
t ö÷÷
(VI - VO )(t) = V(IN) x ççç1÷
çè
t dVdT ø÷
(18)
æ V
ö
t
ç (IN) ÷÷
IL (t) = çç
÷x
ççè RL(SU) ÷÷ø t dVdT
(19)
Where RL(SU) is the load resistance present during start-up. Average energy loss in internal FET during charging
time due to resistive load is given by Equation 20.
tdVdT
Wt =
32
ò0
æ
t ÷÷ö ççæ V(IN)
t ÷÷ö
V(IN) x ççç1 xç
x
÷ dt
÷
t dVdT ø÷ çèç RL(SU)
t dVdT ø÷÷
èç
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(20)
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14
14
Output Voltage (V)
Power Dissipoation (W)
12
12
Load Current (A)
10
10
8
8
6
6
4
4
2
2
0
0
0
20
40
60
80
100
Start-Up Time, tdVdT (%)
V(IN) = 12 V
C(dVdT) = 1 nF,
C(OUT) = 100 µF
RL(SU) = 4.8 Ω
Output Voltage (V)
Load Current (A), Power Dissipation (W)
www.ti.com
V(IN) = 12 V
C(dVdT) = 1 nF,
C(OUT) = 100 µF
C013
RL(SU) = 4.8 Ω
Figure 59. PD(LOAD) in Load During Start-Up
Figure 58. Typical Start-Up With Load
Solving Equation 20 the average power loss in the device due to load is given by Equation 21.
V 2(IN)
æ 1ö
PD(LOAD) = çç ÷÷÷ x
çè 6 ø R
L(SU)
(21)
Total power dissipated in the device during start-up is given by Equation 22.
PD(STARTUP) = PD(INRUSH) + PD(LOAD)
(22)
Total current during start-up is given by Equation 23.
I(STARTUP) = I(INRUSH) + IL (t)
(23)
If I(STARTUP) > I(LIM), the device limits the current to I(LIM) and the current limited charging time is determined by
Equation 24.
t dVdT(current limited) = C(OUT) x
V(IN)
I(LIM)
(24)
The power dissipation, with and without load, for selected start-up time must not exceed the shutdown limits as
shown in Figure 60.
Thermal Shutdown Time (ms)
100000
TA -40C
= -40oC
TA 25C
= 25oC
10000
TA 85C
= 85oC
TA 125C
= 125oC
1000
100
10
1
0.1
1
10
100
Power Dissipation (W)
C014
2
Taken on 2-Layer board, 2oz.(0.08-mm thick) with GND plane area: 14 cm (Top) and 20 cm2 (Bottom)
Figure 60. Thermal Shutdown Limit Plot
For the design example under discussion,
Select ramp-up capacitor C(dVdT) = 1nF, using Equation 2, we get Equation 25.
t dvdt = 8.3 x 104 x 12 x 1 x 10-9 = 0.996ms = : 1ms
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(25)
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The inrush current drawn by the load capacitance (C(OUT)) during ramp-up is calculated using Equation 3 and
Equation 26.
(
I(INRUSH) = 100 x 10-6
æ
) x çççèç1 x1210-3
ö
÷÷÷ = 1.2 A
÷ø
(26)
The inrush Power dissipation is calculated, using Equation 17 and Equation 27.
PD(INRUSH) = 0.5 x 12 x 1.2 = 7.2 W
(27)
For 7.2 W of power loss, the thermal shut down time of the device must not be less than the ramp-up time tdVdT
to avoid the false trip at maximum operating temperature. From thermal shutdown limit graph Figure 60 at TA =
85°C, for 7.2 W of power the shutdown time is approximately 60 ms. So it is safe to use 1 ms as start-up time
without any load on output.
Considering the start-up with load 4.8 Ω, the additional power dissipation, when load is present during start-up is
calculated, using Equation 21 and Equation 28.
æ 1 ö 12 x 12
PD(LOAD) = çç ÷÷÷ x
=5W
çè 6 ø
4.8
(28)
The total device power dissipation during start up is given by Equation 29.
PD(STARTUP) = (7.2 + 5) = 12.2 W
(29)
From thermal shutdown limit graph at TA = 85°C, the thermal shutdown time for 12.2 W is close to 7.5 ms. It is
safe to have 30% margin to allow for variation of system parameters such as load, component tolerance, and
input voltage. So it is well within acceptable limits to use the 1 nF capacitor with start-up load of 4.8 Ω.
If there is a need to decrease the power loss during start-up, it can be done with increase of C(dVdT) capacitor.
To illustrate, choose C(dVdT) = 1.5 nF as an option and recalculate as shown in Equation 30 to Equation 34.
t dvdt = 1.5ms
(30)
æ
12
÷÷ö = 0.8 A
I(INRUSH) = 100 x 10-6 x ççç
çè1.5 x 10-3 ÷÷ø
(31)
PD(INRUSH) = 0.5 x 12x 0.8 = 4.8 W
(32)
æ 1 ö æ12 x 12 ÷ö
PD(LOAD) = çç ÷÷÷ x çç
÷ = 5W
èç 6 ø èç 4.8 ÷ø
(33)
PD(STARTUP) = 4.8 + 5 = 9.8 W
(34)
(
)
From thermal shutdown limit graph at TA = 85°C, the shutdown time for 10 W power dissipation is approximately
17 ms, which increases the margins further for shutdown time and ensures successful operation during start-up
and steady state conditions.
The spreadsheet tool available on the web can be used for iterative calculations.
10.2.2.6 Programing the Power Good Set Point
As shown in Figure 55, R4 and R5 sets the required limit for PGOOD signal as needed for the downstream
converters. Considering a power good threshold of 11 V for this design, the values of R4 and R5 are calculated
using Equation 35.
æ
R ö
V(PGTH) = 0.99 x ççç1 + 4 ÷÷÷
çè
R5 ÷ø
(35)
It is recommended to have high values for these resistors to limit the current drawn from the output node.
Choosing a value of R4 = 475 kΩ, R5 = 47 kΩ provides V(PGTH) = 11 V.
10.2.2.7 Support Component Selections—R6, R7 and CIN
Reference to application schematics, R6 and R7 are required only if PGOOD and FLT are used; these resistors
serve as pull-ups for the open-drain output drivers. The current sunk by each of these pins must not exceed 10
mA (see the Absolute Maximum Ratings table). CIN is a bypass capacitor to help control transient voltages, unit
emissions, and local supply noise. Where acceptable, a value in the range of 0.001 μF to 0.1 μF is
recommended for CIN.
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10.2.3 Application Curves
Figure 61. Hot-Plug Start-Up: Output Ramp Without Load
on Output
Figure 62. Hot-Plug Start-Up: Output Ramp With Start-Up
load of 4.8 Ω
Figure 63. Overvoltage Shutdown
Figure 64. Overvoltage Recovery
IMON
IMON
Figure 65. Over Load: Step Change in Load From 12 Ω to
2 Ω and Back
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Figure 66. Overload Condition: Auto Retry and
Recovery—TPS25942A
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Figure 67. Hot Short: Fast Trip and Current Regulation
Figure 68. Hot Short: Latched—TPS25942L
Figure 69. Hot Short: Auto-Retry and Recovery from Short
Circuit—TPS25942A
Figure 70. Hot Plug-In with Short on Output:
Latched—TPS25942L
Figure 71. Hot Plug-In With Short on Output: AutoRetry—TPS25942A
Figure 72. Power Good Response During Turnon
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Figure 73. Power Good Response During Turnoff
10.3 System Examples
The TPS25942 and TPS25944 provide a simple solution for power multiplexing applications through seamless
transition between two power supplies, each operating at 2.7 V to 18 V and delivering up to 5 A. The devices
with a distinctive feature set of true-reverse blocking, auto-forward conduction and fast switch over, support
applications for both Active ORing and Priority power multiplexing.
10.3.1 Active ORing (Auto-Power Multiplexer) Operation
A typical redundant power supply configuration of the system is shown in Figure 74. Schottky ORing diodes have
been popular for connecting parallel power supplies, such as parallel operation of wall adapter with a battery or a
hold-up storage capacitor. The disadvantage of using ORing diodes is high voltage drop and associated power
loss. The TPS25942 and TPS25944 with an integrated, low-ohmic N-channel FET provide a simple and efficient
solution. Figure 74 shows the Active ORing implementation using the devices.
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System Examples (continued)
Implementation
(See Note A)
IN1
2.7 to 18 V
Primary Supply
IN
CIN
R1
OUT
42m:
R5
EN/UVLO
OVP
Concept
R2
FLT
DMODE
Common Bus
IMON
ILIM
dVdT
R3
CdVdT
OUT
GND
TPS25942x
RILIM
RIMON
COUT
Hot-swap
System Load
TPS25942/44 integrates Hot-swap
and Current limiting functions
IN2
2.7 to 18 V
Auxiliary Supply
IN1
(See Note A)
IN2
R4
OUT
IN
CIN
42m:
EN/UVLO
DMODE
IMON
dVdT
CdVdT
ILIM
GND
TPS25942x
A.
RILIM
CIN: Optional and only for noise suppression.
Figure 74. Active ORing Implementation
A fast reverse comparator controls the internal FET and it is turned ON or OFF with hysteresis as shown in
Figure 75. The internal FET is turned ON in less than 4 us (typical) when the forward voltage drop V(IN) – V(OUT)
exceeds 100 mV and is turned off in 1 µs (typical) as soon as V(IN) – V(OUT) falls below –10 mV. When internal
FET is turned ON, the ORed input supply experiences momentary in-rush current drawn as the FET turns on
charging the bus capacitance. In addition, device can be operated in Diode Mode by independently controlling
DMODE pin.
Forward conduction
Reverse Blocking
-10
100
V(IN)-V(OUT) (mV)
Figure 75. Active ORing Thresholds
Figure 75 shows typical switch-over waveforms of Active ORing implementation using the TPS25942 or
TPS25944.
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System Examples (continued)
V(IN1) = 12.2 V
RL = 14 Ω
V(IN2) = 12 V
C(dVdT) = 1.5 nF
C(OUT) = 100 µF
Figure 76. IN1 Power Recovery: Change Over from IN2 to
IN1 (V(OUT) is AC Coupled)
V(IN1) = 12.2 V
RL = 14 Ω
V(IN2) = 12 V
C(dVdT) = 1.5 nF
C(OUT) = 100 µF
Figure 77. IN1 Brownout Condition: Change Over from IN2
to IN1 (V(OUT) is AC Coupled)
When bus voltages (IN1 and IN2) are matched, device in each rail sees a forward voltage drop and is ON
delivering the load current. During this period, current is shared between the rails in the ratio of differential
voltage drop across each device.
In addition to above, the devices provide inrush current limit and protects each rail from potential overload and
short circuit faults.
10.3.1.1 N+1 Power Supply Operation
The devices can be used to combine multiple power supplies to a common bus in an N+1 configuration. The N+1
power supply configuration as shown in Figure 78, is used where multiple power supplies are paralleled for either
higher capacity, redundancy or both. If it takes N supplies to power the load, adding an extra identical unit in
parallel permits the load to continue operation in the event that any one of the N supplies fails. The devices
emulate the function of the ORing diode and provides with all protections as needed to isolate the rail during hotplug, overvoltage, undervoltage, overcurrent and short-circuit conditions.
Concept
Implementation
V1
DC-DC
Converter
V2
DC-DC
Converter
V3
TPS25942
V2
TPS25942
Common Bus
V1
Common Bus
DC-DC
Converter
V3
TPS25942
Figure 78. N+1 Configuration Implementation
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System Examples (continued)
10.3.1.2 Priority Power MUX Operation
Applications having two energy sources such as PCIe cards, Tablets and Portable battery powered equipment
require preference of one source to another. For example, mains power (wall-adapter) has the priority over the
internal back-up power or auxiliary power. These applications demand for switch over from mains power to backup power only when main input voltage falls below a user defined threshold. The devices provide a simple
solution for priority power multiplexing needs.
Figure 79 shows a typical priority power multiplexing implementation using devices. When primary power IN1 is
present, the device in IN1 path powers the OUT bus irrespective of whether auxiliary power IN2 is greater than or
less than IN1. Once the voltage on the IN1 rail falls below the user-defined threshold, the device IN1 issues a
signal to switch over to auxiliary power IN2. The transition happens seamlessly in less than 125 µs, with minimal
voltage droop on the bus. The voltage droop during transition is a function of load current and bus capacitance
(see Equation 36).
V(droop) =
I(Load) x 125 ms
C(BUS)
where
•
V(droop) in Volts, I(Load) is load current in Ampere, C(BUS) is bus capacitance in µF
(36)
When the main voltage supply (IN1) is not present or during brown-out conditions, the device in auxiliary supply
rail (IN2) provides power to the output. When IN1 recovers, the device connected to IN1 is turned on at defined
slew rate and the device in IN2 path is turned off, allowing a seamless transition from auxiliary to the main
voltage supply with minimal droop and with no shoot-through current.
Priority power multiplexing can be done either between two similar rails (such as 12 V Primary to 12 V Aux, 3.3 V
Primary to 3.3 V Aux) or between dissimilar rails (such as 12 V Primary to 5 V Aux or 3.3 V Aux; or vice versa).
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System Examples (continued)
2.7 to 18 V
Primary Supply
OUT
IN
IN1
CIN
R1
42m:
(See Note A)
EN/UVLO
OVP
R2
DMODE
Master
dVdT
R3
R5
PGOOD
R6
PGTH
IMON
ILIM
VIN1
R7
OUT
GND
CdVdT
TPS25942x
RILIM
RIMON
COUT
priority signal
IN2
2.7 to 18 V
Auxiliary Supply
R4
CIN
42m:
EN/UVLO
OVP
dVdT
CdVdT
OUT
IN
(See Note A)
System Load
Slave
IMON
ILIM
GND
TPS25942x
RILIM
A.
CIN: Optional and only for noise suppression.
B.
Master controls the slave using priority signal for switch over to Auxiliary power.
Figure 79. Priority Power Multiplexing Implementation
Figure 80 and Figure 81 show typical switch-over waveforms of Priority Muxing implementation using the
TPS25942 or TPS25944 for 11.5 V Primary and 14.5 V Auxiliary Bus.
Figure 82 and Figure 83 show typical switch-over waveforms of Priority Muxing implementation using the
TPS25942 or TPS25944 for 12 V Primary and 3.3 V Auxiliary Bus.
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System Examples (continued)
V(IN1) = 11.5 V
V(IN2) = 14.5 V
RL = 5.6 Ω
R(ILIM1) = 24.6 kΩ,
R(ILIM2) = 33.2 kΩ
R(IMON) = 16.2 kΩ
C(OUT) = 150 µF
C(dVdT) = 1.2 nF
V(UVLO-High) = 10.8 V
Figure 80. IN1 Power Recovery: Change Over from
Auxiliary IN2 to Primary Power IN1
V(IN1) = 12 V
V(IN2) = 3.3 V
RLoad = 5.6 Ω
R(ILIM1) = 24.6 kΩ
R(ILIM2) = 33.2 kΩ
R(IMON) = 16.2 kΩ
C(OUT) = 150 µF
C(dVdT) = 1.2 nF
V(UVLO-High) = 10.8 V
Figure 82. IN1 Power Recovery: Change Over from
Auxiliary IN2 to Main Power IN1
V(IN1) = 11.5 V
V(IN2) = 14.5 V
RL = 5.6 Ω
R(ILIM1) = 24.6 kΩ
R(ILIM2) = 33.2 kΩ
R(IMON) = 16.2 kΩ
C(OUT) = 150 µF
C(dVdT) = 1.2 nF
V(UVLO-Low) = 10.2 V
Figure 81. IN1 Brownout Condition: Change Over from
Main IN1 to Auxiliary Power IN2
V(IN1) = 12 V
V(IN2) = 3.3 V
RL = 5.6 Ω
R(ILIM1) = 24.6 kΩ
R(ILIM2) = 33.2 kΩ
R(IMON) = 16.2 kΩ
C(OUT) = 150 µF
C(dVdT) = 1.2 nF
V(UVLO-Low) = 10.2 V
Figure 83. IN1 Brownout Condition: Change Over from
Main IN1 to Auxiliary Power IN2
10.3.1.3 Priority MUXing With Almost Equal Rails (VIN1 ~ VIN2)
Most of the redundant power supply systems used in servers, storage and telecom, multiplex tightly regulated
power rails to provide uninterrupted power to the load. In these systems, the primary and auxiliary rails are close
to each other, typically within one diode drop when both rails are active.
For priority multiplexing in these systems, the TPS25942 or TPS25944 device in auxiliary rail path can be
operated in Diode Mode for a fast switch-over (1 µs typical). The fast switch-over reduces the required hold-up
capacitor on the output rail for a given droop specification.
The circuit implementation of this configuration is shown in Figure 84. During power-fail (brown-out) conditions of
primary rail IN1, it changes IN2 from ‘Diode-Mode’ to normal operation using PGOOD. Similarly during power
recovery of primary rail IN1, the auxiliary rail IN2 is driven into ‘Diode-Mode’.
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System Examples (continued)
OUT
IN
IN1
*
2.7 to 18 V
Primary Supply
CIN
R1
42m:
EN/UVLO
OVP
R2
DMODE
PGOOD
Master
dVdT
R3
R5
R7
OUT
RILIM
*
CIN
System Load
42m:
EN/UVLO
DMODE
Slave
IMON
dVdT
CdVdT
COUT
OUT
IN
IN2
RIMON
*Optional & only for noise
suppression
priority signal
R4
VIN1
GND
CdVdT
TPS25942x
2.7 to 18 V
Auxiliary Supply
R6
PGTH
IMON
ILIM
ILIM
GND
TPS25942x
RILIM
Figure 84. Priority Power Multiplexing Configuration for Almost Equal Rails
The fast switch-over performance is shown in Figure 85.
C(OUT) = 150 µF
RL = 4 Ω
Figure 85. Brownout Condition: Diode Mode for Multiplexing
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System Examples (continued)
10.3.1.4 Reverse Polarity Protection
In applications demanding reverse polarity or reverse battery protection, the TPS25942 and TPS25944 can be
used as an eFuse or ideal diode. A typical reverse polarity protection circuitry is shown in Figure 86. The signal
diode in the GND terminal path ensures that device is not functional during reverse polarity conditions and
internal FET blocks the reverse path.
OUT
IN
IN
2.7 to 18 V
*
CIN
R1
DC/DC
Converter
OUT
COUT
42m:
R4
EN/UVLO
OVP
R2
FLT
DMODE
dVdT
R3
CdVdT
IMON
ILIM
GND
TPS25942x
Signal Diode
(30V, 0.2A)
RILIM
RIMON
*Optional & only for noise
suppression
Figure 86. Reverse Polarity Protection Implementation
11 Power Supply Recommendations
The devices are designed for supply voltage range of 2.7 V ≤ VIN ≤ 18 V. If the input supply is located more than
a few inches from the device an input ceramic bypass capacitor higher than 0.1 μF is recommended. Power
supply must be rated higher than the current limit set to avoid voltage droops during over current and short-circuit
conditions.
11.1 Transient Protection
In case of short circuit and over load current limit, when the device interrupts current flow, input inductance
generates a positive voltage spike on the input and output inductance generates a negative voltage spike on the
output. The peak amplitude of voltage spikes (transients) is dependent on value of inductance in series to the
input or output of the device. Such transients can exceed the Absolute Maximum Ratings of the device if steps
are not taken to address the issue.
Typical methods for addressing transients include
• Minimizing lead length and inductance into and out of the device
• Using large PCB GND plane
• Schottky diode across the output to absorb negative spikes
• A low value ceramic capacitor (C(IN) = 0.001 µF to 0.1 µF) to absorb the energy and dampen the transients.
The approximate value of input capacitance can be estimated with Equation 37.
VSPIKE(Absolute) = V(IN) + I(LOAD) x
L(IN)
C(IN)
where
•
•
•
•
44
V(IN) is the nominal supply voltage
I(LOAD) is the load current,
L(IN) equals the effective inductance seen looking into the source
C(IN) is the capacitance present at the input
Submit Documentation Feedback
(37)
Copyright © 2014–2017, Texas Instruments Incorporated
Product Folder Links: TPS25942A TPS25942L TPS25944A TPS25944L
TPS25942A, TPS25942L, TPS25944A, TPS25944L
www.ti.com
SLVSCE9D – JUNE 2014 – REVISED OCTOBER 2017
Transient Protection (continued)
Some applications may require the addition of a Transient Voltage Suppressor (TVS) to prevent transients from
exceeding the Absolute Maximum Ratings of the device.
The circuit implementation with optional protection components (a ceramic capacitor, TVS and schottky diode) is
shown in Figure 87.
IN
2.7 to 18 V
R1
(See Note A)
IN
R6
EN/UVLO
OVP
DMODE
dVdT
R3
COUT
42mO
CIN
(See Note A)
R2
CdVdT
R4
R7
FLT
PGOOD
PGTH
IMON
ILIM
(See Note A)
GND
TPS25942x
A.
OUT
OUT
RILIM
R5
RIMON
Optional components needed for suppression of transients
Figure 87. Circuit Implementation With Optional Protection Components
11.2 Output Short-Circuit Measurements
It is difficult to obtain repeatable and similar short-circuit testing results. Source bypassing, input leads, circuit
layout and component selection, output shorting method, relative location of the short, and instrumentation all
contribute to variation in results. The actual short itself exhibits a certain degree of randomness as it
microscopically bounces and arcs. Care in configuration and methods must be used to obtain realistic results. Do
not expect to see waveforms exactly like those in the data sheet; every setup differs.
Copyright © 2014–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS25942A TPS25942L TPS25944A TPS25944L
45
TPS25942A, TPS25942L, TPS25944A, TPS25944L
SLVSCE9D – JUNE 2014 – REVISED OCTOBER 2017
www.ti.com
12 Layout
12.1 Layout Guidelines
•
•
•
•
•
•
•
•
•
•
•
46
For all applications, a 0.1-uF or greater ceramic decoupling capacitor is recommended between IN terminal
and GND. For hot-plug applications, where input power path inductance is negligible, this capacitor can be
eliminated or minimized.
The optimum placement of decoupling capacitor is closest to the IN and GND terminals of the device. Care
must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the
GND terminal of the IC. See Figure 88 for a PCB layout example.
High current carrying power path connections must be as short as possible and must be sized to carry at
least twice the full-load current.
Low current signal ground (SGND), which is the reference ground for the device must be a copper plane or
island.
Locate all the TPS25942, TPS25944 support components: R(ILIM), CdVdT, R(IMON), and resistors for UVLO and
OVP, close to their connection pin. Connect the other end of the component to the SGND with shortest trace
length.
The trace routing for the RILIM and R(IMON) components to the device must be as short as possible to reduce
parasitic effects on the current limit and current monitoring accuracy. These traces must not have any
coupling to switching signals on the board.
The SGND plane must be connected to high current ground (main power ground) at a single point, that is at
the negative terminal of input capacitor.
Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the
device they are intended to protect, and routed with short traces to reduce inductance. For example, a
protection Schottky diode is recommended to address negative transients due to switching of inductive loads,
and it must be physically close to the OUT pins.
Thermal Considerations: When properly mounted the PowerPAD™ package provides significantly greater
cooling ability than an ordinary package. To operate at rated power, the PowerPAD must be soldered directly
to the board GND plane directly under the device. The PowerPAD is at GND potential and can be connected
using multiple vias to inner layer GND. Other planes, such as the bottom side of the circuit board can be used
to increase heat sinking in higher current applications. See the Technical Briefs: PowerPad™ Thermally
Enhanced Package ( SLMA002) and PowerPAD™ Made Easy (SLMA004) for more information on using this
PowerPAD™ package.
The thermal via land pattern specific to the TPS25942, TPS25944 can be downloaded from device webpage.
Obtaining acceptable performance with alternate layout schemes is possible; however this layout has been
shown to produce good results and is intended as a guideline.
Submit Documentation Feedback
Copyright © 2014–2017, Texas Instruments Incorporated
Product Folder Links: TPS25942A TPS25942L TPS25944A TPS25944L
TPS25942A, TPS25942L, TPS25944A, TPS25944L
www.ti.com
SLVSCE9D – JUNE 2014 – REVISED OCTOBER 2017
12.2 Layout Example
Top layer
Top layer signal ground plane
Bottom layer signal ground plane
Via to signal ground plane
Power Ground
OUT
OUT
IN
(See Note A)
Output
7
8
9
VI
IN 10
Input
High
Frequency
Bypass
Capacitor
11
6
OUT
IN 12
5
OUT
IN
13
4
OUT
EN 14
3
PGTH
OVP 15
2
PGOOD
GND 16
1
DMODE
IN
VO
20
FLT
19 IMON
18 dVdT
17 ILIM
Signal
Ground
Bottom
layer
Signal Ground
Top Layer
A.
Optional: Needed only to suppress the transients caused by inductive load switching.
Figure 88. Board Layout
Copyright © 2014–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS25942A TPS25942L TPS25944A TPS25944L
47
TPS25942A, TPS25942L, TPS25944A, TPS25944L
SLVSCE9D – JUNE 2014 – REVISED OCTOBER 2017
www.ti.com
13 Device and Documentation Support
13.1 Device Support
For the TPS25942A PSpice Transient Model, see SLVMAA3B.
For the TPS25942L PSpice Transient Model, see SLVMAA4A.
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation see the following:
• Reduce Diode Losses in Redundant Systems With Integrated Power MUXes
• TPS25942x635EVM: Evaluation Module For TPS25942x User's Guide
• TPS25944X635EVM: Evaluation Module for TPS25944X
• Power Multiplexing Using Load Switches and eFuses
13.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 3. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS25942A
Click here
Click here
Click here
Click here
Click here
TPS25942L
Click here
Click here
Click here
Click here
Click here
TPS25944A
Click here
Click here
Click here
Click here
Click here
TPS25944L
Click here
Click here
Click here
Click here
Click here
13.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.6 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.7 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
48
Submit Documentation Feedback
Copyright © 2014–2017, Texas Instruments Incorporated
Product Folder Links: TPS25942A TPS25942L TPS25944A TPS25944L
TPS25942A, TPS25942L, TPS25944A, TPS25944L
www.ti.com
SLVSCE9D – JUNE 2014 – REVISED OCTOBER 2017
13.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2014–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS25942A TPS25942L TPS25944A TPS25944L
49
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS25942ARVCR
ACTIVE
WQFN
RVC
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
25942A
TPS25942ARVCT
ACTIVE
WQFN
RVC
20
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
25942A
TPS25942LRVCR
ACTIVE
WQFN
RVC
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
25942L
TPS25942LRVCT
ACTIVE
WQFN
RVC
20
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
25942L
TPS25944ARVCR
ACTIVE
WQFN
RVC
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
25944A
TPS25944ARVCT
ACTIVE
WQFN
RVC
20
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
25944A
TPS25944LRVCR
ACTIVE
WQFN
RVC
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
25944L
TPS25944LRVCT
ACTIVE
WQFN
RVC
20
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
25944L
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Mar-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
TPS25942ARVCR
WQFN
RVC
20
TPS25942ARVCT
WQFN
RVC
TPS25942LRVCR
WQFN
RVC
TPS25942LRVCR
WQFN
TPS25942LRVCT
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3000
330.0
12.4
3.3
4.3
1.1
8.0
12.0
Q1
20
250
180.0
12.4
3.3
4.3
1.1
8.0
12.0
Q1
20
3000
330.0
12.4
3.3
4.3
1.1
8.0
12.0
Q1
RVC
20
3000
330.0
12.4
3.3
4.3
1.1
8.0
12.0
Q1
WQFN
RVC
20
250
180.0
12.4
3.3
4.3
1.1
8.0
12.0
Q1
TPS25942LRVCT
WQFN
RVC
20
250
180.0
12.4
3.3
4.3
1.1
8.0
12.0
Q1
TPS25944ARVCR
WQFN
RVC
20
3000
330.0
12.4
3.3
4.3
1.1
8.0
12.0
Q1
TPS25944ARVCT
WQFN
RVC
20
250
180.0
12.4
3.3
4.3
1.1
8.0
12.0
Q1
TPS25944LRVCR
WQFN
RVC
20
3000
330.0
12.4
3.3
4.3
1.1
8.0
12.0
Q1
TPS25944LRVCT
WQFN
RVC
20
250
180.0
12.4
3.3
4.3
1.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Mar-2020
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS25942ARVCR
WQFN
RVC
20
3000
367.0
367.0
35.0
TPS25942ARVCT
WQFN
RVC
20
250
210.0
185.0
35.0
TPS25942LRVCR
WQFN
RVC
20
3000
367.0
367.0
35.0
TPS25942LRVCR
WQFN
RVC
20
3000
367.0
367.0
35.0
TPS25942LRVCT
WQFN
RVC
20
250
210.0
185.0
35.0
TPS25942LRVCT
WQFN
RVC
20
250
210.0
185.0
35.0
TPS25944ARVCR
WQFN
RVC
20
3000
367.0
367.0
35.0
TPS25944ARVCT
WQFN
RVC
20
250
210.0
185.0
35.0
TPS25944LRVCR
WQFN
RVC
20
3000
367.0
367.0
35.0
TPS25944LRVCT
WQFN
RVC
20
250
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
RVC0020A
WQFN - 0.8 mm max height
SCALE 3.700
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
0.45
0.35
4.1
3.9
0.25
0.15
DETAIL
OPTIONAL TERMINAL
TYPICAL
C
0.8 MAX
SEATING PLANE
0.05
0.00
0.08
2X 1.5
SYMM
7
(0.2) TYP
EXPOSED
THERMAL PAD
10
16X 0.5
11
6
2X
2.5
SYMM
21
2.6 0.1
SEE TERMINAL
DETAIL
1
16
20X
PIN 1 ID
(OPTIONAL)
17
20
1.6 0.1
20X
0.25
0.15
0.1
0.05
C A B
0.45
0.35
4219150/B 03/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RVC0020A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.6)
SYMM
(R0.05)
TYP
17
20
20X (0.6)
1
16
20X (0.2)
(1)
TYP
21
SYMM
(3.8)
(2.6)
16X (0.5)
11
6
( 0.2) TYP
VIA
7
10
(1 TYP)
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
SOLDER MASK
OPENING
METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219150/B 03/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RVC0020A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
2X (1.47)
20
17
20X (0.6)
1
21
16
20X (0.2)
2X
(1.15)
(R0.05) TYP
SYMM
(3.8)
(0.675)
TYP
16X (0.5)
11
6
METAL
TYP
7
SYMM
10
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD X
81% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4219150/B 03/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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