VLSI PROJECTS LIST
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PROJECT TITLE
BINARY TO GRAY CODE CONVERTER IMPLEMENTATION
USING QCA
Design of a Reversible Floating-Point Square Root Using Modified
Non Restoring Algorithm
Design and Verification of DDR SDRAM Memory Controller
Using System Verilog For Higher Coverage
Concurrent Error Detectable Carry Select Adder with Easy
Testability
The Mesochronous Dual-Clock FIFO Buffer
DESIGN
Front End
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A High-Performance Multiply-Accumulate Unit by Integrating
Additions and Accumulations into Partial Product Reduction Front End
Process
Energy-Efficient Low-Latency Signed Multiplier for FPGA-based
Front End
Hardware Accelerators
An Efficient Parallel DA-Based Fixed-Width Design for
Front End
Approximate Inner-Product Computation
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Design of Power Efficient Posit Multiplier
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Design and analysis of High speed Wallace tree multiplier using
Front End
parallel prefix adders for VLSI circuit designs.
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Efficient Design for Fixed-Width Adder-Tree
Front End
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Hardware-Efficient Post-processing Architectures for True Random
Number Generators
Chaos-Based Bitwise Dynamical Pseudorandom Number Generator
on FPGA
Low-Power Approximate Unsigned Multipliers With Configurable
Error Recovery
Implementation of Ripple Carry and Carry Skip Adders with Speed
and Area Efficient
Front End
Borrow Select Subtractor for Low Power and Area Efficiency
Front End
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Front End
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Rapid Balise Telegram Decoder with Modified LFSR Architecture
Front End
for Train Protection Systems
A Low-Power Yet High-Speed Configurable Adder for
Front End
Approximate Computing
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High-Speed Area-Efficient VLSI Architecture of Three-Operand
Binary Adder
Design of 4:2 Compressor for Parallel Distributed Arithmetic FIR
Filter
PERFORMANCE ANALYSIS OF PARALLEL PREFIX ADDER
FOR DATAPATH VLSI DESIGN
Approximate Reverse Carry Propagate Adder for Energy-Efficient
DSP Applications
Architecture Optimization and Performance Comparison of NonceMisuse-Resistant Authenticated Encryption Algorithms
TOSAM:AnEnergy-EfficientTruncation-andRoundingBasedScalableApproximate Multiplier
Design And Analysis Of Approximate Redundant Binary
Multipliers.
Rounding Technique Analysis Of Power-Area & Energy Efficient
Approximate Multiplier Design
A Combined Arithmetic-High-Level Synthesis Solution to Deploy
Partial Carry-Save Radix-8 Booth Multipliers in Datapath.
Low Power High Accuracy Approximate Multiplier Using
Approximate High Order Compressors.
Efficient Modular Adder Designs Based on Thermometer & OneHot Encoding
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Error Detection And Correction In SRAM Emulated TCAMs
Front end
Efficient Design For Fixed Width Adder Tree
Front end
Area –Time Efficient Streaming Architecture For Architecture For
FAST And BRIEF Detector
Hard Ware Efficient Post Processing Architecture For True
Random Number Generators
Front end
Front end
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A Two Speed Radix -4 Serial –Parallel Multiplier
Front end
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Low power approximate unsigned multipliers with configurable
error recovery
Energy Quality Scalable Adders Based On Non Zeroing Bit
Truncation
Double MAC On A DSP Boosting The Performance Of
Convolutional Neural Networks On FPGAS
Front end
A Low-Power Parallel Architecture for Linear Feedback Shift Registers
Front end
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Ultra-low-voltage GDI-based hybrid full adder design for area and
energy-efficient computing systems
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Design Of Area Efficient And Low Power 4-Bit Multiplier Based On
Full- swing GDI technique
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Multistage Linear Feedback Shift Register Counters With Reduced
Decoding Logic in 130-nm CMOS for Large-Scale Array Applications
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Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced DataIndependent Read Port Leakage for Array Augmentation in 32-nm CMOS
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Column selection enabled 10 T SRAM utilizing shared diff VDD
WRITE and dropped VDD read for FFT on real data.
Cell-state-distribution –assisted threshold voltage detector for
NAND flash memory
Efficient VLSI Implementation of a Sequential Finite Field
Multiplier Using Reordered Normal Basis in Domino Logic
An Approach to LUT Based Multiplier for Short Word Length DSP
Systems
Novel High speed Vedic Multiplier proposal incorporating Adder
based on Quaternary Signed Digit number system
FPGA Implementation of an Improved Watchdog Timer for Safetycritical Applications
Unbiased Rounding for HUB Floating-point Addition
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Frontend
Frontend
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Frontend
A Low-Power Yet High-Speed Configurable Adder for
Approximate Computing
A Low-Power High-Speed Accuracy-Controllable Approximate
Multiplier Design
The Design and Implementation of Multi – Precision Floating Point
Arithmetic Unit Based on FPGA
Extending 3-bit Burst Error-Correction Codes With Quadruple
Adjacent Error Correction
Efficient Modular Adders based on Reversible Circuits
Frontend
MAES: Modified Advanced Encryption Standard for Resource
Constraint Environments
Chip Design for Turbo Encoder Module for In-Vehicle System
Frontend
Low-Power and Fast Full Adder by Exploring New XOR and
XNOR Gates
Low Power 4×4 Bit Multiplier Design using Dadda Algorithm and
Optimized Full Adder
Backend
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Frontend
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Backend
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Low Leakage Fully Half-Select-Free Robust SRAM Cells with BTI
Reliability Analysis
Improved 64-bit Radix-16 Booth Multiplier Based on Partial
Product Array Height Reduction
Clock-Gating of Streaming Applications for Energy Efficient
Implementations on FPGAs
An Improved DCM-Based Tunable True Random Number
Generator for Xilinx FPGA
RoBA Multiplier: A Rounding-Based Approximate Multiplier for
High-Speed yet Energy-Efficient Digital Signal Processing
DLAU: A Scalable Deep Learning Accelerator Unit on FPGA
Overloaded CDMA Crossbar for Network-On-Chip
Design of Power and Area Efficient Approximate Multipliers
Scalable Approach for Power Droop Reduction During Scan-Based
Logic BIST
Design of Low-Power High-Performance 2-4 and 4-16 MixedLogic Line Decoders.
Performance Analysis of a Low-Power High-Speed Hybrid 1-bit
Backend
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Full Adder Circuit
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12T Memory Cell for Aerospace Applications in Nano scale CMOS
Backend
Technology
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Pre-Encoded Multipliers Based on Non-Redundant Radix-4 SignedDigit Encoding
Flexible DSP Accelerator Architecture Exploiting Carry-Save
Arithmetic
Low-Cost High-Performance VLSI Architecture for Montgomery
Modular Multiplication
A High-Speed FPGA Implementation of an RSD-Based ECC
Processor
Hybrid LUT/Multiplexer FPGA Logic Architectures
In-Field Test for Permanent Faults in FIFO Buffers of NOC
Routers
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