Analog Filter Design: Current
Design Techniques and Trends
Edgar Sánchez-Sinencio
Distinguished and TI J. Kilby Chair
Professor
Educational Session ES2-2
Analog Active Filters:
Introduction and motivation
• Analog Filters are used in a host of applications and are key
building blocks in a number of applications.
• The main components in active filters are Op Amp (VCVS) or
Transconductance Amplifier (VCCS), resistors and capacitors.
• In this presentation we discuss different implementations of
non- conventional Amplifiers and their strengths and
weakness.
• Also we present different non-conventional filter topologies in
different domains and/or their implementations.
• Linearity of amplifiers/filters* is still an important active
research area, not discussed here for lack of time.
* M. Mobarak, M. Onabajo, J. Silva-Martinez and E. Sanchez-Sinencio, "Attenuation-Predistortion
Linearization of CMOS OTAs With Digital Correction of Process Variations in OTA-C Filter
Applications," in IEEE Journal of Solid-State Circuits, vol. 45, no. 2, pp. 351-367, Feb. 2010
2
Analog Active Filters: Outline
• Continuous-Time Filters
– Active-R
– Switched-R
– Ring Oscillator Based
– PWM Based
– Inverter Based OTA-C
– Hybrid Filter CT + DT
3
Analog Active Filters: Outline
• Continuous-Time Filters
– Active-R Why?
– The Gm-C filters are operated in open loop
and thus have modest linearity.
Gm-C filter depend on the transconductance
gain Gm and are PVT sensitive but a good
tuning technique has solved those problems.
 Active-R deserves an opportunity to challenge
conventional Gm-C filters
4
Active-R: Basic concept
• Uses the low-pass characteristics of
transistors instead of capacitors to
implement lossy integrators.
𝜔3𝑑𝐵 =
𝐺𝐵𝑊
𝑅
1+ 2
𝑅1
[1] Brand, J.R.; Schaumann, R., "Active R filters: review of theory and practice,“ IEEE Journal on Electronic Circuits and Systems, vol.2, no.4, pp.89,, July 1978
5
Active-R filters: Tradeoffs
 ω0 in the order of magnitude of GBW
 No need for feedback capacitors
 Can compete with Gm-C filters
 Sensitive to PVT
 Load resistance affecting DC gain
 Take into account higher-order poles i.e.
𝐺𝐵𝑊 −𝑠𝜏 𝐺𝐵𝑊
𝐴 𝑠 =
𝑒
≅
(1 − 𝑠𝜏)
𝑠
𝑠
6
Active-R: Basic concept
Uses the low-pass characteristics of Op Amps
instead of capacitors to implement integrators.
Lossy Integrator
αR
Vi
R
-
Building blocks Lossless Integrator
Vi
Vo
A(s)
R
αR
-A(s)
+
Vo
+
𝐴(𝑠) =
𝛼
𝑠
1+
(1 + 𝛼)
𝐺𝐵𝑊
α
α′ =
α+1
𝐺𝐵𝑊α′
𝐴(𝑠) =
𝑠
[1] Brand, J.R.; Schaumann, R., "Active R filters: review of theory and practice,“ IEEE Journal on Electronic Circuits and Systems, vol.2, no.4, pp.89,, July 1978
7
8
9
10
Comparison First-Order Gm-C vs. Active-R
11
Bandpass – 2nd order Active-R filter
2R3
R4
Vi 2R3
-A (s)
R2
+
1
+
VoLP
A2(s)
VoBP R1
-
𝑤ℎ𝑒𝑛 𝑡ℎ𝑒 𝑂𝑝𝐴𝑚𝑝 𝑝𝑜𝑙𝑒𝑠:
𝜔𝑝1 ≪ 𝐺𝐵𝑊1 & 𝜔𝑝2 ≪ 𝐺𝐵𝑊2
𝐻𝐵𝑃 𝑠 ≈
𝜔0 =
𝜔0
𝑠 + 𝜔𝑝2
𝑄
𝜔
𝑠 2 + 0 𝑠 + 𝜔02
𝑄
−𝐻0
𝐺𝐵𝑊1 ⋅ 𝐺𝐵𝑊2 ⋅ 𝛼 ⋅ 𝑅/𝑅1
𝛼=
𝑄=
𝑅42
𝐺𝐵𝑊2 ⋅ 𝛼 ⋅
𝐺𝐵𝑊1 ⋅ 𝑅 ⋅ 2𝑅3
𝑅1
𝑅1 + 𝑅2
𝑅 = 𝑅4 ||𝑅3
𝐴𝑖 𝑠 =
𝐺𝐵𝑖
𝑠 + 𝜔𝑖
[2] Venkateswaran, S., "Multifunction active R filter with two operational amplifiers," Electronics Letters , vol.14, no.23, pp.741,742, November 9 1978
[3] Rao, K.R.; Srinivasan, S., "A bandpass filter using the operational amplifier pole," Solid-State Circuits, IEEE Journal of , vol.8, no.3, pp.245,246, June 1973
12
13
14
Remarks on comparison Gm-C vs. Active-R filters
15
Analog Active Filters: Outline
• Continuous-Time Filters
– Active-R
- Switched-R
- Ring Oscillator Based
- PWM Based
- Inverter Based OTA-C
- Hybrid Filter CT + DT
16
Why switched-R?
• Switched-R (SW-R) filters employ
switches to adjust the time constant of the
filter by changing the duty cycle of the
clock controlling the switches.
 Allows for continuously tunable filters that can
offer a flexible solution for wide ranges of
adjustable bandwidth
17
What are switched-R?
Φ(t) periodic with “TS”
and ON period “TON”
• Duty-cycle controlled switches
are used to control the amount
of charge transferred through a
resistor to a capacitive element.
𝑇𝑂𝑁
𝑇𝑂𝑁
𝐷=
=
𝑇𝑆
𝑇𝑂𝑁 + 𝑇𝑂𝐹𝐹
𝜏=
𝑅𝐶
𝐷
• The overall effective resistance
is defined as the ratio of applied
voltage to average current
which flows to the branch over
one clock period:
𝑅𝑒𝑞
𝑅
=
𝐷
0<𝐷≤1
[1] Kaehler, J.A., "Periodic-switching filter networks-a means of amplifying and varying transfer functions," IEEE Journal of Solid-State Circuits, vol.4, no.4, pp.225,230, Aug 1969
[2] Kurahashi, P.; Hanumolu, P.K.; Temes, G.C.; Un-Ku Moon, "Design of Low-Voltage Highly Linear Switched-R-MOSFET-C Filters,“ IEEE Journal of Solid-State Circuits, vol.42, no.8,
pp.1699,1709, Aug. 2007
18
First-order filter example
Charging phase
•
The complementary switch (SWc)
stirs current to ground when SW is
off such that the current loading
through the resistor branches is
consistent over both clock phases.
Vo
Hold phase
𝜏𝑒𝑓𝑓
𝑅1 𝐶1
=
𝐷
Continuous (100% duty-cycle)
75% duty-cycle
50% duty-cycle
25% duty-cycle
For a step input:
𝑉𝑂𝑒𝑓𝑓 = 1 −
𝐷𝑡
−
𝑒 𝑅1𝐶
𝑢(𝑡)
19
First-order filter example
•
Switched-R filter can allow the
realization of continuously tunable
filters by controlling the duty cycle.
S-1R
𝑅
− 𝑅2
1
𝐻 𝑠 =
𝑠
1+𝜔
3𝑑𝐵
𝜔3𝑑𝐵𝑠−1𝑅
R2=R1
𝐷
=
𝑅2 𝐶
[2]
20
Issues on switches for SW-R vs. SC Filters
• SW-R filters do not
contain floating switches
on large signal nodes,
which can result in
switching limitations on
low voltage operation
when implementing SC
filters. May require clock
bootstrapping [3].
[3] S. Xiao, J. Silva, Un-Ku Moon and G. Temes, "A tunable duty-cycle-controlled switched-R-MOSFET-C CMOS filter for low-voltage and high-linearity applications,"
ISCAS '04. Proceedings of the 2004 International Symposium on Circuits and Systems, 2004, pp. I-433-6 Vol.1.
21
S-2R architecture
𝑘2 + 𝑘1
𝐻 𝑠 =−
𝑠
1+𝜔
3𝑑𝐵𝑆−2𝑅
𝜔3𝑑𝐵𝑠−2𝑅 =
•
There are two paths that charge the cap.
•
Each path is associated with a different
time constant.
•
There is no hold period unlike S-1R.
•
S-2R networks are less sensitive to slew
rate limitation, relaxing the requirements
of the amplifier and reducing the clock
harmonic distortion at the output.
1
1
𝐷
1−𝐷
+ =
+
𝜏1 𝜏2
𝑘1 𝑅1 𝑘2 𝑅2
1
1+ 𝑥−1 𝐷 1
=
𝐶
𝑥𝑘1 𝑅1
𝐶
k2R2
𝑥=
𝑘1 R1
[4] Jiraseree-amornkun, A.; Worapishet, A.; Klumperink, E.; Nauta, B.; Surakampontorn, W., "Theoretical Analysis of Highly Linear
Tunable Filters Using Switched-Resistor Techniques," IEEE Transactions on Circuits and Systems I: Regular Papers, vol.55,
22
no.11, pp.3641,3654, Dec. 2008
S-2R – Tuning range and distortion trade-off
The S-2R topology reduces the
maximum slope at the output of
the filter, reducing the clock
harmonic distortion at the output
(HDclk) with respect to the signal
component (Hdin).
• Resistor ratio trade-off:
 Tuning Range increases with
x.
 Clock harmonic distortion also
increases with x.
Δ𝜔3𝑑𝐵𝑆−1𝑅 % = 2
𝐷𝑚𝑎𝑥/𝑚𝑖𝑛 − 0.5
100%
0.5
Δ𝜔3𝑑𝐵𝑆−2𝑅 % = 2
(𝑥 − 1) 𝐷𝑚𝑎𝑥/𝑚𝑖𝑛 − 0.5
1 + (𝑥 − 1)0.5
where 𝑥 =
𝑅2
𝑅1
S-2R tuning and distortion trade-off
58
100%
100
56
80
54
60
52
40
50
20
48
1
2
3
4
5
6
7
Resistor ratio - x
8
9
Tuning range (%)
•
The frequency tuning range is
defined as the range of variation of
the cut-off frequency from the
nominal case (D=50%).
HDin/HDclk (dB)
•
0
10
23
Topology comparison: S-1R VS S-2R
The reduction on clock harmonic distortion at the output requires the use of a small
scaling factor x, this greatly reduces the frequency tuning range of the filter, which is
always smaller than the tuning range of the S-1R architecture.
X=2
𝐹𝐼𝑁 = 100𝐾𝐻𝑧
𝐹𝐶𝐿𝐾 = 16𝑀𝐻𝑧
Clock to signal freq. ratio:
𝐹𝐶𝐿𝐾
𝐹𝐼𝑁
= 160
24
fin=2kHz
fs=128MHz
Op-Amp GBW=20MHz
Higher-order filters
• Higher order filters using switched-R can be
realized using the Switching-R topologies, like
the biquad structure proposed in [3].
Rb1 and Rb2 resistors are added to bias the input of the Op-Amps (PMOS
input) near ground, allowing low voltage operation.
[5] Kurahashi, P.; Hanumolu, P.K.; Temes, G.; Un-Ku Moon, "A 0.6V Highly Linear Switched-R-MOSFET-C Filter," CICC '06. IEEE
25
Custom Integrated Circuits Conference, 2006, vol., no., pp.833,836, 10-13 Sept. 2006
Linearity of Switched-R filters
• The harmonics of the clock appear on the
output spectrum of the filter.
• Using high frequency clocks can alleviate this
problem.
Push the clock harmonics to higher frequencies,
which can be easily filter out.
However, this increases power consumption,
makes the control of the duty cycle challenging
and can result in additional distortion from slewrate limited operation.
26
How can we reduce clock harmonic
distortion without compromising
tuning range?
One solution: Clock’s spurious tone cancellation (1/2)
•
In order to avoid using high frequency clock signals a harmonic cancellation
technique [5] can be employed to cancel out the spurious tones coming from the
clock.
𝑉𝑜𝑢𝑡
•
1
𝑗𝜔 = −
[𝑉 𝑗𝜔 ∗
𝑗𝜔𝑅𝐶 𝑖𝑛
4𝑒
−3𝑗𝜋𝑛
4
cos
𝜋𝑛
𝜋𝑛
cos
2
4
𝑉𝑐𝑙𝑘 𝑗𝜔
,
𝑛 = 𝜔/𝜔𝑐𝑙𝑘
Multiple paths are introduced with a delay (phase shift), which cancel harmonic
components of the clock without affecting the fundamental.
e-s3T/4
-s3T/4
e
Vclk(s)
e-sT/2
Vclk(s)
1/R
e-sT/2
1/R
e-sT/4
-sT/4
e
1/R
1/R
1/R
1/R
1/R
1/R
Vin(s)
OA
1/R
1/R
Vo(s)
Vin(s)
OA
1/R
Vo(s)
1/R
Lossless integrator
First order low-pass filter
[6] Soto-Aguilar S., Alagappan, A., Sanchez-Sinencio, E., “Clock Harmonic Distortion Reduction Technique for Full Tunable Range in Switched-R-MOSFET-C
27
Filters“, Journal of Analog Integrated Circuits and Signal Processing, to be published.
[5]
Clock’s spurious tone cancellation (2/2)
 The technique employs 4 phases to cancel the first tree harmonics
while still maintaining 100% frequency tuning range, unlike S-2R.
 Cancellation is sensitive to mismatch between the multi-phase paths
First clock harmonic appears at 4𝐹𝑐𝑙𝑘
28
COMPARISON SUMMARY
Topology
S-1R
S-2R
Multi-phase S-1R
Harmonic distortion
1st order active filter
47dB
Tow-Thomas biquad
45dB
1st order active filter
57dB
Tow-Thomas biquad
55dB
1st order active filter
98dB
Tow-Thomas biquad
88dB
Tuning range
100%
34%
100%
[6]
Switches Ron = 36.59Ω
OTA: ADC = 49.9dB, UGB = 102.33MHz
29
Analog Active Filters: Outline
• Continuous-Time Filters
-
Active-R
Switched-R
Ring Oscillator Based
PWM Based
Inverter Based OTA-C
Hybrid Filter CT + DT
30
Ring Oscillators as Integrators
• A ring VCO is an integrator with
voltage input and phase output
𝜙𝑜𝑢𝑡
𝐾𝑉𝐶𝑂
=
𝑣𝑖𝑛 𝑠
𝑠
• Advantages:
Infinite DC gain
Process scalable
Can operate with low supply
voltages
•
•
M. Park, et al., "A multiphase PWM RF modulator using a VCO-based opamp in 45nm CMOS,”, IEEE RFIC, 2010, pp.39-42.
31
B. Drost, et al., "Analog Filter Design Using Ring Oscillator Integrators,” IEEE JSSC, Dec. 2012, pp.3120-3129.
RO Integrator with Current Input and Current
Output
𝐻𝐼𝑁𝑇
𝑠
𝐼𝑂𝑈𝑇 𝐾𝐶𝑃 𝐾𝐶𝐶𝑂 𝐾𝑃𝐷
=
=
𝐼𝐼𝑁
𝑠
• Use PD+CP for phase-to-voltage/current conversion to
interface with other building blocks
• IOUT is PWM current signal
•
•
M. Park, et al., "A multiphase PWM RF modulator using a VCO-based opamp in 45nm CMOS,”, IEEE RFIC, 2010, pp.39-42.
32
B. Drost, et al., "Analog Filter Design Using Ring Oscillator Integrators,” IEEE JSSC, Dec. 2012, pp.3120-3129.
RO Integrator Non-Idealities -1
• Spurious Tones
– Increase FOSC
 Push out harmonics
 Higher power consumption
 Poor linearity as on/off time of the PWM signal gets comparable
with rise/fall time of PD and CP
•
•
M. Park, et al., "A multiphase PWM RF modulator using a VCO-based opamp in 45nm CMOS,”, IEEE RFIC, 2010, pp.39-42.
33
B. Drost, et al., "Analog Filter Design Using Ring Oscillator Integrators,” IEEE JSSC, Dec. 2012, pp.3120-3129.
RO Integrator Non-Idealities -2
• Spurious Tones
– Multiphase PWM
 Cancel all tones up to MFOSC
 Prone to mismatch
•
•
M. Park, et al., "A multiphase PWM RF modulator using a VCO-based opamp in 45nm CMOS,”, IEEE RFIC, 2010, pp.39-42.
34
B. Drost, et al., "Analog Filter Design Using Ring Oscillator Integrators,” IEEE JSSC, Dec. 2012, pp.3120-3129.
RO Integrator Non-Idealities -3
• Non-Linearity
– VCO: Non-linear voltage/current-to-frequency
conversion
• Pseudo-differential architecture  Cancel even order harmonics
– PD+CP: Non-linear behavior when on/off time of the
PWM signal becomes comparable to rise/fall times.
• Limit max duty cycle to be less than 90%
•
B. Drost, et al., "Analog Filter Design Using Ring Oscillator Integrators,” IEEE JSSC, Dec. 2012, pp.3120-3129.
35
RO Integrator Non-Idealities -4
• Integrator Parasitic Poles
– Parasitic pole at VCO supply node
• Add linear resistance RC at supply node
 Pushes parasitic pole to higher frequency
𝜔𝑝𝑎𝑟 =
1
𝑅𝑉𝐶𝑂 𝑅𝐶 𝐶𝑃
𝑅𝑐 < 𝑅𝑉𝐶𝑂
 Improve VCO linearity because it
appears in parallel with non-linear
RVCO
 Reduce loop gain when ROI is utilized
in feedback system
•
B. Drost, et al., "Analog Filter Design Using Ring Oscillator Integrators,” IEEE JSSC, Dec. 2012, pp.3120-3129.
36
First-Order LPF Using RO Integrator
• 3-db bandwidth tuning by varying feedback CP current
𝐻𝐿𝑃𝐹 𝑠 =
1
𝑅𝐼𝑁 𝐾𝐶𝑃𝐹𝐵 1 +
1
𝑠
𝐾𝐶𝑃𝐹𝐵 𝐾𝐶𝐶𝑂 𝐾𝑃𝐷
𝐾𝐶𝑃𝐹𝐵 = 𝑀 × 𝐼𝐶𝑃
•
B. Drost, et al., "Analog Filter Design Using Ring Oscillator Integrators,” IEEE JSSC, Dec. 2012, pp.3120-3129.
37
Tow-Thomas Biquad Using RO Integrator
• Frequency tuning by changing CP bias currents
𝐻𝐿𝑃𝐹 𝑠 =
•
1
𝑅𝐼𝑁 𝐾𝐶𝑃𝐹
1
𝑠2
𝐾𝐶𝐶𝑂1 𝐾𝐶𝐶𝑂2 𝐾𝑃𝐷1 𝐾𝑃𝐷2 𝐾𝐶𝑃1 𝐾𝐶𝑃𝐹
𝐾𝐶𝑃2 𝑠
+1
𝐶𝐶𝑂1 𝐾𝑃𝐷1 𝐾𝐶𝑃1 𝐾𝐶𝑃𝐹
+𝐾
B. Drost, et al., "Analog Filter Design Using Ring Oscillator Integrators,” IEEE JSSC, Dec. 2012, pp.3120-3129.
38
Tow-Thomas Biquad Using RO Integrator
• Frequency tuning and Q tuning by changing CP bias currents
Q=1.5
Q=1
Q=0.7
KCP1=KCPF=108 µA
Q=0.7
fo=1-20 MHz
Q=0.7-1.5
fo=20 MHz
39
ROI-based Filter Design: An Example
• ROI-based LPF with BW=100kHz
𝐻𝐿𝑃𝐹 𝑠 =
1
𝑅𝐼𝑁 𝐾𝐶𝑃𝐹𝐵 1 +
1
𝑠
𝐾𝐶𝑃𝐹𝐵 𝐾𝐶𝐶𝑂 𝐾𝑃𝐷
Parameter
Value
fCCO
100 MHz
KCCO
400 MHz/A
KPD
1/π
KCPFB
392.7 µA
RIN
1 kΩ
40
Simulation Results – Frequency Response
41
Simulation Results – Output Waveforms
M=2
M=1
M=8
42
Simulation Results – Spectral Purity
𝑓𝐼𝑁 = 100 𝑘𝐻𝑧
43
Ring Oscillator Based Amplifier (ROA)
• Another approach is to use the ring oscillator as an infinite DC gain
Opamp in an active-RC filter topology.
Zero
Compensation
• Spurs at VCO oscillation frequency are filtered out if the oscillation
frequency is greater than the desired signal bandwidth
• Effect of non-linearity is improved because of the feedback loop
•
C. W. Hsu and P. R. Kinget, "A 40MHz 4th-order active-UGB-RC filter using VCO-based amplifiers with zero
compensation," ESSCIRC 2014 - 40th, Venice Lido, 2014, pp. 359-362.
44
Ring Oscillator Based Amplifier (ROA)
• 3rd-order Chebyshev active-RS filter using amplifiers with different
DC gains and the ROA
•
C. W. Hsu and P. R. Kinget, "A 40MHz 4th-order active-UGB-RC filter using VCO-based amplifiers with zero
compensation," ESSCIRC 2014 - 40th, Venice Lido, 2014, pp. 359-362.
45
Open Challenges
How to improve linearity of the ROI-based filter
•Linearity of the filter is limited by the non-linear current/voltage-tofrequency conversion of the RO since it operates in open loop.
How to utilize ROI in discrete time filters
•So far ROI is only used in continuous time filters.
How to cancel spurious tones effectively
•Multiphase technique is prone to mismatch
46
Analog Active Filters: Outline
• Continuous-Time Filters
-
Active-R
Switched-R
Ring Oscillator Based
PWM Based
Inverter Based OTA-C
Hybrid Filter CT + DT
47
PWM Filter Design
• The basic idea of Pulse-Width Modulation (PWM) filters
is to replace the linear output stage (Class-A or ClassAB) with a non-linear stage (Class-D).
48
PWM Filter Design
• Advantages
 Building blocks are less sensitive to voltage supply
reduction
 It takes advantage of higher fT as technology scales
 Theoretical rail-to-rail output swing
• Disadvantages
 Strong out of band harmonic components due to the
switching frequency
 Complex implementation compared to standard filter
architectures
 The modulators consume a significant amount of the
power in the system
49
PWM First-Order Filter
• A Fully-Differential lossy integrator is used to illustrate
VA+
VA-
VS+
VS-
Parameter
Value
VDD
1V
R2, R1
10 kΩ
C
4 pF
F-3dB
4 MHz
LPF
80 MHz
CLPF
2 pF
RLPF
1 kΩ
FS
200 MHz
Vtri
550 mVpk-pk
A0
35 dB
THDVA+-VA-
-45 dB
50
Simulation Results of First-Order Filter
Vout = Vout+-Vout-
Parameter
Value
VDD
1V
fin
100 kHz
Vin,Diff
800 mVpk
THD
-45.2dB (0.55 %)
HD2
-62.5 dB (0.01%)
HD3
-48 dB (0.29%)
HD5
-48.5 dB (0.25%)
BW = 4 MHz
51
Simulation Results for one and four phases PWM filter
After filter
Before filter
THD =-14 dB
Before filter
THD =-24 dB
After filter
THD =-14 dB
THD =-36 dB
Vout Diff.
Parameter
Single Phase
4-Phase
VDD
1V
1V
fin
100 kHz
100 kHz
FS
200 MHz
200 MHz
Vtri
550 mVpk-pk
550 mVpk-pk
MHighest Spur
400 MHz
1.6 GHz
Comparators
2
8
Out-of-Band THD
~ 7.31 %
52%
~ 1.86
PWM Filter Design
• Current State-of-the-art: Multi-Phases to push out harmonics
Fs,eff = 2.4 GHz
FBW = 70 MHz
Fs,eff / FBW = 34
•
Vigraham, B.; Kuppambatti, J.; Kinget, P.R., "Switched-Mode Operational Amplifiers and Their Application to Continuous-Time
53
Filters in Nanoscale CMOS," IEEE Journal of Solid-State Circuits, vol. 49, no. 12, pp. 2758-2772, Dec. 2014
PWM Filter Design
• Current Challenges
1. To effectively remove the modulation frequency at
the output of the OpAmp
2. To determine the trade-offs between power, filter
bandwidth and linearity
3. To explore more PWM filter architectures
54
Analog Active Filters: Outline
• Continuous-Time Filters
-
Active-R
Switched-R
Ring Oscillator Based
PWM Based
Inverter Based OTA-C
Hybrid Filter CT + DT
55
Basic Concepts
Motivations
•High data rate communication applications need filters with several
100s MHz bandwidth
Hard disk drive, UWB communications
•Technology/Power supply voltage scaling makes typical analog
design such as OTAs more difficult
Reduced headroom/dynamic range/intrinsic gain
Inverter-based OTA
•Good for low voltage low power high speed applications
Only one high impedance node at the output
Class AB operation
Bram Nauta, “A CMOS transconductance-C filter technique for very high frequencies,” in IEEE J. Solid-State Circuits, vol. 27, no. 2, pp.142-153,
56
Feb. 1992
Inverter as a transconductor (Gm)
I OUT   g mp Vin
NEXT
I OUT   g mn Vin
I OUT  ( g mn  g mp ) Vin
?
 One MOSFET transistor is essentially the simplest Gm cell
 Inverter is a current-reused Gm cell consisting of
complementary PMOS and NMOS
It sounds good, but there are several design issues for OTA
applications
•How to stabilize output common mode
•How to increase output resistance (DC gain)
•How to enhance linearity
57
Class AB Inverter
PMOS
OFF
NMOS
OFF
VDD =1V, VOCM = 0.5V
58
Class AB Inverter as a high speed Gm
GM
Z OUT _ CM 
g m _ red
1
 g m _ blue
Inverter-based OTA’s class AB operation
1
Z

OUT _ DM
VTHN  VTHP  VDD
g m _ red  g m _ blue
Green inverters  Main GM cell
Red inverters  Common mode control/Q tuning using supply
Blue inverters  Negative gm for DC gain enhancement
Balanced configuration for linearity improvement
Bram Nauta, “A CMOS transconductance-C filter technique for very high frequencies,” in IEEE J. Solid-State Circuits, vol. 27, no. 2, pp.142-153,
59
Feb. 1992
Inverter-based vs. Conv. OTA-based
Power supply voltage determines inverter-based OTA’s class and the
optimal design point
Class AB inverter-based OTA is good for high speed and low power
Class C inverter-based OTA is used in SC filter applications
Youngcheol Chae and Gunhee Han, “Low voltage, low power inverter-based switched-capacitor delta-sigma modulator,” in IEEE J. Solid-State
60
Circuits, vol. 44, no. 2, pp.458-472, Feb. 2009
Class AB Inverter-based Gm-C first order LPF
VDD=1V, GM= 4.6mS, CINT=50fF
DC gain = 30dB, fu=6.3GHz
Parasitic cap degrades fu
Vid=10mV
fin=10MHz
THD=2%
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Linearity Enhancement
Joeri Lechevallier, Remko Struiksma, Hani Sherry, Andreia Cathelin, Eric Klumperink, and Bram Nauta, “A Forward-Body-Bias Tuned 450MHz
Gm-C 3rd-Order Low-Pass Filter in 28nm UTBB FD-SOI with >1dBVp IIP3 over a 0.7-to-1V Supply,” in ISSCC Dig. Tech. Papers, pp.96-97, Feb.
62
2015
Open Challenges
How to enhance inverter’s DC gain
•Cascode and Gain-boosting makes DC gain traded off with output
swing (SFDR)
Tuning without an LDO regulator
•Dropout voltage is bad for low supply voltage
How to deal with PVT variation
•Mismatch leads to PSRR/CMRR aggravation in pseudo-differential
topologies
MHz~GHz frequency tunable filter design for high data rate
communication applications
Hao Luo, Yan Han, Ray C.C. Cheung, Xiaopeng Liu, and Tianlin Cao, “A 0.8-V 230-uW 98-dB DR Inverter-Based SD Modulator for Audio
Applications,” in IEEE J. Solid-State Circuits, vol. 48, no. 10, pp.2430-2441, Oct. 2013
Fawzi Houfaf, Mathieu Egot, Andreas Kaiser, Andreia Cathelin, and Bram Nauta, “A 65nm CMOS 1-to-10GHz Tunable Continuous-Time Lowpass Filter for High-Data-Rate Communications,” in ISSCC Dig. Tech. Papers, pp.362-363, Feb. 2012
Joeri Lechevallier, Remko Struiksma, Hani Sherry, Andreia Cathelin, Eric Klumperink, and Bram Nauta, “A Forward-Body-Bias Tuned 450MHz
Gm-C 3rd-Order Low-Pass Filter in 28nm UTBB FD-SOI with >1dBVp IIP3 over a 0.7-to-1V Supply,” in ISSCC Dig. Tech. Papers, pp.96-97, Feb.
63
2015
A New Look: Digital-based Op-Amp
Motivations
• A step towards Analog Design Automation
• Reduced layout design cycle via commercially available synthesis
tools
Digital Standard Cell-based Op-amp
• Extended concept of an inverter-based OTA
• Programmability with respect to required amplifier specifications
• Fully synthesizable
Jun Liu, Ahmed Fahmy, Taewook Kim, and Nima Maghari, “A Fully Synthesized 0.4V 77dB SFDR Reprogrammable SRMC Filter Using Digital
64
Standard Cells,” in IEEE Custom Integr. Circuits Conf., vol. 27, no. 2, pp.142-153, Sep. 2015
Mapping to NAND/NOR-based Amplifier
Inverters are replaced with NAND/NOR gates for common
mode feedback implementation
Jun Liu, Ahmed Fahmy, Taewook Kim, and Nima Maghari, “A Fully Synthesized 0.4V 77dB SFDR Reprogrammable SRMC Filter Using Digital
65
Standard Cells,” in IEEE Custom Integr. Circuits Conf., vol. 27, no. 2, pp.142-153, Sep. 2015
NAND/NOR-based Amplifier
uOP
A0=23dB, BW=16MHz
CMOS 180nm
 NAND/NOR-based unit amplifier can be used in the pseudo
differential amplifier
Common mode feedback employs an inverter chain
A single stage has low gain BAD
66
Towards a Higher Gain Amplifier
Negative resistance to
enhance output resistance
Feedforward compensation
Cascade the unit amplifiers with feed-forward compensation
for stability
Use negative resistance (cross-coupled tri-state inverters) to
increase voltage gain
67
1st Order LPF using digital gates
GAIN=1
BW=1MHz
R1=100k
RF=100k
CF=1.59p
Lossy Integrator Freq. Response
BW=1MHz at VDD=0.8
mOP Freq. Response
VDD=0.8
68
2nd Order LPF using digital gates
GAIN=1
f0=1MHz
Q=0.7
R1=R2=100k
RF1=70k
CF1=CF2=1.59p
Q=0.65
f0=1MHz at VDD=0.8
69
69
Open Challenges
Placement & Routing automation considering small
mismatch and parasitics
How to design a stable amplifier with high gain from digital
gates
• Frequency compensation
How to deal with PVT variation
• uOP’s bandwidth is sensitive to VDD
70
Analog Active Filters: Outline
• Continuous-Time Filters
– Active-R
– Switched-R
– Ring Oscillator Based
– PWM Based
– Inverter Based OTA-C
– Hybrid Filter CT + DT
71
CT+DT Hybrid Baseband Filter
• DT (Discrete-Time)
Filter
• Pros: good channel
selectivity & stopband
attenuation 
• Cons: poor passband
flatness 
• Solution: add a CT
filter to pre-distort the
input signal
* S.H. Shin, et al., “A 0.7-MHz–10-MHz Hybrid Baseband Chain With Improved Passband Flatness for
LTE Application,” TCAS-I, Vol. 62, No. 1, pp. 244—253, Jan. 2015
72
CT+DT Hybrid Baseband Filter
10
Normalized Gain (dB)
0
-10
-20
-30
-40
-50
-60
-70
CT (2nd order LPF)
Sinc Filter (sampling)
MA-32 DT Filter
CT+DT Response
-1
0
10
10
Normalized Frequency (f )
s
73
Classical
Moving Average FIR
Sinc filter comes from
the sampling behavior
1
1+z-1+z-2+z-3
z-1
z-2
z-3
The output sampling rate (fs.out) is
not the same as the input sampling
rate (fs.in)  can’t CASCADE the
same filter to obtain higher order
Solution: Multi-phase Operation
74
6 phases
MA-32 DT Filter
Charge
Sharing
delayed by clock
75
Thanks to my Ph. D students in the
preparation of this material:
Fernando Lavalle, Adriana Sanabria
Borbon, Hatem Osman, Kyoohyun
Noh, Sergio Soto-Aguilar, Congying
Shi and Minglei Zhang
76