Diagonal 13.4 mm (Type 1/1.2) CMOS solid-state Image Sensor with Square Pixel for
Color Cameras
IMX174LQJ-C
Description
The IMX174LQJ-C is a diagonal 13.4 mm (Type 1/1.2) CMOS active pixel type solid-state image sensor with a
square pixel array and 2.35 M effective pixels. This chip features a global shutter with variable charge-integration
time. This chip operates with analog 3.3 V, digital 1.2 V, and interface 1.8 V triple power supply, and has low power
consumption. High sensitivity, low dark current and low PLS characteristics are achieved through the adoption of R,
G and B primary color mosaic filters.
(Applications: FA cameras, ITS cameras)
c.
Features
In
◆ CMOS active pixel type dots
es
◆ Built-in timing adjustment circuit, H/V driver and serial communication circuit
gi
◆ Global shutter function
lo
◆ Input frequency
37.125 MHz / 74.25 MHz
no
◆ Number of recommended recording pixels: 1920 (H) × 1200 (V) approx. 2.30 M pixels
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Readout mode
WUXGA All-pixel scan mode
UXGA readout mode
1080p-Full HD readout mode
ROI mode
Vertical / Horizontal‐Normal / Inverted readout mode
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◆ Readout rate
Maximum frame rate in WUXGA All-pixel scan mode: 10 bit 164.5 frame/s, 12 bit 128.2 frame/s
◆ Variable-speed shutter function (resolution 1 H units)
◆ 10-bit / 12-bit A/D converter
◆ CDS / PGA function
0 dB to 24 dB: Analog Gain (0.1 dB step)
24.1 dB to 48 dB: Analog Gain: 24 dB + Digital Gain: 0.1 dB to 24 dB (0.1 dB step)
◆ I/O interface
Low voltage LVDS (150 mVp-p) serial (2 ch / 4 ch / 8 ch switching) DDR output
◆ Recommended lens F number: 2.8 or more (Close side)
◆ Recommended exit pupil distance: –100 mm to –∞
Sony reserves the right to change products and specifications without prior notice.
This information does not convey any license by any implication or otherwise under any patents or other right.
Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits.
1
IMX174LQJ-C
Device Structure
◆ CMOS image sensor
◆ Image size
Diagonal 13.4 mm (Type 1/1.2) Approx. 2.35 M pixels WUXGA
Diagonal 11.9 mm (Type 1/1.35) Approx. 1.97 M pixels UXGA
Diagonal 13.0 mm (Type 1/1.23) Approx. 2.12 M pixels 1080p-Full HD
◆ Total number of pixels
1936 (H) × 1226 (V)
Approx. 2.37 M pixels
◆ Number of effective pixels
1936 (H) × 1216 (V)
Approx. 2.35 M pixels
◆ Number of active pixels
1936 (H) × 1216 (V)
Approx. 2.35 M pixels
◆ Number of recommended recording pixels
1920 (H) × 1200 (V)
Approx. 2.30 M pixels WUXGA
1600 (H) × 1200 (V)
Approx. 1.92 M pixels UXGA
1920 (H) × 1080 (V)
Approx. 2.07 M pixels 1080p-Full HD
c.
◆ Unit cell size
5.86 µm (H) × 5.86 µm (V)
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◆ Substrate material
Silicon
In
◆ Optical black
Horizontal (H) direction: Front 0 pixels, rear 0 pixels
Vertical (V) direction: Front 10 pixels, rear 0 pixels
2
IMX174LQJ-C
Absolute Maximum Ratings
Item
Symbol
Rating
Unit
Remarks
Supply voltage (Analog 3.3 V)
AVDD
–0.3
to
+4.0
V
Supply voltage (Interface 1.8 V)
OVDD
–0.3
to
+3.3
V
Supply voltage (Digital 1.2 V)
DVDD
–0.3
to
+2.0
V
Input voltage
VI
–0.3
to
OVDD +0.3
V
Not exceed 3.3 V
Output voltage
VO
–0.3
to
OVDD +0.3
V
Not exceed 3.3 V
Operating temperature
Topr
-30
to
+75
˚C
Storage temperature
Tstg
-40
to
+85
˚C
Performance guarantee temperature
Tspec
-10
to
+60
˚C
Max.
Unit
es
3.30
3.45
V
1.70
1.80
1.90
V
1.20
1.30
V
Supply voltage (Analog 3.3 V)
AVDD
3.15
Supply voltage (Interface 1.8 V)
OVDD
Supply voltage (Digital 1.2 V)
DVDD
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Min.
3
1.10
In
Typ.
Symbol
Item
c.
Recommended Operating Conditions
IMX174LQJ-C
USE RESTRICTION NOTICE
This USE RESTRICTION NOTICE ("Notice") is for customers who are considering or currently using the
image sensor products ("Products") set forth in this specifications book. Sony Corporation ("Sony") may,
at any time, modify this Notice which will be available to you in the latest specifications book for the
Products. You should abide by the latest version of this Notice. If a Sony subsidiary or distributor has its
own use restriction notice on the Products, such a use restriction notice will additionally apply between
you and the subsidiary or distributor. You should consult a sales representative of the subsidiary or
distributor of Sony on such a use restriction notice when you consider using the Products.
In
c.
Use Restrictions
 The Products are intended for incorporation into such general electronic equipment as office products,
communication products, measurement products, and home electronics products in accordance with
the terms and conditions set forth in this specifications book and otherwise notified by Sony from time
to time.
 You should not use the Products for critical applications which may pose a life- or injury-threatening
risk or are highly likely to cause significant property damage in the event of failure of the Products. You
should consult your sales representative beforehand when you consider using the Products for such
critical applications. In addition, you should not use the Products in weapon or military equipment.
 Sony disclaims and does not assume any liability and damages arising out of misuse, improper use,
modification, use of the Products for the above-mentioned critical applications, weapon and military
equipment, or any deviation from the requirements set forth in this specifications book.
ch
no
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Design for Safety
 Sony is making continuous efforts to further improve the quality and reliability of the Products; however,
failure of a certain percentage of the Products is inevitable. Therefore, you should take sufficient care
to ensure the safe design of your products such as component redundancy, anti-conflagration features,
and features to prevent mis-operation in order to avoid accidents resulting in injury or death, fire or
other social damage as a result of such failure.
O
S
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Export Control
 If the Products are controlled items under the export control laws or regulations of various countries,
approval may be required for the export of the Products under the said laws or regulations.
You should be responsible for compliance with the said laws or regulations.
FR
AM
No License Implied
 The technical information shown in this specifications book is for your reference purposes only. The
availability of this specifications book shall not be construed as giving any indication that Sony and its
licensors will license any intellectual property rights in such information by any implication or otherwise.
Sony will not assume responsibility for any problems in connection with your use of such information or
for any infringement of third-party rights due to the same. It is therefore your sole legal and financial
responsibility to resolve any such problems and infringement.
Governing Law
 This Notice shall be governed by and construed in accordance with the laws of Japan, without reference
to principles of conflict of laws or choice of laws. All controversies and disputes arising out of or relating
to this Notice shall be submitted to the exclusive jurisdiction of the Tokyo District Court in Japan as the
court of first instance.
Other Applicable Terms and Conditions
 The terms and conditions in the Sony additional specifications, which will be made available to you when
you order the Products, shall also be applicable to your use of the Products as well as to this
specifications book. You should review those terms and conditions when you consider purchasing
and/or using the Products.
4
IMX174LQJ-C
CONTENTS
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Description ......................................................................................................................................................................1
Features ..........................................................................................................................................................................1
Device Structure ..............................................................................................................................................................2
Absolute Maximum Ratings ..............................................................................................................................................3
Recommended Operating Conditions ...............................................................................................................................3
USE RESTRICTION NOTICE ..........................................................................................................................................4
Chip Center and Optical Center........................................................................................................................................7
Pixel Arrangement ...........................................................................................................................................................8
Block Diagram and Pin Configuration ...............................................................................................................................9
Pin Description .............................................................................................................................................................. 11
Electrical Characteristics ................................................................................................................................................ 13
DC Characteristics ..................................................................................................................................................... 13
Power Consumption ................................................................................................................................................... 13
AC Characteristics...................................................................................................................................................... 14
Master Clock (INCK) Waveform Diagram ................................................................................................................. 14
XVS / XHS Input Characteristics in Slave Mode (XMASTER = High) ......................................................................... 15
XTRIG Input Characteristics in Slave Mode (XMASTER = High) only ........................................................................ 15
Serial Communication ............................................................................................................................................. 16
DLCKP / DLCKM, DLOPx / DLOMx ......................................................................................................................... 17
I/O Equivalent Circuit Diagram ....................................................................................................................................... 18
Spectral Sensitivity Characteristics ................................................................................................................................. 19
Image Sensor Characteristics ........................................................................................................................................ 20
Zone Definition of Video Signal Shading...................................................................................................................... 20
Image Sensor Characteristics Measurement Method ...................................................................................................... 21
Measurement Conditions ............................................................................................................................................ 21
Color Coding of Physical Pixel Array ........................................................................................................................... 21
Definition of standard imaging conditions .................................................................................................................... 21
Measurement Method................................................................................................................................................. 22
Setting Registers Using Serial Communication ............................................................................................................... 23
Description of Setting Registers (4-wire) ..................................................................................................................... 23
Register Communication Timing ................................................................................................................................. 23
Register Write and Read ............................................................................................................................................ 24
Register Map ................................................................................................................................................................. 25
Chip ID = 02 (Write: Chip ID = 02h, Read: Chip ID = 82h) ......................................................................................... 26
Chip ID = 03 (Write: Chip ID = 03h, Read: Chip ID = 83h) ......................................................................................... 32
Chip ID = 04 (Write: Chip ID = 04h, Read: Chip ID = 84h) ......................................................................................... 34
Chip ID = 05 (Write: Chip ID = 05h, Read: Chip ID = 85h) ......................................................................................... 35
Chip ID = 06 (Write: Chip ID = 06h, Read: Chip ID = 86h) ......................................................................................... 35
Chip ID = 07 (Write: Chip ID = 07h, Read: Chip ID = 87h) ......................................................................................... 35
Chip ID = 08 (Write: Chip ID = 08h, Read: Chip ID = 88h) ......................................................................................... 36
Chip ID = 09 (Write: Chip ID = 09h, Read: Chip ID = 89h) ......................................................................................... 36
Readout Drive Modes .................................................................................................................................................... 37
Sync code .................................................................................................................................................................. 38
List of Sync Code .................................................................................................................................................... 38
Sync Code Output Timing ....................................................................................................................................... 38
Image Data Output Format ......................................................................................................................................... 39
WUXGA mode (All-pixel scan) ................................................................................................................................. 39
UXGA mode............................................................................................................................................................ 42
1080p-Full HD mode ............................................................................................................................................... 45
ROI mode ............................................................................................................................................................... 48
Description of Various Function ...................................................................................................................................... 53
Standby mode............................................................................................................................................................ 53
Slave Mode and Master Mode .................................................................................................................................... 54
Gain Adjustment Function ........................................................................................................................................... 55
Black Level Adjustment Function ................................................................................................................................ 56
Horizontal / Vertical Normal Operation and Inverted Operation ..................................................................................... 57
Shutter and Integration Time Settings ......................................................................................................................... 58
Global Shutter (Normal Mode) Operation ................................................................................................................. 59
5
IMX174LQJ-C
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Global Shutter (Tigger Mode) Operation................................................................................................................... 60
Mode Transitions of Global Shutter Operation .......................................................................................................... 62
Pulse Output Function ............................................................................................................................................. 63
Signal Output ............................................................................................................................................................. 65
Output Pin Settings ................................................................................................................................................. 65
Output Pin Bit Width Selection ................................................................................................................................. 67
Output Signal Range ............................................................................................................................................... 67
Register Hold Setting.................................................................................................................................................. 68
Mode Transition ......................................................................................................................................................... 69
Power-on and Power-off Sequence ................................................................................................................................ 70
Power-on sequence ................................................................................................................................................... 70
Power-off Sequence ................................................................................................................................................... 71
Sensor Setting Flow....................................................................................................................................................... 72
Setting Flow in Sensor Slave Mode ............................................................................................................................. 72
Sensor Flow in Sensor Master Mode........................................................................................................................... 73
Peripheral Circuit ........................................................................................................................................................... 74
Power Pins ................................................................................................................................................................ 74
I/O signal pins ............................................................................................................................................................ 75
Spot Pixel Specifications ................................................................................................................................................ 76
Sport Pixel Zone Definition ......................................................................................................................................... 76
Notice on White Pixels Specifications ............................................................................................................................. 77
Measurement Method for Spot Pixels ............................................................................................................................. 78
Spot Pixel Pattern Specification...................................................................................................................................... 79
Marking ......................................................................................................................................................................... 80
Notes On Handling ........................................................................................................................................................ 81
Package Outline ............................................................................................................................................................ 83
List of Trademark Logos and Definition Statements......................................................................................................... 84
6
IMX174LQJ-C
Chip Center and Optical Center
Top View
Package center
Optical center
Package reference (H, V)
20.00 ± 0.1 mm
Package
outline H
direction
10.00 ± 0.075 mm
A1-Pin
16.80 ± 0.1 mm
8.40 ± 0.075 mm
N1-Pin
Package
outline V
direction
es
In
c.
Sensor
scanning V
direction (normal)
A11-Pin
lo
gi
N11-Pin
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Optical Center
7
Sensor
scanning H
direction (normal)
IMX174LQJ-C
Pixel Arrangement
Reference pin
Top View
1200
Total number of pixels:
1936 (H) × 1226 (V) = 2.37 M pixel (WUXGA)
Number of effective pixels: 1936 (H) × 1216 (V) = 2.35 M pixel (WUXGA)
Number of active pixels: 1936 (H) × 1216 (V) = 2.35 M pixel (WUXGA)
Number of recommended recording pixels:
1920 (H) × 1200 (V) = 2.30 M pixel (WUXGA)
1600 (H) × 1200 (V) = 1.92 M pixel (UXGA)
1920 (H) × 1080 (V) = 2.07 M pixel (1080p-Full HD)
Recording pixel area
8
8
8
Effective margin for color processing
4
Vertical (V) direction effective OB
6
OB side ignored area
GG BB
RR G
G
In
Horizontal scan direction (Normal)
lo
gi
N11 pin
1920
es
G
G BB
R
R GG
B
GG
GB
B
G
RRR G
G
Effective margin for color processing
Effective margin for
color processing
8
A1 pin
c.
G BB
G
G B
R G
R
R GG
Effective margin for
color processing
Vertical scan direction (Normal)
N1 pin
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Pixel Arrangement
8
A11 pin
IMX174LQJ-C
Block Diagram and Pin Configuration
(Top View)
Sensor Control Unit
(SCU)
2 ch / 4 ch / 8 ch digital Output
PLL
no
lo
gi
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In
c.
Sensor
Drive Circuit
CDS/Column Circuit
Block Diagram
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CDS/Column Circuit
9
Bias
IMX174LQJ-C
A
1
B
C
D
E
F
G
H
J
K
L
VDDH10
VDDH13
VCP1
VDDH16
VCP2
VDDM1
INCK
VDDM2
VDDM3
VDDH11
VRL1
VRL3
VSSH11
VRL6
VRL7
VSSL6
VSSM1
VSSM2
VSSH5
VRL2
VRL4
VRL5
VSSL3
VSSL4
XCLR
XMASTER
M
NC
N
NC
2
VCAP
VDDH7
3
VDDH1
VDDH8
VDDL4
4
NC
VDDH2
VDDH9
5
NC
NC
VSSL1
VDDL1
VSSL2
VDDL2
VDDL6
VDDL8
NC
SDO
DLOPA
DLOMA
DLOPC
DLOMC
XCE
DLOPB
DLOMB
DLOPD
DLOMD
DLCKP
DLCKM
NC
NC
SDI
DLOPG
DLOMG
DLOPE
DLOME
XTRIG
DLOPH
DLOMH
DLOPF
DLOMF
NC
VDDH3
VSSH1
TOUT1
SCK
Bottom View
6
VDDH4
VSSH2
TOUT2
7
VDDL3
NC
VSSH3
VDDH6
VSSH4
9
VSSH8
VDDL5
VDDL7
XHS
VSSH9
VSSH12
VSSH13
XVS
NC
VSSM4
c.
8
NC
NC
NC
VSSH6
VSSH7
VSSH10
VDDH17
VSSH14
VSSL5
NC
VDDH12
VDDH14
VDDH15
VDDH18
VDDH19
VDDL9
VDDL10
ch
no
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gi
NC
VSSL7
es
10
In
VDDH5
Te
Analog Power Supply (3.3 V)
Analog GND
Interface GND
S
Interface Power Supply (1.8 V)
Digital GND
O
Digital Power Supply (1.2 V)
FR
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11
VSSM3
NC
Clock
Data output
Signal I/O
Pin Configuration
10
NC
NC
VSSL8
VSSL9
VDDL11
VDDL12
NC
NC
IMX174LQJ-C
Pin Description
gi
es
In
c.
―
Reference pin (Connect to a 0.22 µF to GND)
3.3 V power supply
3.3 V power supply
3.3 V power supply
3.3 V power supply
3.3 V power supply
3.3 V power supply
―
3.3 V power supply
3.3 V power supply
3.3 V power supply
3.3 V GND
3.3 V GND
3.3 V GND
3.3 V GND
3.3 V power supply
3.3 V power supply
3.3 V GND
―
―
Pulse1 output pin
Pulse2 output pin
―
―
3.3 V GND
3.3 V power supply
3.3 V power supply
Connect to VCP1
Connect to VCP1
―
1.2 V GND
1.2 V GND
―
―
―
3.3 V GND
3.3 V power supply
Connect to VRL1, 2, 3, 4, 5 (Connect to 4.7 µF × 2 to GND)
Connect to VCP1
Connect to VCP1
―
1.2 V power supply
1.2 V power supply
1.2 V power supply
3.3 V GND
3.3 V GND
3.3 V GND
3.3 V power supply
3.3 V power supply
3.3 V GND
Connect to VCP1
1.2 V power supply
1.2 V power supply
3.3 V GND
3.3 V power supply
3.3 V power supply
Connect to VRL6, 7 (Connect to 4.7 µF × 2 to GND)
Connect to VCP2
1.2 V GND
1.2 V power supply
1.2 V power supply
lo
N.C
VCAP
VDDH1
VDDH2
VDDH3
VDDH4
VDDH5
VDDH6
N.C.
VDDH7
VDDH8
VDDH9
VSSH1
VSSH2
VSSH3
VSSH4
VDDH10
VDDH11
VSSH5
N.C
N.C
TOUT1
TOUT2
N.C
N.C
VSSH6
VDDH12
VDDH13
VRL1
VRL2
N.C
VSSL1
VSSL2
N.C
N.C
N.C
VSSH7
VDDH14
VCP1
VRL3
VRL4
N.C
VDDL1
VDDL2
VDDL3
VSSH8
VSSH9
VSSH10
VDDH15
VDDH16
VSSH11
VRL5
VDDL4
VDDL5
VSSH12
VDDH17
VDDH18
VCP2
VRL6
VSSL3
VDDL6
VDDL7
no
―
O
Power
Power
Power
Power
Power
Power
―
Power
Power
Power
GND
GND
GND
GND
Power
Power
GND
―
―
O
O
―
―
GND
Power
Power
I
I
―
GND
GND
―
―
―
GND
Power
O
I
I
―
Power
Power
Power
GND
GND
GND
Power
Power
GND
I
Power
Power
GND
Power
Power
O
I
GND
Power
Power
Description
ch
A1
A3
A4
A5
A6
A7
A8
A9
A11
B3
B4
B5
B6
B7
B8
B9
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
F1
F2
F3
F4
F8
F9
F10
F11
G1
G2
G3
G4
G8
Symbol
Te
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
Analog
/ Digital
―
A
A
A
A
A
A
A
―
A
A
A
A
A
A
A
A
A
A
―
―
D
D
―
―
A
A
A
A
A
―
D
D
―
―
―
A
A
A
A
A
―
D
D
D
A
A
A
A
A
A
A
D
D
A
A
A
A
A
D
D
D
S
I/O
O
Pin No.
FR
AM
No.
11
IMX174LQJ-C
No.
Pin No.
I/O
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
G9
G10
G11
H1
H2
H3
H4
H8
H9
H10
H11
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
K1
K2
GND
GND
Power
Power
I
GND
Power
I/O
I/O
GND
Power
I
GND
I
O
I
I
I
I
―
GND
Power
Power
GND
Analog
/ Digital
A
A
A
D
A
D
D
D
D
D
D
D
D
D
D
D
D
D
D
―
D
D
D
D
87
K3
I
D
XMASTER
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
K4
K5
K6
K7
K8
K9
K10
K11
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
M3
M4
M5
M6
M7
M8
M9
N1
N3
N4
N5
N6
N7
N8
N9
N11
O
O
―
O
O
―
GND
Power
Power
GND
―
O
O
―
O
O
―
GND
Power
―
O
O
O
O
O
―
―
GND
O
O
O
O
O
GND
―
D
D
―
D
D
―
D
D
D
D
―
D
D
―
D
D
―
D
D
―
D
D
D
D
D
―
―
D
D
D
D
D
D
D
―
DLOPA
DLOPB
N.C
DLOPG
DLOPH
N.C
VSSL8
VDDL11
VDDM3
VSSM2
N.C
DLOMA
DLOMB
N.C
DLOMG
DLOMH
N.C
VSSL9
VDDL12
N.C
DLOPC
DLOPD
DLCKP
DLOPE
DLOPF
N.C
N.C
VSSM3
DLOMC
DLOMD
DLCKM
DLOME
DLOMF
VSSM4
N.C
Description
3.3 V GND
3.3 V GND
3.3 V power supply
1.8 V power supply
Connect to VCP2
1.2 V GND
1.2 V power supply
horizontal sync signal
Vertical sync signal
1.2 V GND
1.2 V power supply
Master clock input
1.2 V GND
System clear (Normal: High = OVDD, Clear: Low = GND)
4-wire serial communication I/F SDO pin
4-wire serial communication I/F XCE pin
4-wire serial communication I/F SCK pin
4-wire serial communication I/F SDI pin
Trigger input
―
1.2 V GND
1.2 V power supply
1.8 V power supply
1.8 V GND
Master / Slave select
(In Slave mode: High = OVDD, In Master mode: Low = GND)
Low voltage LVDS serial output (Data)
Low voltage LVDS serial output (Data)
―
Low voltage LVDS serial output (Data)
Low voltage LVDS serial output (Data)
―
1.2 V GND
1.2 V power supply
1.8 V power supply
1.8 V GND
―
Low voltage LVDS serial output (Data)
Low voltage LVDS serial output (Data)
―
Low voltage LVDS serial output (Data)
Low voltage LVDS serial output (Data)
―
1.2 V GND
1.2 V power supply
―
Low voltage LVDS serial output (Data)
Low voltage LVDS serial output (Data)
Low voltage LVDS serial output (Clock)
Low voltage LVDS serial output (Data)
Low voltage LVDS serial output (Data)
―
―
1.8 V GND
Low voltage LVDS serial output (Data)
Low voltage LVDS serial output (Data)
Low voltage LVDS serial output (Clock)
Low voltage LVDS serial output (Data)
Low voltage LVDS serial output (Data)
1.8 V GND
―
Te
ch
no
lo
gi
es
In
c.
VSSH13
VSSH14
VDDH19
VDDM1
VRL7
VSSL4
VDDL8
XHS
XVS
VSSL5
VDDL9
INCK
VSSL6
XCLR
SDO
XCE
SCK
SDI
XTRIG
N.C
VSSL7
VDDL10
VDDM2
VSSM1
S
O
FR
AM
Symbol
* N.C. pins in the table above should be left open on the board.
12
IMX174LQJ-C
Electrical Characteristics
DC Characteristics
Symbol
Conditions
Min.
Typ.
Max.
Unit
Analog
VDDHx
AVDD
―
3.15
3.30
3.45
V
Interface
VDDMx
OVDD
―
1.70
1.80
1.90
V
Digital
VDDLx
DVDD
―
1.10
1.20
1.30
V
0.8 ×
OVDD
―
―
V
―
―
0.2 ×
OVDD
V
―
OVDD/2
―
V
100
150
210
mV
OVDD -0.4
―
―
V
―
―
0.4
V
XHS
XVS
XCLR
INCK
XMASTER
SCK
SDI
XCE
XTRIG
XVS / XHS
in Slave mode
DLOPx
DLOMx
DCKPx
DCKMx
Digital output voltage
Power Consumption
Operating current
Serial LVDS 8 ch
WUXGA 12 bit 128.2 frame/s
Standby current
Operating current:
(Typical value condition) :
(Maximum value condition) :
Standby current:
(Maximum value condition) :
es
VOH
ch
XVS / XHS
in Master mode
O
S
Te
VOL
DLOP*
DLCKP
Item
Low voltage LVDS
(termination
resistance: 100 Ω)
VOD
FR
AM
LVDS
output
VCM
XHS
XVS
SDO
TOUT1
TOUT2
DLOM*
DLCKM
In
c.
VIL
gi
Digital input voltage
VIH
lo
Supply
voltage
Pins
no
Item
VCM
VOD
Pins
Symbol
Typ.
Max.
Unit
VDDH
IAVDD
141
200
mA
VDDM
IOVDD
21
30
mA
VDDL
IDVDD
122
170
mA
VDDH
IAVDD_STB
―
0.2
mA
VDDM
IOVDD_STB
―
0.2
mA
VDDL
IDVDD_STB
―
12
mA
Supply voltage: 3.30 V / 1.80 V / 1.20 V, Tj = 25 ˚C
Supply voltage: 3.45 V / 1.90 V / 1.30 V, Tj = 60 ˚C
Worst state of internal circuit operating current consumption.
Supply voltage: 3.45 V / 1.90 V / 1.30 V, Tj = 60 ˚C, INCK = 0 V,
The device in the light-obstructed state.
13
IMX174LQJ-C
AC Characteristics
Master Clock (INCK) Waveform Diagram
1/fINCK
0.8 × OVDD
tWHINCK
INCK
0.5 × OVDD
tWLINCK
0.2 × OVDD
tWP
tP
Duty Ratio = tWP / tP × 100
Min.
Typ.
Max.
Unit
Remarks
fINCK
fINCK × 0.96
fINCK
fINCK × 1.02
MHz
fINCK =
37.125 MHz, 74.25 MHz
INCK Low level pulse width
tWLINCK
4
―
―
ns
INCK High level pulse width
tWHINCK
4
―
―
45.0
50.0
lo
gi
INCK clock duty
In
INCK clock frequency
c.
Symbol
es
Item
FR
AM
O
S
Te
ch
no
* The INCK fluctuation affects the frame rate.
14
―
ns
55.0
%
Define with 0.5 × OVDD
IMX174LQJ-C
XVS / XHS Input Characteristics in Slave Mode (XMASTER = High)
0.8 × OVDD
XVS
0.2 × OVDD
tWLXHS
tWHXHS
0.8 × OVDD
XHS
0.2 × OVDD
tHFDLY
tVRDLY
Symbol
Min.
Typ.
Max.
Unit
tWLXHS
4/fINCK
―
―
ns
XHS High level pulse width
tWHXHS
4/fINCK
―
―
ns
XVS - XHS fall width
tHFDLY
1/fINCK
―
―
ns
XHS - XVS rise width
tVRDLY
1/fINCK
―
―
ns
es
In
XHS Low level pulse width
c.
Item
lo
gi
Synchronization cannot be performed from XVS and XHS signal in mater mode. Detect the sync code.
ch
no
XTRIG Input Characteristics in Slave Mode (XMASTER = High) only
Te
HMAX
0.8 × OVDD
XHS
S
0.2 × OVDD
tTGHDLYR
FR
AM
O
tTGHDLYF
0.8 × OVDD
XTRIG
0.2 × OVDD
Item
Symbol
Min.
Typ.
Max.
Unit
XTRIG fall - XHS fall width
tTGHDLYF
10
―
HMAX-10
INCK
XTRIG rise - XHS fall width
tTGHDLYR
10
―
HMAX-10
INCK
15
IMX174LQJ-C
Serial Communication
4-wire
0.8 × OVDD
XCLR
tWLXCLR
0.2 × OVDD
tENINCK
0.8 × OVDD
INCK
0.2 × OVDD
tENXCE
0.8 × OVDD
XCE
tWHXCE
0.2 × OVDD
tSUXCE
tHDXCE
0.8 × OVDD
1/fSCK
SCK
0.2 × OVDD
tHDSDI
c.
tSUSDI
In
0.8 × OVDD
SDI
DATA
DATA
es
0.2 × OVDD
gi
tDLSDO
0.8 × OVDD
SDO
DATA
lo
DATA
Symbol
Max.
Unit
—
—
13.5
MHz
4/fINCK
—
—
ns
tENINCK
1
—
—
µs
XCE effective margin
tENXCE
20
—
—
µs
XCE input setup time
tSUXCE
20
—
—
ns
XCE input hold time
tHDXCE
20
—
—
ns
XCE High level pulse width
tWHXCE
20
—
—
ns
SDI input setup time
tSUSDI
10
—
—
ns
SDI input hold time
tHDSDI
10
—
—
ns
SDO output delay time
tDLSDO
0
—
25
ns
fSCK
XCLR Low level pulse width
tWLXCLR
FR
AM
O
SCK clock frequency
INCK effective margin
Min.
Te
Typ.
S
Item
ch
no
0.2 × OVDD
16
Remarks
Output load capacitance:
20 pF
IMX174LQJ-C
DLCKP / DLCKM, DLOPx / DLOMx
DLCKM
DLCKP
DLCKP –
DLCKM
tSUDO tHDDO
DLOP*
DLOM*
c.
DLOP* –
DLOM*
es
DLO setup time
tSUDO
400
DLO hold time
tHDDO
gi
40
Max.
Unit
Remarks
50
60
%
DCK freq = 297 MHz (Max.)
—
—
ps
Data Rate 297 MHz DDR
—
—
ps
Data Rate 297 MHz DDR
lo
—
400
FR
AM
O
S
DLCK clock duty
Typ.
no
Min.
ch
Symbol
Te
(Output load capacitance: 8 pF)
Item
In
Valid Data
17
IMX174LQJ-C
I/O Equivalent Circuit Diagram
: External pin
Symbol
Equivalent circuit
Symbol
Equivalent circuit
VDDM1
VDDM1
XVS
XHS
INCK
VSSM1
VSSM1
VDDM1
VDDM1
Digital
input
Digital
output
In
c.
SDO
es
XCLR
SDI
SCK
XCE
XMASTER
XTRIG
Digital
I/O
VSSM1
gi
VSSM1
lo
VRL1
VRL2
VRL3
VRL4
VRL5
VRL6
VRL7
no
Analog
I/O
Te
ch
VCP1
VCP2
VSSH3
O
S
VSSH2
Analog
I/O
VDDM2
VDDM3
VCAP
FR
AM
VDDH4
DOPx
DOMx
DCKP
DCKM
Analog
I/O
Data
output
VSSM2
VSSM3
VSSH4
18
IMX174LQJ-C
Spectral Sensitivity Characteristics
(Excludes lens characteristics and light source characteristics.)
Red
Green
Blue
1.0
G
0.9
R
0.7
B
0.6
0.5
0.4
c.
0.3
In
0.2
gi
es
0.1
550
600
650
700
750
Wavelength [nm]
Te
ch
no
500
S
450
O
400
lo
0.0
FR
AM
Relative response [ ]
0.8
19
800
850
900
950
1000
IMX174LQJ-C
Image Sensor Characteristics
(AVDD = 3.3 V, OVDD = 1.8 V, DVDD = 1.2 V, All-pixel scan mode, AD: 12 bit, Tj = 60 ˚C, Gain = 0 dB)
Symbol
Min.
Typ.
Max.
Unit
Measurement
method
S
3768
(850)
4503
(1016)
―
Digit
(mV)
1
R/G
RG
0.42
―
0.57
―
B/G
BG
0.33
―
0.48
―
Vsat2D
3768
(850)
―
―
Digit
(mV)
SH01
―
―
20
%
Item
Sensitivity
Sensitivitiy
ratio
Remarks
1/30 s storage
2
Saturation signal
Video signal shading
3
Zone0 to II'
Zone0, I
4
25
%
Vdt
―
―
0.66
(0.15)
Digit
(mV)
5
1/30 s storage
ΔVdt
―
―
0.66
(0.15)
Digit
(mV)
6
1/30 s storage
7
Zone II'
Sm
dB
es
PLS
(Parasitic Light Sensitivity)
―
c.
Dark signal shading
―
In
Dark signal
SH2D
Zone0 to II'
Te
Zone Definition of Video Signal Shading
ch
no
lo
gi
Note) 1. Converted value into mV using 1Digit = 0.2256 mV for 12-bit output and 1Digit = 0.9023 mV for
10-bit output.
2. The video signal shading is the measured value in the wafer status and does not include characteristics of
the seal glass.
FR
AM
O
S
H = 1936
V/10
V = 1216
H/8
H/8
Zone 0, Ⅰ
V/10
Zone Ⅱ, Ⅱ’
Effective pixel area
20
IMX174LQJ-C
Image Sensor Characteristics Measurement Method
Measurement Conditions
In the following measurements, the device drive conditions are at the typical values of the bias conditions and clock
voltage conditions.
In the following measurements, spot pixels are excluded and, unless otherwise specified, the optical black (OB) level
is used as the reference for the signal output, which is taken as the value of the signal output of the measurement
system.
Color Coding of Physical Pixel Array
Gb
B
R
Gr
R
Gr
Gb
B
Gb
B
R
Gr
R
Gr
In
B
es
Gb
c.
The primary color filters of this image sensor are arranged in the layout shown in the figure below. Gr and Gb
represent the G signal on the same line as the R and B signals, respectively. The Gb signal and B signal lines
and the R signal and Gr signal lines are output successively.
no
lo
gi
Color Coding Diagram
Definition of standard imaging conditions
FR
AM
O
S
Te
ch
◆ Standard imaging condition I:
2
Use a pattern box (luminance: 706 cd/m , color temperature of 3200 K halogen source) as a subject. (Pattern for
evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0 mm) as an IR cut filter and image at
F5.6. The luminous intensity to the sensor receiving surface at this point is defined as the standard sensitivity
testing luminous intensity.
◆ Standard image condition II:
Image a light source (color temperature of 3200 K) with a uniformity of brightness within 2 % at all angles. Use a
testing standard lens with CM500S (t = 1.0 mm) as an IR cut filter. The luminous intensity is adjusted to the value
indicated in each testing item by the lens diaphragm.
◆ Standard image condition III:
Image a light source (color temperature of 3200 K) with a uniformity of brightness within 2 % at all angles. Use a
testing standard lens (exit pupil distance -100 mm) with CM500S (t = 1.0 mm) as an IR cut filter. The luminous
intensity is adjusted to the value indicated in each testing item by the lens diaphragm.
21
IMX174LQJ-C
Measurement Method
1.
Sensitivity
Set the measurement condition to the standard imaging condition I. After setting the electronic shutter mode
with a shutter speed of 1/100 s, measure the Gr and Gb signal outputs (VGr, VGb) at the center of the screen,
and substitute the values into the following formula.
S = (VGr + VGb) / 2 × 100/30 [mV]
2.
Sensitivity ratio
Set the measurement condition to the standard imaging condition II. After adjusting the average value of the Gr
and Gb signal outputs to 1016 mV, measure the R signal output (VR [mV]), the Gr and Gb signal outputs (VGr,
VGb [mV]) and the B signal output (VB [mV]) at the center of the screen in frame readout mode, and substitute
the values into the following formulas.
VG = (VGr + VGb) / 2
RG = VR / VG
BG = VB / VG
Saturation signal
Set the measurement condition to the standard imaging condition II. After adjusting the luminous intensity to 20
times the intensity with the average value of the Gr and Gb signal outputs, 1016 mV, measure the minimum
values of the Gr, Gb, R and B signal outputs.
4.
Video signal shading
Set the measurement condition to the standard imaging condition III. With the lens diaphragm at F2.8, adjust
the luminous intensity so that the average value of the Gr and Gb signal outputs are 1016 mV. Then measure
the maximum value (Gmax [mV]) and the minimum value (Gmin [mV]) of the Gr and Gb signal outputs, and
substitute the values into the following formula.
Te
ch
SH = (Gmax – Gmin) / 1016 × 100 [%]
no
lo
gi
es
In
c.
3.
Dark signal
With the device junction temperature of 60 ˚C and the device in the light-obstructed state, divide the output
difference between 1/30 s integration and 1/300 s integration by 0.9, and calculate the signal output converted
to 1/30 s integration. Measure the average value of this output (Vdt [mV]).
6.
Dark signal shading
After the measurement item 4, measure the maximum value (Vdmax [mV]) and the minimum value (Vdmin
[mV]) of the dark signal output, and substitute the values into the following formula.
FR
AM
O
S
5.
ΔVdt = Vdmax – Vdmin [mV]
7.
PLS
Set the measurement condition to the standard imaging condition II, the Gr and Gb output signal Vave
measured by standard image condition. Then, adjust the luminous intensity to 500 times the intensity with
average value of the Gr and Gb signal output, Vave. When the charge drain is executed be the electronic
shutter and the condition that not be readout from photo diode to analog memory, readout by dropping to 1/113
frame rate.
Sm = 20 × log ((Vsm/Vave) × (1/500) × (1/113)) [dB]
22
IMX174LQJ-C
Setting Registers Using Serial Communication
Description of Setting Registers (4-wire)
The serial data input order is LSB-first transfer. The table below shows the various data types and descriptions.
Serial Data Transfer Order
Chip ID
(8 bit)
Start address
(8 bit)
Data
(8 bit)
Data
(8 bit)
Data
(8 bit)
…
(8 bit)
Type and Description
Type
es
lo
Data
gi
Address
In
c.
Chip ID
Description
Chip ID: 02 Write: 02h / Read: 82h
Chip ID: 03 Write: 03h / Read: 83h
Chip ID: 04 Write: 04h / Read: 84h
Chip ID: 05 Write: 05h / Read: 85h
Chip ID: 06 Write: 06h / Read: 86h
Chip ID: 07 Write: 07h / Read: 87h
Chip ID: 08 Write: 08h / Read: 88h
Chip ID: 09 Write: 09h / Read: 89h
Designate the address according to the Register Map. When using a communication method
that designates continuous addresses, the address is automatically incremented from the
previously transmitted address.
Input the setting values according to the Register Map.
no
Register Communication Timing
FR
AM
O
S
Te
ch
Perform serial communication in sensor standby mode or within communication period. For the registers marked "V"
in the item of Reflection timing, when the communication is performed in the communication period shown in the
figure below they are reflected by frame reflection timing. For the registers noted “Immediately” in the item of
Reflection timing, the settings are reflected when the communication is performed. (For the immediate reflection
registers, set them in sensor standby state.)
Frame reflection register
reflection timing
Recommended
serial communication period
Communication prohibited period
WUXGA/UXGA: 10XHS period / HD1080p: 6XHS
XVS
Global Shutter
(Normal mode)
XHS
Data line
Blank line
Data line
Frame reflection register
reflection timing
Recommended
serial communication period
Communication prohibited period
WUXGA/UXGA: 10XHS period / HD1080p: 6XHS
XTRIG
Global Shutter
(Trigger mode)
XHS
Blank line
23
Data line
IMX174LQJ-C
Register Write and Read
◆ Follow the communication procedure below when writing registers.
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Set XCE Low to enable the chip's communication function. Serial data input is executed using SCK and SDI.
Transmit data in sync with SCK 1 bit at a time from the LSB using SDI. Transfer SDI in sync with the falling
edge of SCK. (The data is loaded at the rising edge of SCK.)
Input the Chip ID (CID = 02h to 09h) to the first byte. If the Chip ID differs, subsequent data is ignored.
Input the start address to the second byte. The address is automatically incremented.
Input the data to the third and subsequent bytes. The data in the third byte is written to the register address
designated by the second byte, and the register address is automatically incremented thereafter when
writing the data for the fourth and subsequent bytes. Normal register data is loaded to the inside of the
sensor and established in 8-bit units.
The register values starting from the register address designated by the second byte are output from the
SDO pin. The register values before the write operation are output. The actual register values are the input
data.
Set XCE High to end communication.
◆ Follow the communication procedure below when reading registers.
c.
In
es
ch
(7)
gi
(6)
lo
(3)
(4)
(5)
Set XCE Low to enable the chip's communication function. Serial data input is executed using SCK and SDI.
Transmit data in sync with SCK 1 bit at a time from the LSB using SDI. Transfer SDI in sync with the falling
edge of SCK. (The data is loaded at the rising edge of SCK.)
Input Chip ID (CID = 82h to 89h) to the first byte. If the Chip ID differs, subsequent data is ignored.
Input the start address to the second byte. The address is automatically incremented.
Input data to the third and subsequent bytes. Input dummy data in order to read the registers. The dummy
data is not written to the registers. To read continuous data, input the necessary number of bytes of dummy
data.
The register values starting from the register address designated by the second byte are output from the
SDO pin. The input data is not written, so the actual register values are output.
Set XCE High to end communication.
no
(1)
(2)
O
S
Te
Note) When writing data to multiple registers with discontinuous addresses, access to undesired registers
can be avoided by repeating the above procedure multiple times.
FR
AM
XCE
SCK
SDI
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
SDO
0 1 2 3 4 5 6 7
Data established timing
Chip ID
Start address
N bytes of data
Serial Communication (Continuous Addresses)
XCE
SCK
SDI
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
SDO
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
Data established timing
Chip ID
Start address
N bytes of data
Chip ID
Serial Communication (Discontinuous Addresses)
24
Start address
N bytes of data
IMX174LQJ-C
Register Map
This sensor has a total of 2048 bytes of registers, composed of registers with address 00h to FEh that correspond to
Chip ID = 02h to 09h. Use the initial values for empty address. Some registers must be change from the initial values,
so the sensor control side should be capable of setting 2048 bytes.
There are two different register reflection timing. Values are reflected immediately after writing to register noted as
“Immediately”, or at the frame reflection register reflection timing described in the item of “Register Communication
Timing” in the section of “Setting Registers with Serial Communication” for registers noted as “V” in the Reflection
timing column of the Register Map. For the immediate reflection registers below, set them in sensor standby state.
・STBLVDS
・ADBIT
・ODBIT
・OPORTSEL
・INCKSEL0
・INCKSEL1
・INCKSEL2
・INCKSEL3
In
c.
For the register that is writing "*" to the setting value in description, change the value from the default value after the
reset.
FR
AM
O
S
Te
ch
no
lo
gi
es
Do not perform communication to addresses not listed in the Register Map. Doing so may result in operation errors.
25
IMX174LQJ-C
Chip ID = 02 (Write: Chip ID = 02h, Read: Chip ID = 82h)
Bit
2
Fixed to 0
0
3
Fixed to 0
0
4
5
Fixed to 0
Fixed to 0
0
0
―
―
6
Fixed to 0
0
―
7
Fixed to 0
0
[7:0]
to
[7:0]
―
01h
―
―
00h
to
00h
―
―
―
2
Fixed to 0
0
―
3
Fixed to 0
0
4
5
LVDS channels that not using be standby
0h: 8 ch active
1h: 4 ch active
2h: 2 ch active
Others: Setting prohibited
0h
STBLVDS [3:0]
In
[7:0]
to
[7:0]
gi
Fixed to 00h
00h
to
00h
00h
―
Immediately
00h
to
00h
―
Register hold
(Function not to update V reflection registers)
0: Invalid 1: Valid
0
Immediately
1
Fixed to 0
0
―
2
3
Fixed to 0
Fixed to 0
4
Fixed to 0
0
―
Fixed to 0
0
―
Fixed to 0
Fixed to 0
0
0
―
―
lo
REGHOLD [0]
ch
Te
O
FR
AM
[7:0]
to
[7:0]
S
6
7
0
0
00h
to
00h
Fixed to 00h
00h
00h
to
00h
―
―
―
Setting of master mode operation
0: Master mode operation start
1: Master mode operation stop
1
Immediately
1
Fixed to 0
0
―
2
Fixed to 0
0
3
4
Fixed to 0
Fixed to 0
0
0
5
Fixed to 0
0
―
6
Fixed to 0
0
―
7
Fixed to 0
Global shutter mode setting
0: Normal mode 1: Trigger mode
0
―
0
Immediately
1
Fixed to 0
0
―
2
3
Fixed to 0
Fixed to 0
0
0
4
Fixed to 0
0
―
5
Fixed to 0
0
―
6
7
Fixed to 0
Fixed to 0
0
0
―
―
0
0
13h
―
0
0
5
12h
0
Fixed to 0
Fixed to 0
0
0Dh
to
11h
Immediately
00h
to
00h
Fixed to 00h
7
0Ch
1
0
1
6
06h
to
0Bh
1: Standby
c.
05h
Reflection
timing
1
STANDBY [0]
es
01h
to
04h
Description
Standby mode
0: Normal operation
Fixed to 0
0
00h
Register Name
no
Address
Default value
after reset
By
By
register
address
XMSTA [0]
TRIGEN [0]
26
01h
00h
―
―
―
―
―
IMX174LQJ-C
Bit
0
3
Fixed to 0
0
4
5
Fixed to 0
Fixed to 0
0
0
―
―
6
Fixed to 0
0
―
7
Fixed to 0
0
―
Drive mode setting
0h: WUXGA 2h: UXGA 4h: 1080p-Full HD
Others: Setting prohibited
0h
V
4
5
Fixed to 0
Fixed to 0
0
0
6
Fixed to 0
0
―
7
Fixed to 0
0
―
0
VREVERSE [0]
Vertical (V) direction readout inversion control
0: Normal 1: Inverted
0
V
1
HREVERSE [0]
0
V
MODE [3:0]
3
3
Fixed to 0
4
Fixed to 0
5
6
Fixed to 0
Fixed to 0
7
Fixed to 0
0
LSB
3
4
5
6
es
gi
lo
When sensor master mode
vertical span setting.
(Number of operation lines count from 1)
Immediately
0
―
0
0
―
01h
00h
00h
―
―
―
―
―
0
―
0
0
―
―
0
―
E6h
4E6h
V
O
S
VMAX [11:0]
FR
AM
1
2
1
ch
4
7
7
19h
Te
3
0
In
c.
2
Horizontal (H) direction readout inversion control
0: Normal 1: Inverted
Fixed to 0
5
6
18h
Reflection
timing
Fixed to 0
ADBIT [0]
1
2
17h
By
address
2
2
16h
By
register
1
0
1
15h
Description
AD conversion bits setting
0: 10 bit 1: 12 bit
Fixed to 0
0
14h
Register Name
no
Address
Default value
after reset
MSB
Fixed to 0
0
Fixed to 0
Fixed to 0
0
0
Fixed to 0
[7:0]
00h
―
―
―
―
0
Fixed to 00h
0
1
04h
00h
―
LSB
2
1Ah
3
CEh
4
5
6
7
0
1
HMAX [15:0]
When sensor master mode
horizontal span setting.
(Number of operation clocks count from 1)
01CEh
V
2
1Bh
3
01h
4
5
6
7
MSB
27
IMX174LQJ-C
Bit
1
2
Fixed to 0
0
3
Fixed to 0
0
4
5
1h
6
Output channel selection
1h: 8 ch 3h: 4 ch 4h: 2 ch
Others: Setting prohibited
7
Fixed to 0
OPORTSEL [2:0]
Reflection
timing
1
Immediately
0
―
―
11h
01h
02h
―
Immediately
―
01h
02h
―
―
0
Immediately
1
Fixed to 0
0
―
2
Fixed to 0
0
3
4
Fixed to 0
Fixed to 0
0
0
5
Fixed to 0
0
―
6
Fixed to 0
0
―
CKSEL [0]
Set to data rate.
Fixed to 0
Fixed to 0
4
Fixed to 0
5
Fixed to 0
6
7
Fixed to 0
Fixed to 0
22h
to
27h
28h
[7:0]
to
[7:0]
[7:0]
29h
to
2Dh
[7:0]
to
[7:0]
ch
2
3
es
FREQ [1:0]
Te
1
Fixed to 0
Fixed to 01h
In
7
[7:0]
c.
The value is set according to drive mode.
When WUXGA, UXGA, ROI: 0
When 1080p-Full HD: 1
0
21h
By
address
0
Fixed to 00h *
Fixed to 02h
gi
20h
ODBIT [0]
[7:0]
[7:0]
0
1Fh
By
register
lo
1Dh
1Eh
Description
Number of output bit setting
0: 10 bit 1: 12 bit
Fixed to 0
0
1Ch
Register Name
no
Address
Default value
after reset
0
01h
00h
01h
―
―
―
―
―
0h
V
0
0
―
―
0
00h
―
0
―
0
0
―
―
―
―
―
Fixed to 30h *
01h
01h
V
Do not rewrite
―
―
―
XVSOUTSEL[1:0]
XVS pin setting
0h: Slave mode 2h: Master mode
2h
XHSOUTSEL[1:0]
XHS pin setting
0h: Slave mode 2h: Master mode
2h
4
Fixed to 0
0
5
Fixed to 0
0
―
6
7
Fixed to 0
Fixed to 0
0
0
―
―
TOUT1SEL[1:0]
TOUT1 pin setting
0h: Low fixed 3h: Pulse output
0h
Immediately
TOUT2SEL[1:0]
TOUT2 pin setting
0h: Low fixed 3h: Pulse output
0h
4
Fixed to 0
0
5
Fixed to 0
0
―
6
7
Fixed to 0
Fixed to 0
0
0
―
―
30h
0
Fixed to 00h
00h
00h
―
31h
0
Fixed to 00h
00h
00h
―
1
2Eh
2
3
0
1
2Fh
2
3
0
1
O
FR
AM
0
S
Do not rewrite
TRIG_TOUT1_SEL[2:0]
2
32h
3
4
5
6
7
TRIG_TOUT2_SEL[2:0]
Immediately
Immediately
0Ah
―
Immediately
00h
―
TOUT1 pin setting
0h: Low fixed 1h: Pulse1 output
0h
Fixed to 0
0
TOUT2 pin setting
0h: Low fixed 2h: Pulse2 output
0h
Immediately
Fixed to 0
0
―
28
Immediately
00h
―
IMX174LQJ-C
Address
Bit
33h
to
75h
[7:0]
to
[7:0]
76h
Register Name
Default value
after reset
Description
Do not rewrite
0
PULSE1_EN_NOR [0]
1
PULSE1_EN_TRIG [0]
2
PULSE1_POL [0]
Pulse1 output in normal mode
0: Disable 1: Enable
Pulse1 output in trigger mode
0: Disable 1: Enable
By
register
By
address
―
―
Reflection
timing
―
0
Immediately
0
Immediately
3
Pulse1 polarity selection
0: High active 1: Low active
Fixed to 0
0
―
4
Fixed to 0
0
―
5
Fixed to 0
0
―
6
7
Fixed to 0
Fixed to 0
0
0
―
―
0
LSB
0
00h
Immediately
1
77h
2
3
00h
4
Pulse1 active period start timing setting
Designated in line units from reference point
(For details, see the “Pulse Output Function”)
In
0
PULSE1_UP [15:0]
1
gi
2
3
4
6
7
MSB
Fixed to 00h
0
5
6
7
0
1
2
7Bh
―
S
O
4
FR
AM
3
00h
LSB
1
2
7Ah
00h
Te
[7:0]
ch
no
5
79h
Immediately
00h
lo
78h
0000h
es
6
7
c.
5
PULSE1_DN [15:0]
00h
Pulse1 active period end timing setting
Designated in line units from readout start
(For details, see the “Pulse Output Function”)
0000h
3
Immediately
00h
4
5
6
7
MSB
7Ch
[7:0]
Fixed to 00h
00h
00h
―
7Dh
[7:0]
Fixed to 00h
00h
00h
―
29
IMX174LQJ-C
Address
7Eh
Bit
Register Name
0
PULSE2_EN_NOR [0]
1
PULSE2_EN_TRIG [0]
2
PULSE2_POL [0]
Default value
after reset
Description
By
register
Pulse2 output in normal mode
0: Disable 1: Enable
Pulse2 output in trigger mode
0: Disable 1: Enable
By
address
Reflection
timing
0
Immediately
0
Immediately
Pulse2 polarity selection
0: High active 1: Low active
0
3
Fixed to 1 *
0
―
4
Fixed to 0
0
―
5
6
Fixed to 0
Fixed to 0
0
0
―
―
7
Fixed to 0
0
―
0
LSB
00h
Immediately
1
2
7Fh
3
00h
4
5
6
0
Pulse2 active period start timing setting
Designated in line units from reference point
(For details, see the “Pulse Output Function”)
PULSE2_UP [15:0]
4
gi
Fixed to 00h
LSB
Te
2
3
3
4
5
FR
AM
83h
O
6
2
00h
―
00h
S
4
5
0
1
00h
ch
0
1
7
lo
MSB
[7:0]
no
7
82h
00h
es
3
5
6
81h
Immediately
In
1
2
80h
0000h
c.
7
PULSE2_DN [15:0]
Pulse2 active period end timing setting
Designated in line units from reference point
(For details, see the “Pulse Output Function”)
0000h
Immediately
00h
6
7
MSB
00h
00h
―
―
―
―
Set according to INCK frequency and drive mode.
Set according to INCK frequency and drive mode.
20h
00h
20h
00h
Immediately
Immediately
INCKSEL2 [7:0]
Set according to INCK frequency and drive mode.
20h
20h
Immediately
INCKSEL3 [7:0]
Set according to INCK frequency and drive mode.
00h
00h
Immediately
[7:0]
[7:0]
Fixed to 00h
Fixed to 00h
00h
00h
00h
00h
―
―
98h
[7:0]
Fixed to 00h
00h
00h
―
99h
[7:0]
Fixed to 00h
00h
00h
―
84h
85h
to
91h
[7:0]
[7:0]
to
[7:0]
Fixed to 00h
92h
93h
[7:0]
[7:0]
INCKSEL0 [7:0]
INCKSEL1 [7:0]
94h
[7:0]
95h
[7:0]
96h
97h
Do not rewrite
30
IMX174LQJ-C
Address
Bit
Register Name
Default value
after reset
Description
0
By
register
By
address
Reflection
timing
LSB
1
2
9Ah
3
0Ah
4
5
6
Itegration time adjustment
Designated in line unit
SHS [11:0]
00Ah
V
7
0
1
2
9Bh
3
MSB
4
Fixed to 0
0
5
6
Fixed to 0
Fixed to 0
0
0
7
Fixed to 0
00h
―
―
―
―
0
[7:0]
Fixed to 00h
00h
00h
―
9Dh
9Eh
[7:0]
[7:0]
Fixed to 6Eh
Fixed to 02h
6Eh
02h
6Eh
02h
―
―
9Fh
[7:0]
Fixed to 00h
00h
00h
―
A0h
[7:0]
The value is set according to drive mode.
When WUXGA, UXGA, ROI: A4h
When 1080p-Full HD: 64h
A4h
A4h
Immediately
A1h
[7:0]
Fixed to 02h
02h
02h
―
A2h
[7:0]
Fixed to 01h
01h
01h
―
A3h
A4h
[7:0]
[7:0]
Fixed to 00h
Fixed to 00h
00h
00h
00h
00h
―
―
A5h
[7:0]
08h
08h
Immediately
A6h
to
A8h
[7:0]
to
[7:0]
―
―
―
A9h
[7:0]
0Ch
0Ch
V
AAh
to
BBh
[7:0]
to
[7:0]
―
―
―
BCh
BDh
[7:0]
[7:0]
10 bit: Fixed to 30h / 12 bit: Fixed to 10h *
Do not rewrite
A0h
―
A0h
―
Immediately
―
BEh
[7:0]
Fixed to 45h *
3Eh
3Eh
Immediately
BFh
[7:0]
10 bit: Fixed to 40h / 12 bit: Fixed to 20h *
00h
00h
Immediately
C0h
C1h
[7:0]
[7:0]
10 bit: Fixed to 01h / 12 bit: Fixed to 02h *
Do not rewrite
00h
―
00h
―
Immediately
―
C2h
[7:0]
Fixed to A0h *
20h
20h
Immediately
C3h
to
C5h
[7:0]
to
[7:0]
Do not rewrite
―
―
―
C6h
[7:0]
10 bit: Fixed to 01h / 12 bit: Fixed to 03h *
03h
03h
Immediately
C7h
to
D1h
[7:0]
to
[7:0]
Do not rewrite
―
―
―
D2h
[7:0]
10 bit: Fixed to 05h / 12 bit: Fixed to 0Fh *
0Fh
0Fh
Immediately
D3h
to
D6h
[7:0]
to
[7:0]
Do not rewrite
―
―
―
D7h
D8h
to
FFh
[7:0]
[7:0]
to
[7:0]
Fixed to 00h *
01h
01h
Immediately
Do not rewrite
―
―
―
gi
lo
no
GTWAIT [7:0]
es
In
c.
9Ch
The value is set according to drive mode.
When WUXGA, UXGA, ROI: 08h
When 1080p-Full HD: 04h
Te
ch
GSDLY [7:0]
Do not rewrite
FR
AM
O
S
LVDS output timing
8ch: 0Ch 4ch: 18h 2ch: 30h
Do not rewrite
31
IMX174LQJ-C
Chip ID = 03 (Write: Chip ID = 03h, Read: Chip ID = 83h)
Address
00h
01h
02h
03h
04h
Bit
Register Name
0
ROIH1ON [0]
1
ROIV1ON [0]
[7:2]
[7:0]
Default value
after reset
By
By
register
address
Description
The horizontal setting of ROI area (1, y) (y = 1 to 4)
0: Disable 1: Enable
The vertical setting of ROI area (x, 1) (x = 1 to 4)
0: Disable 1: Enable
Fixed to 00h
000h
[7:3]
Fixed to 00h
00h
[7:0]
[2:0]
Designation of vertical cropping position
on area (x, 1) (x = 1 to 4)
000h
00h
[2:0]
ROIPH1 [10:0]
ROIPV1 [10:0]
Fixed to 00h
[7:0]
06h
[2:0]
[7:3]
Designation of horizontal cropping size
on area (1, y) (y = 1 to 4)
07h
[7:0]
ROIWV1 [10:0]
ROIV2ON [0]
Fixed to 00h
The horizontal setting of ROI area (2, y) (y = 1 to 4)
0: Disable 1: Enable
The vertical setting of ROI area (x, 2) (x = 1 to 4)
0: Disable 1: Enable
Fixed to 00h
In
1
[7:2]
0Dh
0Eh
0Fh
[7:3]
[7:0]
ROIPH2 [10:0]
0
Fixed to 00h
00h
000h
[7:3]
Fixed to 00h
00h
[7:0]
[2:0]
Designation of horizontal cropping size
on area (2, y) (y = 1 to 4)
000h
00h
ROIPV2 [10:0]
ROIWH2 [10:0]
Fixed to 00h
[7:0]
[2:0]
[7:3]
000h
11h
Designation of vertical cropping size
on area (x, 2) (x = 1 to 4)
Fixed to 00h
00h
14h
O
0
ROIH3ON [0]
1
ROIV3ON [0]
[7:2]
13h
ROIWV2 [10:0]
FR
AM
12h
[7:0]
[2:0]
S
[7:3]
10h
ROIPH3 [10:0]
The horizontal setting of ROI area (3, y) (y = 1 to 4)
0: Disable 1: Enable
The vertical setting of ROI area (x, 3) (x = 1 to 4)
0: Disable 1: Enable
Fixed to 00h
000h
00h
[7:3]
Fixed to 00h
[7:0]
[2:0]
[7:3]
000h
16h
Designation of vertical cropping position
on area (x, 3) (x = 1 to 4)
Fixed to 00h
00h
17h
[7:0]
18h
19h
1Ah
[2:0]
[7:3]
[7:0]
[2:0]
[7:3]
ROIWH3 [10:0]
ROIWV3 [10:0]
00h
00h
00h
00h
00h
00h
Designation of horizontal cropping size
on area (3, y) (y = 1 to 4)
000h
Fixed to 00h
00h
Designation of vertical cropping size
on area (x, 3) (x = 1 to 4)
000h
Fixed to 00h
00h
32
V
―
Immediately
―
V
―
Immediately
―
V
00h
Immediately
―
00h
00h
00h
00h
00h
00h
00h
00h
V
―
Immediately
―
V
―
Immediately
―
V
00h
Immediately
―
00h
Designation of horizontal cropping position
on area (3, y) (y = 1 to 4)
15h
ROIPV3 [10:0]
00h
0
0
Immediately
―
00h
00h
Designation of vertical cropping position
on area (x, 2) (x = 1 to 4)
[2:0]
00h
0
000h
no
0Ch
[2:0]
00h
Designation of horizontal cropping position
on area (2, y) (y = 1 to 4)
ch
0Bh
[7:0]
Te
0Ah
000h
es
ROIH2ON [0]
00h
Designation of vertical cropping size
on area (x, 1) (x = 1 to 4)
gi
0
Fixed to 00h
c.
[7:3]
000h
lo
[2:0]
ROIWH1 [10:0]
V
00h
[7:3]
09h
0
Designation of horizontal cropping position
on area (1, y) (y = 1 to 4)
05h
08h
0
Reflection
timing
00h
00h
00h
00h
00h
00h
00h
00h
V
―
Immediately
―
V
―
Immediately
―
IMX174LQJ-C
Address
Bit
0
1Bh
1
Register Name
Description
1Dh
[7:0]
[2:0]
By
register
The horizontal setting of ROI area (4, y) (y = 1 to 4)
0: Disable 1: Enable
The vertical setting of ROI area (x, 4) (x = 1 to 4)
0: Disable 1: Enable
ROIH4ON [0]
ROIV4ON [0]
[7:2]
1Ch
Default value
after reset
ROIPH4 [10:0]
0
0
Fixed to 00h
00h
Designation of horizontal cropping position
on area (4, y) (y = 1 to 4)
000h
00h
[7:3]
Fixed to 00h
1Eh
[7:0]
[2:0]
[7:3]
000h
1Fh
Designation of vertical cropping position
on area (x, 4) (x = 1 to 4)
Fixed to 00h
00h
20h
[7:0]
Fixed to 00h
00h
Designation of vertical cropping size
on area (x, 4) (x = 1 to 4)
000h
[7:3]
Fixed to 00h
00h
[7:0]
to
[7:0]
Do not rewrite
―
no
lo
gi
es
In
c.
ROIWV4 [10:0]
ch
[2:0]
Te
24h
to
FFh
000h
S
23h
[7:3]
[7:0]
ROIWH4 [10:0]
O
22h
[2:0]
Designation of horizontal cropping size
on area (4, y) (y = 1 to 4)
FR
AM
21h
ROIPV4 [10:0]
33
By
address
Reflection
timing
V
00h
Immediately
―
00h
00h
00h
00h
00h
00h
00h
00h
―
V
―
Immediately
―
V
―
Immediately
―
―
IMX174LQJ-C
Chip ID = 04 (Write: Chip ID = 04h, Read: Chip ID = 84h)
Register Name
Default value
after reset
By
By
register
address
Bit
00h
[7:0]
Fixed to 01h
01h
01h
―
01h
02h
[7:0]
[7:0]
Fixed to 00h
Fixed to F0h
00h
F0h
00h
F0h
―
―
03h
[7:0]
Fixed to 00h
00h
00h
―
0
Description
Reflection
timing
Address
LSB
1
2
04h
3
4
Gain setting
0 dB (000d) to 48 dB (480d)
0.1 dB Step
GAIN [8:0]
5
6
000h
00h
V
7
Fixed to 0
Fixed to 0
0
0
3
Fixed to 0
0
4
Fixed to 0
0
5
6
Fixed to 0
Fixed to 0
0
0
―
―
7
Fixed to 0
0
―
c.
MSB
1
2
In
05h
0
[7:0]
to
[7:0]
Do not rewrite
12h
[7:0]
10 bit: Fixed to 40h / 12 bit: Fixed to 20h *
13h
14h
to
19h
[7:0]
[7:0]
to
[7:0]
10 bit: Fixed to 40h / 12 bit: Fixed to 20h *
1Ah
1Bh
to
57h
[7:0]
[7:0]
to
[7:0]
0
10 bit: Fixed to 0Fh / 12 bit: Fixed to 08h *
3
4
5
6
59h
5Ah
to
FFh
gi
lo
00h
―
―
―
―
―
00h
00h
V
00h
00h
V
―
―
―
0Fh
0Fh
Immediately
―
―
―
S
Do not rewrite
O
LSB
FR
AM
58h
no
Te
ch
Do not rewrite
1
2
es
06h
to
11h
―
―
BLKLEVEL [8:0]
Black level offset value setting
Recommended value:
60d (10 bit), 240d (12 bit)
0F0h
F0h
V
7
0
MSB
1
Fixed to 0
0
―
2
Fixed to 0
0
―
3
4
Fixed to 0
Fixed to 0
0
0
5
Fixed to 0
0
―
6
Fixed to 0
0
―
7
[7:0]
to
[7:0]
Fixed to 0
0
―
Do not rewrite
―
34
00h
―
―
―
―
IMX174LQJ-C
Chip ID = 05 (Write: Chip ID = 05h, Read: Chip ID = 85h)
Default value
Address
00h
bit
Register Name
after reset
Description
Reflection
timing
By
By
register
address
Do not rewrite
―
―
―
[7:0]
to
to
66h
[7:0]
67h
[7:0]
Fixed to 04h *
34h
34h
Immediately
68h
[7:0]
10 bit: Fixed to 22h / 12 bit: Fixed to 11h *
46h
46h
Immediately
69h
[7:0]
Do not rewrite
―
―
―
Fixed to 05h *
00h
00h
Immediately
Do not rewrite
―
―
―
Immediately
to
to
6Bh
[7:0]
6Ch
[7:0]
6Dh
[7:0]
to
[7:0]
73h
[7:0]
Fixed to 0Ch *
2Ch
2Ch
74h
[7:0]
Do not rewrite
―
―
―
75h
[7:0]
10 bit: Fixed to 0Bh / 12 bit: Fixed to 0Fh *
13h
13h
Immediately
76h
[7:0]
―
―
―
00h
00h
Immediately
―
―
―
[7:0]
90h
[7:0]
to
[7:0]
Fixed to 7Ch *
Do not rewrite
no
to
FFh
In
8Fh
Do not rewrite
es
[7:0]
gi
to
8Eh
lo
to
c.
to
72h
bit
Register Name
Description
[7:0]
to
to
FFh
[7:0]
FR
AM
00h
O
S
Address
Te
ch
Chip ID = 06 (Write: Chip ID = 06h, Read: Chip ID = 86h)
Do not rewrite
Default value
after reset
Reflection
By
By
register
address
―
―
timing
―
Chip ID = 07 (Write: Chip ID = 07h, Read: Chip ID = 87h)
Default value
Address
00h
Bit
Register Name
Description
after reset
Reflection
timing
By
By
register
address
Do not rewrite
―
―
―
Fixed to 04h *
00h
00h
Immediately
Do not rewrite
―
―
―
Fixed to 85h *
80h
80h
Immediately
Do not rewrite
―
―
―
Fixed to 5Ah *
0Ah
0Ah
Immediately
Do not rewrite
―
―
―
[7:0]
to
to
B6h
[7:0]
B7h
[7:0]
B8h
[7:0]
to
to
C4h
[7:0]
C5h
[7:0]
C6h
[7:0]
to
to
D4h
[7:0]
D5h
[7:0]
D6h
[7:0]
to
to
FFh
[7:0]
35
IMX174LQJ-C
Chip ID = 08 (Write: Chip ID = 08h, Read: Chip ID = 88h)
Default value
Address
00h
bit
Register Name
after reset
Description
Reflection
timing
By
By
register
address
Do not rewrite
―
―
―
Fixed to 10h *
80h
80h
Immediately
Do not rewrite
―
―
―
[7:0]
to
to
24h
[7:0]
25h
[7:0]
26h
[7:0]
to
to
2Ah
[7:0]
2Bh
[7:0]
Fixed to E0h *
50h
50h
Immediately
2Ch
[7:0]
Fixed to 0Ah *
0Bh
0Bh
Immediately
2Dh
[7:0]
Do not rewrite
―
―
―
to
[7:0]
30h
[7:0]
Fixed to AFh *
B6h
B6h
Immediately
31h
[7:0]
Fixed to 10h *
80h
80h
Immediately
32h
[7:0]
Do not rewrite
―
―
―
In
to
[7:0]
Description
no
Register Name
Do not rewrite
Te
[7:0]
S
to
FFh
ch
[7:0]
to
O
00h
bit
FR
AM
Address
lo
gi
Chip ID = 09 (Write: Chip ID = 09h, Read: Chip ID = 89h)
es
to
FFh
c.
to
2Fh
36
Default value
after reset
Reflection
By
By
register
address
―
―
timing
―
IMX174LQJ-C
Readout Drive Modes
The table below lists the operating modes available with this sensor.
Serial LVDS ch
rate
rate
[frame/s]
[Gbps]
2 ch
4 ch
8 ch
164.5
4.752
N/A
N/A
82.3
2.376
N/A
〇
Number of
INCK in 1H
INCK:
74.25 MHz
〇
180
360
〇
360
720
720
1440
231
462
〇
N/A
〇
64.1
2.376
N/A
〇
〇
32.1
1.188
〇
〇
〇
164.5
4.752
N/A
N/A
〇
82.3
2.376
N/A
〇
〇
41.2
1.188
〇
〇
〇
128.2
4.752
N/A
N/A
〇
64.1
2.376
N/A
〇
〇
32.1
1.188
〇
〇
〇
120
3.564
N/A
N/A
〇
60
1.782
N/A
〇
〇
30
0.891
〇
〇
〇
120
3.564
N/A
N/A
〇
60
1.782
N/A
〇
〇
30
0.891
〇
〇
〇
*4
4.752
N/A
N/A
〇
*4
2.376
N/A
〇
〇
*4
1.188
〇
〇
*4
4.752
N/A
N/A
*4
2.376
N/A
*4
1.188
〇
V
10
1920
1200
12
1254
2464
10
2304
1600
1200
12
1920
12
2640
1080
1125
2200
10
2304
*3
*3
*4
〇
〇
〇
〇
12
462
924
924
1848
180
360
360
720
720
1440
231
462
1254
2464
10
〇
〇
V
2304
ch
Te
H
c.
〇
N/A
H
In
〇
4.752
conversion
es
1.188
S
*2
INCK:
41.2
O
of pixels
37.125 MHz
128.2
FR
AM
ROI
Total number
recording pixels
A/D
UXGA
HD1080p
Number of
*1
gi
WUXGA
Data
lo
mode
Frame
no
Drive
2464
462
924
924
1848
275
550
550
1100
1100
2200
275
550
550
1100
1100
2200
180
360
360
720
720
1440
231
462
462
924
924
1848
*1 The data rate of each output channel is value that is obtained by total data rate divided by the number of
channels.
Example) In WUXGA 164.5 [frame/s] mode: 4.752 [Gbps] / 8 = 594 [Mbps]
*2
For the setting value to register HMAX / VMAX, see the section of each drive mode settings
*3
Designated cropping area (ROI)
*4
See the section of “ROI mode”
37
IMX174LQJ-C
Sync code
The sync code is added immediately before and after “dummy signal + OB signal + effective pixel data” and
then output. The sync code is output in order of 1st, 2nd, 3rd and 4th. The fixed value is output for 1st to 3rd.
(BLK: Blanking period)
…
H.BLK
4th
H.BLK
3rd
1st
2nd
DATA
・・・・・・・
DATA
DATA
4th
EAV
DATA
3rd
1st
2nd
…
H.BLK
H.BLK
H.BLK
SAV
XVS
V.BLK
H.BLK
SAV
(Invalid line)
H.BLK
EAV
(Invalid line)
…
H.BLK
H.BLK
H.BLK
V.BLK
H.BLK
H.BLK
Frame information line
H.BLK
H.BLK
H.OB/V.OB
H.BLK
H.BLK
H.OB/V.OB
H.BLK
H.OB / effective pixel
SAV
(Valid line)
H.OB / effective pixel
H.BLK
H.BLK
H.BLK
H.OB / effective pixel
H.BLK
H.OB / effective pixel
H.BLK
H.OB / effective pixel
H.BLK
V.BLK
gi
SAV
(Invalid line)
EAV
(Invalid line)
Frame information line
ch
H.OB/V.OB
H.BLK
EAV
(Valid line)
H.BLK
H.BLK
Te
SAV
(Valid line)
H.BLK
H.BLK
V.BLK
no
H.BLK
H.BLK
H.BLK
lo
H.BLK
H.BLK
H.BLK
…
V.BLK
H.BLK
…
…
…
H.BLK
es
H.BLK
In
…
…
…
EAV
(Valid line)
c.
H.BLK
…
…
…
H.BLK
S
Sync Code Output Timing
FR
AM
O
List of Sync Code
1st code
Sync code
SAV (Valid line)
EAV (Valid line)
SAV (Invalid line)
EAV (Invalid line)
2nd code
3rd code
4th code
10 bit
12 bit
10 bit
12 bit
10 bit
12 bit
10 bit
3FFh
FFFh
000h
000h
000h
000h
200h
12 bit
800h
3FFh
FFFh
000h
000h
000h
000h
274h
9D0h
3FFh
FFFh
000h
000h
000h
000h
2ACh
AB0h
3FFh
FFFh
000h
000h
000h
000h
2D8h
B60h
Sync Code Output Timing
The sensor output signal passes through the internal circuits and is output with a latency time (system delay)
relative to the horizontal sync signal. This system delay value is undefined for each line, so refer to the sync
codes output from the sensor and perform synchronization.
XHS
DATA
38
SAV
System Delay
EAV
DATA
SAV
DLO
EAV
System Delay
DATA
IMX174LQJ-C
Image Data Output Format
WUXGA mode (All-pixel scan)
Register List of WUXGA mode
Setting value
Address
bit
Register name
Initial
Value
AD = 10 bit
164.5
[frame/s]
82.3
[frame/s]
AD = 12 bit
41.2
[frame/s]
128.2
[frame/s]
64.1
[frame/s]
32.1
[frame/s]
Remarks
Chip ID = 02h
0h
05h
[7:4]
STBLVDS
0h
14h
N/A
1h
[0]
ADBIT
1
15h
17h
[3:0]
[7:0]
MODE
0h
0h
18h
[3:0]
VMAX
4E6h
4E6h
1Ah
[7:0]
1Bh
[7:0]
[0]
HMAX
1CEh
ODBIT
1
N/A
N/A
2h
N/A
168h
8 ch LVDS
4 ch LVDS
1h
N/A
0
2h
1
2D0h
5A0h
0: 10 bit 1: 12 bit
1254 line
1CEh
39Ch
0
738h
1
0: 10 bit 1: 12 bit
1h
OPORTSEL
1h
N/A
3h
N/A
[7:0]
CKSEL
00h
21h
[1:0]
FREQ
0h
[7:0]
INCKSEL0
00h
1h
2h
0h
1h
2h
8 ch LVDS
0h
1h
N/A
0h
1h
4 ch LVDS
N/A
N/A
0h
N/A
N/A
0h
2 ch LVDS
Initial setting
30h
INCKSEL1
00h
[7:0]
INCKSEL2
20h
10h
INCK = 37.125 MHz: 02h
INCK = 74.25 MHz: 00h
10h
INCK = 37.125 MHz: 02h
INCK = 74.25 MHz: 00h
[7:0]
INCKSEL3
00h
A0h
A5h
[7:0]
[7:0]
GTWAIT
GSDLY
A4h
08h
A9h
[7:0]
―
0Ch
―
A0h
―
3Eh
―
00h
40h
20h
Initial setting
―
―
00h
20h
01h
02h
Initial setting
Initial setting
ch
95h
O
[7:0]
2 ch LVDS
0h
20h
94h
4 ch LVDS
4h
N/A
01h
93h
N/A
gi
92h
―
N/A
lo
[7:0]
4h
no
28h
N/A
3h
In
1Fh
8 ch LVDS
N/A
c.
[6:4]
2 ch LVDS
WUXGA mode
es
1Ch
N/A
Te
A4h
08h
S
0Ch
N/A
N/A
18h
N/A
30h
8 ch LVDS
N/A
30h
N/A
18h
N/A
10h
4 ch LVDS
30h
2 ch LVDS
Initial setting
[7:0]
BEh
[7:0]
BFh
[7:0]
C0h
C2h
[7:0]
[7:0]
C6h
[7:0]
―
03h
01h
03h
Initial setting
D2h
[7:0]
―
0Fh
05h
0Fh
Initial setting
D7h
[7:0]
Chip ID = 04h
―
01h
FR
AM
BCh
45h
Initial setting
A0h
00h
Initial setting
12h
[7:0]
―
00h
40h
20h
Initial setting
12h
[7:0]
―
00h
40h
20h
Initial setting
1Ah
[7:0]
Chip ID = 05h
―
0Fh
0Fh
08h
Initial setting
67h
[7:0]
―
34h
68h
[7:0]
―
46h
6Ch
73h
[7:0]
[7:0]
―
―
00h
2Ch
75h
[7:0]
―
13h
8Fh
[7:0]
―
00h
04h
22h
Initial setting
11h
05h
0Ch
0Bh
39
Initial setting
Initial setting
0Fh
7Ch
Initial setting
Initial setting
Initial setting
IMX174LQJ-C
Chip ID = 07h
B7h
[7:0]
―
00h
04h
Initial setting
C5h
D5h
[7:0]
[7:0]
―
―
80h
0Ah
85h
5Ah
Initial setting
Initial setting
Chip ID = 08h
[7:0]
―
80h
10h
Initial setting
[7:0]
[7:0]
―
―
50h
0Bh
E0h
0Ah
Initial setting
Initial setting
30h
[7:0]
―
B6h
AFh
Initial setting
31h
[7:0]
―
80h
10h
Initial setting
Vertical effective OB
8
Effective margin for color processing
RG
GB
RG
GB
RG
GB
c.
Number of recommended
recording pixels:
1920 (H) × 1200 (V) = 2.30 M pixel
Number of active pixels: 1936 (H) × 1216 (V) = 2.35 M pixel
Number of effective pixels: 1936 (H) × 1216 (V) = 2.35 M pixel
Total number of pixels:
1936 (H) × 1226 (V) = 2.37 M pixel
Total
1254 [H]
1200
Recording pixel area
1920
8
4
lo
Total 10 bit: 2304 [pixels] / 12 bit: 2464 [pixels]
Effective margin for color processing
1
Vertical blanking
ch
8
Te
RG
GB
no
RG
GB
Horizontal scan direction (Normal)
O
S
XHS
FR
AM
Pixel Array Image Drawing in WUXGA Mode
40
RG
GB
RG
GB
Horizontal blanking
Ignored OB
4
Sync code
Frame information line
6
Effective margin
for color processing
Vertical blanking period
1
In
8
Communication period
es
Effective margin
for color processing
4
4
22
gi
Sync code
RG
GB
Horizontal blanking
Vertical scan direction (Normal)
XVS
25h
2Bh
2Ch
IMX174LQJ-C
(1 Frame) : 1254 [lines]
XVS
XHS
Line No. during
normal operation
Line No. during
inverted operation
Normal
SAV1 SAV2 SAV3 SAV4
CH1 / DLOP/M D
CH2 / DLOP/M E
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
7
10
1
6
7
10 1226
1
1
2
3
4
6
5
6
7
8
11
4
9
10
11
12
18
19
1218 1219
1219 1218
8
19
12
11
10
9
8
7
6
5
4
3
2
1
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
5
6
7
8
9
10
11
12
13
14
15
16
1936 1932 1928 1924
1935 1931 1927 1923
1934 1930 1926 1922
1933 1929 1925 1921
1
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
1921 1925 1929 1933
1922 1926 1930 1934
1923 1927 1931 1935
1924 1928 1932 1936
HB
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
484 DATA
4 DATA
HB
CH1 / DLOP/M D
CH2 / DLOP/M E
CH3 / DLOP/M C
CH4 / DLOP/M F
CH5 / DLOP/M B
CH6 / DLOP/M G
CH7 / DLOP/M A
CH8 / DLOP/M H
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
9
10
11
12
13
14
15
16
Te
SAV1 SAV2 SAV3 SAV4
1
2
3
4
5
6
7
8
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
S
SAV1 SAV2 SAV3 SAV4
O
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
HB
no
SAV1 SAV2 SAV3 SAV4
17
18
19
20
21
22
23
24
ch
CH1 / DLOP/M D
CH2 / DLOP/M E
CH3 / DLOP/M C
CH4 / DLOP/M F
CH5 / DLOP/M B
CH6 / DLOP/M G
CH7 / DLOP/M A
CH8 / DLOP/M H
FR
AM
Inverted
8 ch output
Normal
lo
4 DATA
8
c.
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
1
2
3
4
11
4 DATA
In
CH1 / DLOP/M D
CH2 / DLOP/M E
CH3 / DLOP/M C
CH4 / DLOP/M F
SAV1 SAV2 SAV3 SAV4
es
Normal
SAV1 SAV2 SAV3 SAV4
Inverted
968 DATA
1226
18
1200
1925 1927 1929 1931 1933 1935
1926 1928 1930 1932 1934 1936
1936 1934 1932 1930 1928 1926
1935 1933 1931 1929 1927 1925
4 DATA
CH1 / DLOP/M D
CH2 / DLOP/M E
CH3 / DLOP/M C
CH4 / DLOP/M F
HB
6
gi
2 ch output
CH1 / DLOP/M D
CH2 / DLOP/M E
HB
4 ch output
22
Inverted
4
1
1936 1928 1920
1935 1927 1919
1934 1926 1918
1933 1925 1917
1932 1924 1916
1931 1923 1915
1930 1922 1914
1929 1921 1913
4 DATA
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
4 DATA
：Communication period
：Frame information line
：Ineffective OB
：Effective OB
：Blanking
SAV
1st [9]
SAV
1st [8]
SAV
1st [7]
SAV
1st [6]
SAV
1st [5]
SAV
1st [4]
SAV
1st [3]
SAV
1st [2]
SAV
1st [1]
SAV
1st [0]
CHx
(x = 1-8)
24
23
22
21
20
19
18
17
242 DATA
DCK (DDR)
10 bit
Output
1913 1921 1929
1914 1922 1930
1915 1923 1931
1916 1924 1932
1917 1925 1933
1918 1926 1934
1919 1927 1935
1920 1928 1936
12 bit
Output
CHx
(x = 1-8)
SAV
1st [11]
SAV
1st [10]
SAV
1st [9]
SAV
1st [8]
SAV
1st [7]
SAV
1st [6]
SAV
1st [5]
SAV
1st [4]
SAV
1st [3]
SAV
1st [2]
SAV
1st [1]
SAV
1st [0]
DCK (DDR)
Drive Timing Chart for Serial Output in WUXGA Mode
41
HB
：Sync code
：Color processing margin
：Recording pixel area
：Dummy
*HB: Horizontal blanking
IMX174LQJ-C
UXGA mode
Register List of UXGA mode
Setting value
Address
bit
Register name
Initial
Value
AD = 10 bit
164.5
[frame/s]
82.3
[frame/s]
AD = 12 bit
41.2
[frame/s]
128.2
[frame/s]
64.1
[frame/s]
32.1
[frame/s]
Remarks
Chip ID = 02h
0h
05h
[7:4]
STBLVDS
0h
14h
N/A
1h
[0]
ADBIT
1
15h
17h
[3:0]
[7:0]
MODE
0h
2h
18h
[3:0]
VMAX
4E6h
4E6h
1Ah
[7:0]
1Bh
[7:0]
[0]
HMAX
1CEh
ODBIT
1
N/A
N/A
2h
N/A
N/A
0
168h
8 ch LVDS
4 ch LVDS
1h
2h
1
2D0h
5A0h
0: 10 bit 1: 12 bit
UXGA mode
1254 line
1CEh
39Ch
0
738h
1
0: 10 bit 1: 12 bit
1h
1h
N/A
3h
N/A
1Fh
[7:0]
CKSEL
00h
21h
[1:0]
FREQ
0h
INCKSEL1
00h
94h
[7:0]
INCKSEL2
20h
95h
[7:0]
INCKSEL3
00h
A0h
A5h
[7:0]
[7:0]
GTWAIT
GSDLY
A4h
08h
A9h
[7:0]
―
0Ch
2 ch LVDS
1h
2h
0h
1h
2h
8 ch LVDS
0h
1h
N/A
0h
1h
4 ch LVDS
N/A
N/A
0h
N/A
N/A
0h
2 ch LVDS
Initial setting
30h
20h
[7:0]
4h
0h
01h
93h
N/A
10h
INCK = 37.125 MHz: 02h
INCK = 74.25 MHz: 00h
gi
INCKSEL0
4 ch LVDS
N/A
N/A
lo
[7:0]
3h
00h
10h
INCK = 37.125 MHz: 02h
INCK = 74.25 MHz: 00h
no
92h
―
4h
A4h
08h
ch
[7:0]
N/A
Te
28h
8 ch LVDS
N/A
c.
OPORTSEL
In
[6:4]
2 ch LVDS
es
1Ch
N/A
N/A
S
N/A
0Ch
18h
N/A
30h
8 ch LVDS
N/A
30h
N/A
18h
N/A
10h
4 ch LVDS
30h
2 ch LVDS
Initial setting
[7:0]
―
A0h
BEh
[7:0]
―
3Eh
BFh
[7:0]
―
00h
40h
20h
Initial setting
C0h
C2h
[7:0]
[7:0]
―
―
00h
20h
01h
02h
Initial setting
Initial setting
C6h
[7:0]
―
03h
01h
03h
Initial setting
D2h
[7:0]
―
0Fh
05h
0Fh
Initial setting
―
01h
D7h
[7:0]
Chip ID = 04h
FR
AM
O
BCh
45h
Initial setting
A0h
00h
Initial setting
12h
[7:0]
―
00h
40h
20h
Initial setting
13h
[7:0]
―
00h
40h
20h
Initial setting
1Ah
[7:0]
Chip ID = 05h
―
0Fh
0Fh
08h
Initial setting
67h
[7:0]
―
34h
68h
[7:0]
―
46h
6Ch
73h
[7:0]
[7:0]
―
―
00h
2Ch
75h
[7:0]
―
13h
8Fh
[7:0]
―
00h
04h
22h
Initial setting
11h
05h
0Ch
0Bh
42
Initial setting
Initial setting
0Fh
7Ch
Initial setting
Initial setting
Initial setting
IMX174LQJ-C
Chip ID = 07h
B7h
[7:0]
―
00h
04h
Initial setting
C5h
D5h
[7:0]
[7:0]
―
―
80h
0Ah
85h
5Ah
Initial setting
Initial setting
Chip ID = 08h
[7:0]
―
80h
10h
Initial setting
[7:0]
[7:0]
―
―
50h
0Bh
E0h
0Ah
Initial setting
Initial setting
30h
[7:0]
―
B6h
AFh
Initial setting
31h
[7:0]
―
80h
10h
Initial setting
Vertical effective OB
8
Effective margin for color processing
RG
GB
RG
GB
RG
GB
c.
Number of recommended
recording pixels:
1600 (H) × 1200 (V) = 1.92 M pixel
Number of active pixels: 1616 (H) × 1216 (V) = 1.97 M pixel
Number of effective pixels: 1616 (H) × 1216 (V) = 1.97 M pixel
Total number of pixels:
1616 (H) × 1226 (V) = 1.98 M pixel
Total
1254 [H]
1200
Recording pixel area
1600
8
4
lo
Total 10 bit: 2304 [pixels] / 12 bit: 2464 [pixels]
Effective margin for color processing
1
Vertical blanking
ch
8
Te
RG
GB
no
RG
GB
Horizontal scan direction (Normal)
O
S
XHS
FR
AM
Pixel Array Image Drawing in UXGA Mode
43
RG
GB
RG
GB
Horizontal blanking
Ignored OB
4
Sync code
Frame information line
6
Effective margin
for color processing
Vertical blanking period
1
In
8
Communication period
es
Effective margin
for color processing
4
4
22
gi
Sync code
RG
GB
Horizontal blanking
Vertical scan direction (Normal)
XVS
25h
2Bh
2Ch
IMX174LQJ-C
(1 Frame) : 1254 [lines]
XVS
XHS
Line No. during
normal operation
Line No. during
inverted operation
Normal
SAV1 SAV2 SAV3 SAV4
CH1 / DLOP/M D
CH2 / DLOP/M E
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
7
10
1
6
7
10 1226
1
1
2
3
4
6
5
6
7
8
11
4
9
10
11
12
18
19
1218 1219
1219 1218
8
19
12
11
10
9
8
7
6
5
4
3
2
1
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
5
6
7
8
9
10
11
12
13
14
15
16
1616 1612 1608 1604
1615 1611 1607 1603
1614 1610 1606 1602
1613 1609 1605 1601
1
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
1601 1605 1609 1613
1602 1606 1610 1614
1603 1607 1611 1615
1604 1608 1612 1616
HB
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
404 DATA
4 DATA
HB
CH1 / DLOP/M D
CH2 / DLOP/M E
CH3 / DLOP/M C
CH4 / DLOP/M F
CH5 / DLOP/M B
CH6 / DLOP/M G
CH7 / DLOP/M A
CH8 / DLOP/M H
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
9
10
11
12
13
14
15
16
Te
SAV1 SAV2 SAV3 SAV4
1
2
3
4
5
6
7
8
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
S
SAV1 SAV2 SAV3 SAV4
O
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
HB
no
SAV1 SAV2 SAV3 SAV4
17
18
19
20
21
22
23
24
ch
CH1 / DLOP/M D
CH2 / DLOP/M E
CH3 / DLOP/M C
CH4 / DLOP/M F
CH5 / DLOP/M B
CH6 / DLOP/M G
CH7 / DLOP/M A
CH8 / DLOP/M H
FR
AM
Inverted
8 ch output
Normal
lo
4 DATA
8
c.
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
1
2
3
4
11
4 DATA
In
CH1 / DLOP/M D
CH2 / DLOP/M E
CH3 / DLOP/M C
CH4 / DLOP/M F
SAV1 SAV2 SAV3 SAV4
es
Normal
SAV1 SAV2 SAV3 SAV4
Inverted
808 DATA
1226
18
1200
1605 1607 1609 1611 1613 1615
1606 1608 1610 1612 1614 1616
1616 1614 1612 1610 1608 1606
1615 1613 1611 1609 1607 1605
4 DATA
CH1 / DLOP/M D
CH2 / DLOP/M E
CH3 / DLOP/M C
CH4 / DLOP/M F
HB
6
gi
2 ch output
CH1 / DLOP/M D
CH2 / DLOP/M E
HB
4 ch output
22
Inverted
4
1
1616 1608 1600
1615 1607 1599
1614 1606 1598
1613 1605 1597
1612 1604 1596
1611 1603 1595
1610 1602 1594
1609 1601 1593
4 DATA
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
4 DATA
：Communication period
：Frame information line
：Ineffective OB
：Effective OB
：Blanking
SAV
1st [9]
SAV
1st [8]
SAV
1st [7]
SAV
1st [6]
SAV
1st [5]
SAV
1st [4]
SAV
1st [3]
SAV
1st [2]
SAV
1st [1]
SAV
1st [0]
CHx
(x = 1-8)
24
23
22
21
20
19
18
17
202 DATA
DCK (DDR)
10 bit
Output
1593 1601 1609
1594 1602 1610
1595 1603 1611
1596 1604 1612
1597 1605 1613
1598 1606 1614
1599 1607 1615
1600 1608 1616
12 bit
Output
CHx
(x = 1-8)
SAV
1st [11]
SAV
1st [10]
SAV
1st [9]
SAV
1st [8]
SAV
1st [7]
SAV
1st [6]
SAV
1st [5]
SAV
1st [4]
SAV
1st [3]
SAV
1st [2]
SAV
1st [1]
SAV
1st [0]
DCK (DDR)
Drive Timing Chart for Serial Output in UXGA Mode
44
HB
：Sync code
：Color processing margin
：Recording pixel area
：Dummy
*HB: Horizontal blanking
IMX174LQJ-C
1080p-Full HD mode
Register List of 1080p-Full HD mode
Setting value
Address
bit
Register name
Initial
Value
AD = 10 bit
120
[frame/s]
AD = 12 bit
60
[frame/s]
30
[frame/s]
120
[frame/s]
60
[frame/s]
30
[frame/s]
Remarks
Chip ID = 02h
0h
05h
[7:4]
STBLVDS
0h
14h
N/A
[0]
ADBIT
1
15h
17h
[3:0]
[7:0]
MODE
0h
4h
18h
[3:0]
VMAX
4E6h
465h
1Ah
[7:0]
1Bh
[7:0]
[0]
HMAX
1CEh
ODBIT
1
N/A
N/A
N/A
2h
N/A
N/A
0
226h
8 ch LVDS
4 ch LVDS
1h
2h
1
44Ch
898h
0: 10 bit 1: 12 bit
1080p-Full HD mode
1125 line
226h
44Ch
0
898h
1
0: 10 bit 1: 12 bit
1h
1h
N/A
N/A
[7:0]
CKSEL
00h
21h
[1:0]
FREQ
0h
INCKSEL0
20h
93h
[7:0]
INCKSEL1
00h
94h
[7:0]
INCKSEL2
95h
[7:0]
INCKSEL3
00h
A0h
A5h
[7:0]
[7:0]
GTWAIT
GSDLY
A4h
08h
A9h
[7:0]
―
0Ch
N/A
4h
2 ch LVDS
0h
1h
2h
0h
1h
2h
8 ch LVDS
N/A
0h
1h
N/A
0h
1h
4 ch LVDS
N/A
N/A
0h
N/A
N/A
0h
2 ch LVDS
Initial setting
01h
20h
4 ch LVDS
N/A
30h
INCK = 37.125 MHz: 18h
INCK = 74.25 MHz: 0Ch
00h
INCK = 37.125 MHz: 20h
INCK = 74.25 MHz: 10h
lo
[7:0]
3h
01h
no
92h
4h
ch
[7:0]
N/A
Te
―
28h
8 ch LVDS
N/A
c.
1Fh
3h
In
OPORTSEL
es
[6:4]
2 ch LVDS
gi
1Ch
1h
N/A
S
N/A
00h
64h
06h
0Ch
18h
N/A
30h
8 ch LVDS
N/A
30h
N/A
18h
N/A
10h
4 ch LVDS
30h
2 ch LVDS
Initial setting
[7:0]
―
A0h
BEh
[7:0]
―
3Eh
BFh
[7:0]
―
00h
40h
20h
Initial setting
C0h
C2h
[7:0]
[7:0]
―
―
00h
20h
01h
02h
Initial setting
Initial setting
C6h
[7:0]
―
03h
01h
03h
Initial setting
D2h
[7:0]
―
0Fh
05h
0Fh
Initial setting
D7h
[7:0]
Chip ID = 04h
―
01h
FR
AM
O
BCh
45h
Initial setting
A0h
00h
Initial setting
12h
[7:0]
―
00h
40h
20h
Initial setting
13h
[7:0]
―
00h
40h
20h
Initial setting
1Ah
[7:0]
Chip ID = 05h
―
0Fh
0Fh
08h
Initial setting
67h
[7:0]
―
34h
68h
[7:0]
―
46h
6Ch
73h
[7:0]
[7:0]
―
―
00h
2Ch
75h
[7:0]
―
13h
8Fh
[7:0]
―
00h
04h
22h
Initial setting
11h
05h
0Ch
0Bh
Initial setting
Initial setting
0Fh
7Ch
45
Initial setting
Initial setting
Initial setting
IMX174LQJ-C
Chip ID = 07h
B7h
[7:0]
―
00h
04h
Initial setting
C5h
D5h
[7:0]
[7:0]
―
―
80h
0Ah
85h
5Ah
Initial setting
Initial setting
Chip ID = 08h
[7:0]
―
80h
10h
Initial setting
[7:0]
[7:0]
―
―
50h
0Bh
E0h
0Ah
Initial setting
Initial setting
30h
[7:0]
―
B6h
AFh
Initial setting
31h
[7:0]
―
80h
10h
Initial setting
Vertical effective OB
8
Effective margin for color processing
RG
GB
RG
GB
RG
GB
c.
Number of recommended
recording pixels:
1920 (H) × 1080 (V) = 2.07 M pixel
Number of active pixels: 1936 (H) × 1096 (V) = 2.12 M pixel
Number of effective pixels: 1936 (H) × 1096 (V) = 2.12 M pixel
Total number of pixels:
1936 (H) × 1106 (V) = 2.14 M pixel
Total
1125 [H]
1080
Recording pixel area
1920
8
4
lo
Total 10 bit: 2640 [pixels] / 12 bit: 2200 [pixels]
RG
GB
Effective margin for color processing
ch
8
no
RG
GB
Horizontal scan direction (Normal)
Te
XHS
FR
AM
O
S
Pixel Array Image Drawing in 1080p-Full HD Mode
46
RG
GB
RG
GB
Horizontal blanking
Ignored OB
4
Sync code
Frame information line
6
Effective margin
for color processing
Vertical blanking period
1
In
8
Communication period
es
Effective margin
for color processing
4
4
14
gi
Sync code
RG
GB
Horizontal blanking
Vertical scan direction (Normal)
XVS
25h
2Bh
2Ch
IMX174LQJ-C
(1 Frame) : 1125 [lines]
XVS
XHS
Line No. during
normal operation
Line No. during
inverted operation
Normal
SAV1 SAV2 SAV3 SAV4
CH1 / DLOP/M D
CH2 / DLOP/M E
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
7
10
1
6
7
10 1106
1
1
2
3
4
6
5
6
7
8
11
4
9
10
11
12
18
19
1098 1099
1099 1098
8
19
12
11
10
9
8
7
6
5
4
3
2
1
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
5
6
7
8
9
10
11
12
13
14
15
16
1936 1932 1928 1924
1935 1931 1927 1923
1934 1930 1926 1922
1933 1929 1925 1921
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
1921 1925 1929 1933
1922 1926 1930 1934
1923 1927 1931 1935
1924 1928 1932 1936
HB
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
484 DATA
4 DATA
HB
CH1 / DLOP/M D
CH2 / DLOP/M E
CH3 / DLOP/M C
CH4 / DLOP/M F
CH5 / DLOP/M B
CH6 / DLOP/M G
CH7 / DLOP/M A
CH8 / DLOP/M H
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
9
10
11
12
13
14
15
16
Te
SAV1 SAV2 SAV3 SAV4
1
2
3
4
5
6
7
8
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
S
SAV1 SAV2 SAV3 SAV4
O
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
HB
no
SAV1 SAV2 SAV3 SAV4
17
18
19
20
21
22
23
24
ch
CH1 / DLOP/M D
CH2 / DLOP/M E
CH3 / DLOP/M C
CH4 / DLOP/M F
CH5 / DLOP/M B
CH6 / DLOP/M G
CH7 / DLOP/M A
CH8 / DLOP/M H
FR
AM
Inverted
8 ch output
Normal
lo
4 DATA
8
c.
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
1
2
3
4
11
4 DATA
In
CH1 / DLOP/M D
CH2 / DLOP/M E
CH3 / DLOP/M C
CH4 / DLOP/M F
SAV1 SAV2 SAV3 SAV4
es
Normal
SAV1 SAV2 SAV3 SAV4
Inverted
968 DATA
1106
18
1080
1925 1927 1929 1931 1933 1935
1926 1928 1930 1932 1934 1936
1936 1934 1932 1930 1928 1926
1935 1933 1931 1929 1927 1925
4 DATA
CH1 / DLOP/M D
CH2 / DLOP/M E
CH3 / DLOP/M C
CH4 / DLOP/M F
HB
6
gi
2 ch output
CH1 / DLOP/M D
CH2 / DLOP/M E
HB
4 ch output
14
Inverted
4
1
1936 1928 1920
1935 1927 1919
1934 1926 1918
1933 1925 1917
1932 1924 1916
1931 1923 1915
1930 1922 1914
1929 1921 1913
4 DATA
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
4 DATA
：Communication period
：Frame information line
：Ineffective OB
：Effective OB
：Blanking
SAV
1st [9]
SAV
1st [8]
SAV
1st [7]
SAV
1st [6]
SAV
1st [5]
SAV
1st [4]
SAV
1st [3]
SAV
1st [2]
SAV
1st [1]
SAV
1st [0]
CHx
(x = 1-8)
24
23
22
21
20
19
18
17
242 DATA
DCK (DDR)
10 bit
Output
1913 1921 1929
1914 1922 1930
1915 1923 1931
1916 1924 1932
1917 1925 1933
1918 1926 1934
1919 1927 1935
1920 1928 1936
HB
：Sync code
：Color processing margin
：Recording pixel area
：Dummy
*HB: Horizontal blanking
12 bit
Output
CHx
(x = 1-8)
SAV
1st [11]
SAV
1st [10]
SAV
1st [9]
SAV
1st [8]
SAV
1st [7]
SAV
1st [6]
SAV
1st [5]
SAV
1st [4]
SAV
1st [3]
SAV
1st [2]
SAV
1st [1]
SAV
1st [0]
DCK (DDR)
Drive Timing Chart for Serial Output in 1080p-Full HD Mode
47
IMX174LQJ-C
ROI mode
This Sensor has ROI function that signals are cut out and read out in multi arbitrary positions.
Cropping position can set maximum 16 areas that specified by horizontal 4 points and vertical 4 points, regarding
effective pixel start position as origin (0, 0) in all pixel scan mode. Cropping is available from WUXGA mode and
horizontal period are fixed to the value for this mode.
These cropped areas by horizontal cropping setting (ROI (1, y) to ROI (4, y)) are output with left justified and that
extends the horizontal blanking period. In vertical cropping area (ROI (x, 1) to ROI (x, 4)), the number of image
data is also output from cropping start line and the frame rate can be adjusted by changing the number of input
XVS lines in slave mode or changing register VMAX in master mode.
One invalid frame is generated when the ROI area changing size or cropping address.
ROI image is shown in the figure below.
ROIPH1
ROIPH2
ROIPH3
ROIPH4
Ignored OB
Vertical effective OB
ROIPV1
RG
GB
RG
GB
ROIWH1
ROIWH2
ROIWH3
ROIWH4
ROIWV1
ROI (1, 1)
ROI (2, 1)
ROI (3, 1)
ROI (4, 1)
c.
ROIPV2
ROI (1, 2)
In
ROIWV2
ROI (2, 2)
ROI (3, 2)
ROIPV3
es
Total 1254
ROIWV3
ROI (2, 3)
gi
ROI (1, 3)
lo
ROIPV4
ROI (1, 4)
ROI (2, 4)
no
ROIWV4
ROI (3, 3)
ROI (4, 3)
ROI (4, 4)
ROI (4, 4)
Total 10 bit: 2304 / 12 bit: 2464
RG
GB
ch
RG
GB
ROI (4, 2)
Te
Vertical blanking
O
S
Image Drawing of Designated Areas in ROI Mode
FR
AM
Ignored OB
Vertical effective OB
ROIPV1
ROIPV2
R G ROIWH1
G B ROIWV1
ROIWH2
ROIWH3
ROIWH4 R G
GB
ROI (1, 1) ROI (2, 1)
ROI (3, 1)
ROI (4, 1)
ROI (3, 2)
ROI (4, 2)
ROI (3, 3)
ROI (4, 3)
ROI (2, 4)
ROI (4, 4)
Vertical blanking
ROI (4, 4) G B
ROIWV2
ROIPV3
ROI (1, 2) ROI (2, 2)
Vertical period
ROIWV3
ROIPV4
ROI (1, 3) ROI (2, 3)
R G ROIWV4
GB
ROI (1, 4)
RG
Total 10 bit: 2304 / 12 bit: 2464
Details of Image Drawing
48
IMX174LQJ-C
Register List of ROI mode
Setting value
bit
Register name
Initial
Value
[7:4]
STBLVDS
0h
Address
*1
[frame/s]
AD = 10 bit
*2
[frame/s]
*3
[frame/s]
*4
[frame/s]
AD = 12 bit
*5
[frame/s]
*6
[frame/s]
Remarks
Chip ID = 02h
0h
05h
N/A
1h
N/A
N/A
0
8 ch LVDS
N/A
2h
1h
N/A
N/A
1
4 ch LVDS
2h
14h
[0]
ADBIT
1
15h
[3:0]
MODE
0h
17h
[7:0]
18h
1Ah
[3:0]
[7:0]
VMAX
4E6h
*1
*2
*3
*4
*5
*6
1Bh
[7:0]
HMAX
1CEh
168h
2D0h
5A0h
1CEh
39Ch
738h
ODBIT
1
[0]
WUXGA mode
0
1
0: 10 bit 1: 12 bit
1h
[6:4]
OPORTSEL
1h
N/A
3h
1Fh
[7:0]
CKSEL
00h
21h
[1:0]
FREQ
0h
28h
[7:0]
―
01h
30h
92h
[7:0]
INCKSEL0
20h
20h
93h
[7:0]
INCKSEL1
00h
INCK = 37.125 MHz: 00h
INCK = 74.25 MHz: 04h
95h
[7:0]
INCKSEL2
00h
INCK = 37.125 MHz: 00h
INCK = 74.25 MHz: 04h
A0h
[7:0]
GTWAIT
A4h
A5h
[7:0]
GSDLY
08h
N/A
1h
0h
2h
1h
N/A
N/A
0h
[7:0]
―
A0h
BEh
BFh
[7:0]
[7:0]
―
―
3Eh
00h
C0h
[7:0]
―
00h
C2h
[7:0]
―
C6h
D2h
[7:0]
[7:0]
―
―
D7h
[7:0]
N/A
S
N/A
4h
2 ch LVDS
0h
N/A
1h
0h
2h
1h
8 ch LVDS
4 ch LVDS
N/A
N/A
0h
2 ch LVDS
Initial setting
03h
0Fh
es
A4h
08h
0Ch
18h
N/A
30h
N/A
30h
40h
01h
N/A
30h
2 ch LVDS
10h
Initial setting
20h
Initial setting
Initial setting
02h
Initial setting
A0h
01h
05h
8 ch LVDS
4 ch LVDS
18h
45h
20h
FR
AM
[7:0]
Te
N/A
1Ah
N/A
gi
BCh
O
lo
0Ch
no
―
[7:0]
[7:0]
N/A
In
0h
N/A
ch
[7:0]
12h
13h
4h
8 ch LVDS
4 ch LVDS
3h
00h
A9h
Chip ID = 04h
N/A
N/A
c.
1Ch
0h
2 ch LVDS
0: 10 bit 1: 12 bit
Initial setting
03h
0Fh
Initial setting
Initial setting
―
01h
―
―
00h
00h
40h
40h
20h
20h
Initial setting
Initial setting
―
0Fh
0Fh
08h
Initial setting
34h
46h
22h
11h
Initial setting
Initial setting
00h
Initial setting
Chip ID = 05h
67h
68h
[7:0]
[7:0]
―
―
6Ch
[7:0]
―
00h
05h
73h
[7:0]
―
2Ch
0Ch
75h
8Fh
[7:0]
[7:0]
―
―
13h
00h
04h
0Bh
Initial setting
Initial setting
0Fh
7Ch
Initial setting
Initial setting
Chip ID = 07h
B7h
[7:0]
―
00h
04h
Initial setting
C5h
D5h
[7:0]
[7:0]
―
―
80h
0Ah
85h
5Ah
Initial setting
Initial setting
Chip ID = 08h
25h
[7:0]
―
80h
10h
Initial setting
2Bh
2Ch
[7:0]
[7:0]
―
―
50h
0Bh
E0h
0Ah
Initial setting
Initial setting
30h
[7:0]
―
B6h
AFh
Initial setting
31h
[7:0]
―
80h
10h
Initial setting
49
IMX174LQJ-C
Setting value
bit
Address
Register name
Initial
Value
*1
[frame/s]
AD = 10 bit
*2
[frame/s]
*3
[frame/s]
*4
[frame/s]
AD = 12 bit
*5
[frame/s]
*6
[frame/s]
Chip ID = 03h
[0]
ROIH1ON
0
The horizontal setting of ROI area (1, y) (y = 1 to 4)
0: Disable
1: Enable
[1]
ROIV1ON
0
The vertical setting of ROI area (x, 1) (x = 1 to 4)
0: Disable
1: Enable
00h
01h
[7:0]
02h
[2:0]
03h
[7:0]
04h
[2:0]
05h
[7:0]
06h
[2:0]
07h
[7:0]
08h
[2:0]
ROIPH1
000h
Designation of horizontal cropping position on area (1, y) (y = 1 to 4)
ROIPV1
000h
Designation of vertical cropping position on area (x, 1) (x = 1 to 4)
ROIWH1
000h
Designation of horizontal cropping size on area (1, y) (y = 1 to 4)
ROIWV1
000h
Designation of vertical cropping size on area (x, 1) (x = 1 to 4)
[0]
ROIH2ON
0
The horizontal setting of ROI area (2, y) (y = 1 to 4)
0: Disable
1: Enable
[1]
ROIV2ON
0
The vertical setting of ROI area (x, 2) (x = 1 to 4)
0: Disable
1: Enable
[7:0]
0Bh
[2:0]
0Ch
[7:0]
0Dh
[2:0]
0Eh
[7:0]
0Fh
[2:0]
10h
[7:0]
11h
[2:0]
In
es
0Ah
c.
09h
000h
Designation of horizontal cropping position on area (2, y) (y = 1 to 4)
ROIPV2
000h
Designation of vertical cropping position on area (x, 2) (x = 1 to 4)
ROIWH2
000h
Designation of horizontal cropping size on area (2, y) (y = 1 to 4)
ROIWV2
000h
Designation of vertical cropping size on area (x, 2) (x = 1 to 4)
[0]
ROIH3ON
0
[1]
ROIV3ON
0
[7:0]
14h
[2:0]
15h
[7:0]
16h
[2:0]
17h
[7:0]
18h
[2:0]
19h
[7:0]
1Ah
[2:0]
lo
no
ch
Te
S
FR
AM
13h
The horizontal setting of ROI area (3, y) (y = 1 to 4)
0: Disable 1: Enable
O
12h
gi
ROIPH2
The vertical setting of ROI area (x, 3) (x = 1 to 4)
0: Disable 1: Enable
ROIPH3
000h
Designation of horizontal cropping position on area (3, y) (y = 1 to 4)
ROIPV3
000h
Designation of vertical cropping position on area (x, 3) (x = 1 to 4)
ROIWH3
000h
Designation of horizontal cropping size on area (3, y) (y = 1 to 4)
ROIWV3
000h
Designation of vertical cropping size on area (x, 3) (x = 1 to 4)
[0]
ROIH4ON
0
The horizontal setting of ROI area (4, y) (y = 1 to 4)
0: Disable 1: Enable
[1]
ROIV4ON
0
The vertical setting of ROI area (x, 4) (x = 1 to 4)
0: Disable 1: Enable
1Bh
1Ch
[7:0]
1Dh
[2:0]
1Eh
[7:0]
1Fh
[2:0]
20h
[7:0]
21h
[2:0]
22h
[7:0]
23h
[2:0]
ROIPH4
000h
Designation of horizontal cropping position on area (4, y) (y = 1 to 4)
ROIPV4
000h
Designation of vertical cropping position on area (x, 4) (x = 1 to 4)
ROIWH4
000h
Designation of horizontal cropping size on area (4, y) (y = 1 to 4)
ROIWV4
000h
Designation of vertical cropping size on area (x, 4) (x = 1 to 4)
50
Remarks
IMX174LQJ-C
Restrictions on ROI mode
The register settings should satisfy following conditions:
* Do not designate area like be overlap.
ROIPH1 + ROIWH1 < ROIPH2
ROIPH2 + ROIWH2 < ROIPH3
ROIPH3 + ROIWH3 < ROIPH4
ROIPH4 + ROIWH4 < 1936d
ROIWH1+ ROIWH2+ ROIWH3+ ROIWH4 > 92
ROIPV1 + ROIWV1 < ROIPV2
ROIPV2 + ROIWV2 < ROIPV3
ROIPV3 + ROIWV3 < ROIPV4
ROIPV4 + ROIWV4 < 1216d
* Set the horizontal and vertical setting in even number
Frame rate on ROI mode
In
c.
Frame rate [frame/s] = 1 / ((“Number of lines per frame” or VMAX ) × ( 1 H period ))
gi
es
* Number of lines per frame or VMAX = ROIWV1 + ROIWV2 + ROIWV3 + ROIWV4 + 38
* 1 period: Change according to the data rate settings and the number of LVDS channels.
Calculate by number of INCK in 1 H and the period of INCK.
ch
no
lo
The example of ROI setting is shown below.
ROIWV1 + ROIWV2 + ROIWV3 + ROIWV4 = 600
ROIWV1 + ROIWV2 + ROIWV3 + ROIWV4 = 2 (minimum value)
Te
Frame rate List of each setting
[µs]
Total number of ROI:
600 [line]
Total number of ROI:
2 [line]
*1
4.849
323.3
5156.3
9.697
161.6
2578.1
19.394
80.8
1289.1
*4
6.222
251.9
4017.9
*5
12.444
126.0
2008.9
*6
24.889
63.0
1004.5
*3
FR
AM
*2
S
1 H period
O
Frame rate
[frame/s]
Register settings
No.
in register list
51
IMX174LQJ-C
(1 Frame) : Y + 37 + VB [lines]
XVS
XHS
Line No. during
normal operation
Line No. during
inverted operation
4
22
1
6
7
10
11
12
14
Y-1
Y
1
6
7
10
Y
Y-1 Y-2 Y-3
12
11
1
6
13
4
Y
VB
Y = ROIWV1 + ROIWV2 + ROIWV3 + ROIWV4
Normal
CH1 / DLOP/M D
CH2 / DLOP/M E
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
5
6
7
8
X
X-1
X-2
X-3
X-4
X-5
X-6
X-7
9
10
11
12
13
14
15
16
X-8 X-12
X-9 X-13
X-10 X-14
X-11 X-15
16
15
14
13
12
11
10
9
10
9
8
7
6
5
4
3
2
1
X-7 X-3
X-6 X-2
X-5 X-1
X-4 X
8
7
6
5
SAV1 SAV2 SAV3 SAV4
Te
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
S
SAV1 SAV2 SAV3 SAV4
O
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
X
X-1
X-2
X-3
X-4
X-5
X-6
X-7
17
18
19
20
21
22
23
24
X-8 X-16
X-9 X-17
X-10 X-18
X-11 X-19
X-12 X-20
X-13 X-21
X-14 X-22
X-15 X-23
4 DATA
X-23 X-15
X-22 X-14
X-21 X-13
X-20 X-12
X-19 X-11
X-18 X-10
X-17 X-9
X-16 X-8
24
23
22
21
20
19
18
17
X / 8 DATA
16
15
14
13
12
11
10
9
SAV
1st [9]
SAV
1st [8]
SAV
1st [7]
SAV
1st [6]
SAV
1st [5]
SAV
1st [4]
SAV
1st [3]
SAV
1st [2]
SAV
1st [1]
SAV
1st [0]
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
4
3
2
1
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
4 DATA
X-7
X-6
X-5
X-4
X-3
X-2
X-1
X
EAV1 EAV2 EAV3 EAV4
8
7
6
5
4
3
2
1
EAV1 EAV2 EAV3 EAV4
HB
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
EAV1 EAV2 EAV3 EAV4
4 DATA
HB
：Sync code
：Ignored area of effective pixel side
：Color processing margin
：Recording pixel area
：Dummy
SAV
1st [11]
SAV
1st [10]
SAV
1st [9]
SAV
1st [8]
SAV
1st [7]
SAV
1st [6]
SAV
1st [5]
SAV
1st [4]
SAV
1st [3]
SAV
1st [2]
SAV
1st [1]
SAV
1st [0]
*HB: Horizontal blanking
Drive Timing Chart for Serial Output in ROI Mode
52
HB
EAV1 EAV2 EAV3 EAV4
：Communication period
：Frame information line
：Ineffective OB
：Effective OB
：Blanking
DCK (DDR)
EAV1 EAV2 EAV3 EAV4
4 DATA
gi
SAV1 SAV2 SAV3 SAV4
9
10
11
12
13
14
15
16
lo
SAV1 SAV2 SAV3 SAV4
SAV1 SAV2 SAV3 SAV4
1
2
3
4
5
6
7
8
DCK (DDR)
12 bit
Output
12
11
X-15 X-11
X-14 X-10
X-13 X-9
X-12 X-8
no
CH1 / DLOP/M D
CH2 / DLOP/M E
CH3 / DLOP/M C
CH4 / DLOP/M F
CH5 / DLOP/M B
CH6 / DLOP/M G
CH7 / DLOP/M A
CH8 / DLOP/M H
SAV1 SAV2 SAV3 SAV4
FR
AM
Normal
8 ch output
1
2
3
4
X / 4 DATA
SAV1 SAV2 SAV3 SAV4
CHx
(x = 1-8)
X-11 X-9 X-7 X-5 X-3 X-1
X-10 X-8 X-6 X-4 X-2 X
X X-2 X-4 X-6 X-8 X-10
X-1 X-3 X-5 X-7 X-9 X-11
4 DATA
CH1 / DLOP/M D
CH2 / DLOP/M E
CH3 / DLOP/M C
CH4 / DLOP/M F
CH5 / DLOP/M B
CH6 / DLOP/M G
CH7 / DLOP/M A
CH8 / DLOP/M H
CHx
(x = 1-8)
11
12
c.
SAV1 SAV2 SAV3 SAV4
10 bit
Output
9
10
In
CH1 / DLOP/M D
CH2 / DLOP/M E
CH3 / DLOP/M C
CH4 / DLOP/M F
SAV1 SAV2 SAV3 SAV4
HB
7
8
es
Normal
4 ch output
SAV1 SAV2 SAV3 SAV4
Inverted
5
6
X / 2 DATA
CH1 / DLOP/M D
CH2 / DLOP/M E
CH3 / DLOP/M C
CH4 / DLOP/M F
HB
3
4
4 DATA
Inverted
HB
1
2
ch
2 ch output
CH1 / DLOP/M D
CH2 / DLOP/M E
Inverted
X = ROIWH1 + ROIWH2 + ROIWH3 + ROIWH4
SAV1 SAV2 SAV3 SAV4
IMX174LQJ-C
Description of Various Function
Standby mode
This sensor stops its operation and goes into standby mode which reduces the power consumption by writing “1” to
the standby control register STANDBY. Standby mode is also established after power-on or other system reset
operation.
Register List of Standby setting
Register details
Register
STANDBY
Chip ID
Address
Bit
02h
00h
[0]
Initial value
Setting value
1h: Standby
0h: Operating
1h
Remarks
Register communication is
executed even in standby
mode.
Initial regulator or
stabilization period
1 ms
lo
Standby
cancel
no
Register
initial settings
gi
es
In
c.
The serial communication registers hold the previous values. However, the address registers transmitted in standby
mode are overwritten. The serial communication block operates even in standby mode, so standby mode can be
canceled by setting the STANDBY register to “0”. Some time is required for sensor internal circuit stabilization after
standby mode is canceled. For details on the sequence of setting and cancel of standby mode, see the sensor
setting flow after power on.
After standby mode is canceled, a normal image is output from the 9 frames after internal regulator stabilization
(1 ms or more).
STANDBY
1→ 0
Te
ch
XCE
O
S
XVS
FR
AM
Initialization period: 8 frames
Sequence from Standby Cancel to Stable Image Output
53
Normal image output
IMX174LQJ-C
Slave Mode and Master Mode
The sensor can be switched between slave mode and master mode.
The switching is made by the XMASTER pin. Establish the XMASTER pin status before canceling the system reset.
(Do not switch this pin status during operation.)
Input a vertical sync signal to XVS and input a horizontal sync signal to XHS when a sensor is in slave mode.
For sync signal interval, input data lines to output for vertical sync signal and 1H period designated in each operating
mode for horizontal sync signal. See the section of "Readout Drive mode" for the number of output data line and 1H
period.
Set the XMSTA register to “0” in order to start the operation after setting to master mode. In addition, set the count
number of sync signal in vertical direction by the VMAX [11:0] register and the clock number in horizontal direction by
the HMAX [15:0] register. See the description of operation mode for details of the section of “Readout Drive Modes”.
Pin Processing
Pin name
Pin processing
Operation mode
Low fixed
Master mode
High fixed
Slave mode
XMASTER pin
Remarks
High: OVDD
Low: GND
12h
[0]
1h
17h
[7:0]
XMSTA
Setting value
4E6h
18h
[3:0]
1Ah
Te
02h
S
HMAX [15:0]
ch
VMAX [11:0]
In
Initial
value
es
Bit
XHSOUTSEL [1:0]
FR
AM
XVSOUTSEL [1:0]
The master operation starts
by setting 0.
See the item of
each drive mode
Line number per frame
designated
(Master mode and Slave
mode common setting.)
See the item of
each drive mode
Clock number per line
designated
(Master mode and Slave
mode common setting.)
[7:0]
01CEh
[7:0]
O
1Bh
Remarks
1h: Master operation
ready (Initial value)
0h: Master operation start
lo
Address
no
Chip ID
gi
Register details
Register
c.
Register List of Slave Mode and Master Mode
[1:0]
0h
0h: High level output
2h: VSYNC output
Other: Setting prohibited
Set to 2h in master mode
Set to 0h in slave mode
[3:2]
0h
0h: High level output
2h: HSYNC output
Other: Setting prohibited
Set to 2h in master mode
Set to 0h in slave mode
2Eh
XVS / XHS Output Waveform in Master Mode
XVS
1 XHS
XHS
INCK = 37.125 MHz: 8 INCK
INCK = 74.25 MHz: 16 INCK
54
IMX174LQJ-C
Gain Adjustment Function
PGC
The Programmable Gain Control (PGC) of this device consists of the analog block and digital block.
The total of analog gain and digital gain can be set up to 48 dB by the GAIN [8:0] register setting.
The value which is ten times the gain is set to register. The same setting is applied in all colors.
Example) When set to 6 dB:
6 × 10 = 60d, GAIN = 03Ch
Analog Gain
Analog + Digital Gain
48.0
45.0
42.0
39.0
36.0
33.0
c.
27.0
In
24.0
21.0
es
18.0
15.0
gi
12.0
lo
9.0
1E0h
1C2h
1A4h
186h
168h
14Ah
10Eh
0D2h
0B4h
096h
Te
078h
05Ah
03Ch
01Eh
000h
0.0
ch
3.0
0F0h
no
6.0
12Ch
Gain [dB]
30.0
S
Register setting value [HEX]
FR
AM
O
Register List of Gain setting
Register details
Register
Chip ID
GAIN [8:0]
Address
Bit
04h
[7:0]
05h
[0]
04h
Initial
value
000h
55
Setting value
Remarks
Setting range
000h to 1E0h
(0d to 480d)
Setting value:
Gain [dB] × 10
IMX174LQJ-C
Black Level Adjustment Function
The black level offset (offset variable range: 000h to 1FFh) can be added relative to the data in which the digital gain
modulation was performed by the BLKLEVEL register. When the BLKLEVEL [8:0] setting is increased by 1 LSB, the
black level is increased by 1 LSB.
* Use with values shown below is recommended.
10 bit output: 03Ch (60 d)
12 bit output: 0F0h (240 d)
Register List of Black level adjustment
Register details
Initial
value
Register
Chip ID
Bit
58h
[7:0]
59h
[0]
0F0h
Setting value
000h to 1FFh
O
S
Te
ch
no
lo
gi
es
In
c.
04h
FR
AM
BLKLEVEL
Address
56
IMX174LQJ-C
Horizontal / Vertical Normal Operation and Inverted Operation
The sensor readout direction (normal / inverted) in vertical direction can be switched by the VREVERSE register
setting and sensor readout direction (normal / inverted) in horizontal direction can be switched by the HREVERSE
register setting. See the section of “Readout Drive Modes” for the order of readout lines in normal and inverted
modes.
Register List of Readout Drive Direction setting
Register details
Bit
Initial
value
[0]
0h
0h: Normal (Initial value)
1h: Inverted
[1]
0h
0h: Normal (Initial value)
1h: Inverted
Register
Chip ID
Address
VREVERSE
02h
Setting value
16h
HREVERSE
In normal mode
In inverted mode
N1-Pin
A1-Pin
A1-Pin
es
In
c.
N1-Pin
V (+)
gi
V (+)
H (+)
N11-Pin
Te
ch
no
lo
H (+)
N11-Pin
A11-Pin
A11-Pin
(Chip outline)
FR
AM
O
S
(Chip outline)
Normal and Inverted Drive Outline in Vertical Direction (TOP VIEW)
In normal mode
N1-Pin
In inverted mode
N1-Pin
A1-Pin
A1-Pin
V (+)
V (+)
H (+)
H (+)
N11-Pin
N11-Pin
A11-Pin
(Chip outline)
A11-Pin
(Chip outline)
Normal and Inverted Drive Outline in Horizontal Direction (TOP VIEW)
57
IMX174LQJ-C
Shutter and Integration Time Settings
This sensor has a global shutter function that integrates to the all line collectively by using memory in each pixel.
This sensor has a variable electronic shutter function that can control the integration time in line units for adjust the
exposure time. This sensor transferred signal to memory in pixel after the exposure (memory transfer), then this
sensor performs output in which readout operation is performed sequentially for each line in sync with the XHS signal.
This sensor has trigger mode that can be controlled exposure start timing and memory transfer timing by trigger.
Note) For integration time control, an image which reflects the setting is output from the frame after the setting
changes.
In this item, the shutter operation and integration time are shown as in the figure below with the time sequence on the
horizontal axis and the vertical address on the vertical axis. For simplification, shutter and readout operation are
noted in line units.
Shutter timing
XVS
Memory transfer timing
Data out period
Memory wait time
XHS
Exposure period
In
c.
Last line
Last-1 line
Last-2 line
Last-3 line
es
Sensor
no
lo
gi
4 line
3 line
2 line
1 line
delay
Output
Effective signal
Te
ch
Blanking
Shutter timing
Memory transfer timing
Data out period
Memory wait time
Ignored
FR
AM
XVS
O
S
Image Drawing of Global Shutter (Normal mode) Operation
XTRIG
XHS
Exposure period
Last line
Last-1 line
Last-2 line
Last-3 line
Sensor
4 line
3 line
2 line
1 line
delay
Output
Blanking
Effective signal
Image Drawing of Global Shutter (Trigger mode) Operation
58
Blanking
IMX174LQJ-C
Global Shutter (Normal Mode) Operation
The integration time can be controlled by varying the electronic shutter timing. In the electronic shutter settings,
the integration time is controlled by the SHS [11:0] register. For setting value of SHS [11:0], see the table “List of
Exposure Setting”. When the sensor is operating in slave mode, the number of lines per frame is determined by
the XVS interval (number of lines), using the input XHS interval as the line unit. When the sensor is operating in
master mode, the number of lines per frame is determined by the VMAX [11:0] register. The number of lines per
frame differs according to the operating mode.
Calculation Formula of Exposure Time
Exposure time [s] = (1 H period) × (Number of lines per frame - SHS) + 13.73 [µs]
*1
: Exposure time error (tOFFSET)
*1
Register List of Shutter setting
Register
Register details
Chip ID
Address
Bit
02h
17h
18h
9Ah
9Bh
[7:0]
[3:0]
[7:0]
[3:0]
VMAX [11:0]
Setting value
4E6h
Set the number of lines per frame (only in master mode)
00Ah
Sets the shutter sweep time.
memory wait time to (Number of lines per frame - 1)
In
c.
SHS [11:0]
Initial
value
*3
*4
6
ROI
10
no
lo
gi
Exposure
Setting value
[H]
ch
10
8 ch LVDS / Maximum frame rate
Frame rate
[frame/s]
10 bit
*1
VTR
12 bit
1
164.5
128.2
1244
1124
1
6
1119
VTR-1
1
1125
S
1080p-Full HD
1254
Te
10
FR
AM
*2
SHS
Setting
value
[DEC]
1253
WUXGA
UXGA
*1
Number of
lines per
frame
[DEC]
O
Drive mode
memory
wait time
[H]
es
List of Exposure Setting
Actually exposure
*4
[ms]
10 bit
12 bit
0.019
0.020
6.045
120
10
8.303
0.019
*2
VTR = ROIWV1 + ROIWV2 + ROIWV3 + ROIWV4 + 38
For the frame rate, see the section “ROI mode” in “Readout Drive Mode”.
Conform to the calculation formula of exposure time. (Number of lines per frame = VTR)
INCK frequency is input by typical value, and t OFFSET (13.73 [µs]) is included.
Communication period
Memory transfer timing
Data out
Exposure time
Time base
XVS
VMAX setting value or XVS input interval
SHS = α
XHS
α [H]
Frame2
Exposure time
Memory wait time
Output
V-Blanking
Frame1
Image Drawing of Global Shutter (Normal Mode)
59
0.020
*3
VTR-10
Shutter timing
7.754
0.021
Memory wait time
V-Blanking
IMX174LQJ-C
Global Shutter (Tigger Mode) Operation
The integration time can be controlled by varying the pulse width that is input to XTRIG pin. The pulse width
designated in XHS unit [H]. For the transition from normal mode to trigger mode, set 1 to the register TRIGEN.
The XVS input signal is ignored during trigger mode operating. In case of inputting trigger continuously, there are
period which prohibit the trigger rise input (tTGPD) and fall input (tGES) based on the previous trigger rise.
When the trigger rise is input before the rise input prohibited period (t TGPD), the frame currently being input
becomes invalid and storage starts over again. (Interrupt operation)
This function is slave mode only. The number of lines per frame differs according to the operating mode.
Calculation Formula of Exposure Time
Exposure time [s] = (XTRIG low level pulse width) + 13.73 [µs]*1
*1
: Exposure time error (tOFFSET)
Register List of shutter setting
02h
TRIGEN
Bit
Initial
value
[0]
0h
13h
0h: Global shutter (normal mode)
1h: Global shutter (trigger mode)
In
Parameter List of Global Shutter (Trigger Mode)
Integration end delay
tTGED
Integration time
tTGSE
Te
Next trigger fall prohibited period (1080p Full-HD)
no
ch
Next trigger fall prohibited period (WUXGA / UXGA / ROI)
tTGES
Next trigger rise prohibited period (WUXGA / UXGA)
tTGPD
O
Next trigger rise prohibited period (ROI)
S
Next trigger rise prohibited period (1080p Full-HD)
FR
AM
Data output delay (WUXGA / UXGA / ROI)
tTGDLY
Data output delay (1080p-Full HD)
*1
Typ.
Max.
Unit
2
―
3
H
2 + tOFFSET
―
3 + tOFFSET
H
1
―
―
H
13
―
―
9
―
―
1254
―
―
1125
―
―
VTR*1
―
―
―
25
―
―
17
―
es
tTGST
lo
Integration start delay
Min.
gi
Symbol
Item
Setting value
c.
Register details
Chip ID
Address
Register
VTR = ROIWV1 + ROIWV2 + ROIWV3 + ROIWV4 + 38
Shutter timing
Communication period
Memory transfer timing
Data out
Exposure time
Time base
XVS
Ignored
tTGSE
Trigger fall prohibited period
tTGES
tTGPD
XTRIG
Trigger rise prohibited period
XHS
Frame1
Exposure time
tTGST
tTGED
Memory wait time
tTGDLY
Output
V-Blanking
Frame1
Image Drawing of Global Shutter (Trigger Mode)
60
V-Blanking
H
H
H
IMX174LQJ-C
Interrupt Operation
The image drawing when the interrupt operation is generated is shown below. When the trigger is raised again
and the next frame is output during read of the frame for which read was started by a trigger rise (Frame1 in the
figure below), Frame1 becomes an invalid frame. Trigger timing of interrupt generating corresponds to tTGPD in
Parameter List of Global Shutter (Trigger Mode)
Shutter timing
Communication period
Memory transfer timing
Exposure time
Data out
Time base
XVS
Ignored
tTGSE
tTGES
tTGPD
XTRIG
XHS
tTGST
tTGST
tTGED
Frame1
Exposure time
Frame2
Exposure time
Memory wait time
tTGDLY
V-Blanking
Memory wait time
Frame1
V-Blanking
Interrupt
c.
Invalid Frame
O
S
Te
ch
no
lo
gi
es
In
Image Drawing of Interrupt Operation in Global Shutter (Trigger Mode)
FR
AM
Output
tTGED
61
Frame2
IMX174LQJ-C
Mode Transitions of Global Shutter Operation
The sensor can be switched between normal mode and trigger mode in global shutter operation by setting the
register TRIGEN. The sensor will transition to normal mode or trigger mode 20H after the register TRIGEN is set.
(The XVS and XTRIG input during transition are prohibited.)
Transition from Normal Mode to Trigger Mode
The sensor will transition from normal mode to trigger mode after setting 1d to register TRIGEN. The XVS input is
ignored after transition to trigger mode. Trigger input is prohibited for a 20H period after the register TRIGEN is set.
When TRIGEN is set during data read, read operation is stopped and that frame becomes an invalid frame.
* The communication is available till 9 H period only when sensor transition to the Trigger mode.
Shutter timing
Communication period
Memory transfer timing
Exposure time
Data out
Time base
Trigger mode start
XVS
XVS input is ignored
XTRIG
Trigger fall prohibited period : 20H
Arbitrary timing: > 0 H
c.
TRIGEN=1d
In
XHS
Extended only when the transition to Trigger mode.
es
Reflection delay(tTGST)
gi
Memory wait time
lo
Exposure time
V-Blanking
no
Output Frame1
Te
ch
Image Drawing of Transition from Normal Mode to Trigger Mode
S
Transition from Trigger Mode to Normal Mode
FR
AM
O
The sensor will transition from trigger mode to normal mode after setting 0d to register TRIGEN. Start XVS input
after transition to normal mode. Set TRIGEN after Next trigger rise prohibited period (tTGPD) has passed. When
TRIGEN is set before tTGPD, read operation is stopped and that frame becomes an invalid frame.
Shutter timing
Communication period
Memory transfer timing
Exposure time
Data out
Time base
Normal mode start
XVS
XVS and XTRIG input prohibited period: 20H
XTRIG
tTGPD
TRIGEN=0d
XHS
tTGED
Output
Memory wait time
V-Blanking
Frame1
V-Blanking
Image Drawing of Transition from Normal Mode to Trigger Mode
62
Arbitrary timing:
>0H
IMX174LQJ-C
Pulse Output Function
This sensor has a pulse output function that indicates each state of shutter operation. The pulse output from
TOUT1 pin and TOUT2 pin. The rise timing and fall timing of pulse are set by Register. For the reference point
(The timing when register value set to 0) to be set, see the table “List of Reference point". The pulse is output
asynchronously with other signals on the basis of the sensor internal timing shown in the “List of Reference point".
Register List of Pulse Output Function
Register details
Bit
Initial
value
[1:0]
0h
TOUT1 pin setting
0h: Low fixed
3h: Pulse output
TOUT2SEL [1:0]
[3:2]
0h
TOUT2 pin setting
0h: Low fixed
3h: Pulse output
TRIG_TOUT1_SEL
[2:0]
[2:0]
0h
TOUT1 pin output selection
0h: Low fixed 1h: Pulse1 output
TRIG_TOUT2_SEL
[2:0]
[6:4]
0h
TOUT2 pin output selection
0h: Low fixed 2h: Pulse2 output
PULSE1_EN_NOR
[0]
0
Pulse1 enable in normal mode
0: disable 1: enable
Chip ID
Address
TOUT1SEL [1:0]
2Fh
c.
32h
es
76h
0
[1]
[2]
no
PULSE1_POL
02h
7Ah
[7:0]
7Bh
[7:0]
FR
AM
PULSE2_EN_NOR
O
S
PULSE1_DN [15:0]
PULSE2_EN_TRIG
PULSE2_UP [15:0]
PULSE2_DN [15:0]
7Eh
0
Pulse1 enable in trigger mode
0: disable 1: enable
Pulse1 polarity selection
0: High active 1: Low active
0000h
Pulse1 active period start timing setting
Designated in line units from reference point
0000h
Pulse1 active period end timing setting
Designated in line units from reference point
[7:0]
Te
78h
[7:0]
ch
77h
PULSE1_UP [15:0]
lo
gi
PULSE1_EN_TRIG
PULSE2_POL
Setting value
In
Register
[0]
0
Pulse2 enable in normal mode
0: disable 1: enable
[1]
0
Pulse2 enable in trigger mode
0: disable 1: enable
[2]
0
Pulse2 polarity selection
0: High active 1: Low active
7Fh
[7:0]
80h
[7:0]
82h
[7:0]
83h
[7:0]
0000h
Pulse2 active period start timing setting
Designated in line units from reference point
0000h
Pulse2 active period end timing setting
Designated in line units from reference point
List of Reference Point
Normal mode
Trigger mode
Reference point of Pulse1
XVS fall edge in N frame
Fall edge of input trigger
Reference point of Pulse2
XVS fall edge in N + 1 frame
Rise edge of input trigger
63
IMX174LQJ-C
Shutter timing
Communication period
Memory transfer timing
Exposure time
Data out
Time base
XVS
N Frame
N + 1 Frame
N + 2 Frame
…
XHS
Memory wait time
Memory wait time
Memory wait time
N + 1 Frame
Exposure time
Output
V-Blanking
N + 2 Frame
Exposure time
N Frame
V-Blanking
N + 3 Frame
Exposure time
N + 1Frame
V-Blanking
N + 2 frame
V-Blanking
TOUT1
PULSE1_POL=0d
PULSE1_EN_NOR=1d
Designate by PULSE1_UP
Designate by PULSE1_UP
Designate by PULSE1_DN
Designate by PULSE1_DN
TOUT2
PULSE2_POL=0d
PULSE2_EN_NOR=1d
Designate by PULSE2_UP
Designate by PULSE2_DN
Image Drawing of Pulse Output Function in Global Shutter (Normal Mode)
In
c.
In normal mode, TOUT1 and TOUT2 are output alternately each time inputting XVS.
es
Shutter timing
Communication period
Memory transfer timing
Exposure time
gi
Data out
Ignored
no
XVS
lo
Time base
Trigger fall prohibited period
tTGSE
tTGES
tTGPD
ch
XTRIG
Te
XHS
Trigger rise prohibited period
Output
TOUT1
PULSE1_POL=0d
TRIG_TOUT1_SEL=1d
PULSE1_EN_TRIG=1d
O
FR
AM
tTGST
S
Frame1
Exposure time
tTGED
Memory wait time
V-Blanking
Designate by
PULSE1_UP = 2d
Frame1
Designate by
PULSE1_DN = 14d
TOUT2
PULSE2_POL=0d
TRIG_TOUT2_SEL=2d
PULSE2_EN_TRIG=1d
Designate by PULSE2_UP = 2d
Designate by PULSE2_DN = 1256d
Image Drawing of Pulse Output Function in Global Shutter (Trigger Mode)
64
V-Blanking
IMX174LQJ-C
Signal Output
Output Pin Settings
This sensor supports Low voltage LVDS serial (2 ch / 4 ch / 8 ch switching) DDR output.
In addition, the data rate per channel is adjustable. The table below shows the output format settings.
Register List of Output Settings
Register details
Register
Chip ID
STBLVDS
02h
OPORTSEL [2:0]
FREQ [1:0]
Address
Bit
Initial
value
05h
[7:4]
0h
The un-using LVDS channel go into standby
1Ch
[6:4]
1h
Number of output channel setting
(Refer the list of output setting below)
21h
[1:0]
0h
Frame rate adjust
(Refer the list of output setting below)
Setting value
List of Output Setting
Register setting
OPORTSEL
FREQ
c.
STBLVDS
Number of
LVDS
channel
In
Drive mode
WUXGA
UXGA
ROI
1h
1h
2h
3h
lo
0h
1h
8 ch
gi
0h
es
0h
4 ch
0h
2 ch
ch
4h
Te
2h
no
1h
1h
1h
FR
AM
1h
O
1080p-Full HD
2h
8 ch
2h
S
0h
0h
0h
3h
Data rate
per channel
[Mbps/ch]
Total data rate
[Gbps]
594
4.752
297
2.376
148.5
1.188
594
2.376
297
1.188
594
1.188
445.5
3.564
222.75
1.782
111.375
0.891
445.5
1.782
222.75
0.891
445.5
0.891
4 ch
1h
4h
0h
2 ch
Each output pin is shown in the table below when setting low-voltage LVDS serial 2 ch / 4 ch / 8 ch output.
In 2 ch and 4 ch output, set the un-using channels to standby.
Output Pins for Low Voltage LVDS Serial
Low voltage LVDS serial DDR output
Output pins
2 ch
4 ch
8 ch
DLOPA / DLOMA
Hi-Z
Hi-Z
Ch 7
DLOPB / DLOMB
Hi-Z
Hi-Z
Ch 5
DLOPC / DLOMC
Hi-Z
Ch 3
Ch 3
DLOPD / DLOMD
Ch 1
Ch 1
Ch 1
DLOPE / DLOME
Ch 2
Ch 2
Ch 2
DLOPF / DLOMF
Hi-Z
Ch 4
Ch 4
DLOPG / DLOMG
Hi-Z
Hi-Z
Ch 6
DLOPH / DLOMH
Hi-Z
Hi-Z
Ch 8
65
IMX174LQJ-C
Low-voltage LVDS serial 2 ch / 4 ch / 8 ch output format is shown in the figure below.
When setting 2 ch, after four data of SAV is output in the order of CH1 and CH2 pixel data is repeatedly output in
the same order and then four data of EAV is output in the same order to CH1 and CH2 respectively.
When setting 4 ch, after four data of SAV is output in the order of CH1, CH2, CH3 and CH4 pixel data is
repeatedly output in the same order and then four data of EAV is output in the same order to CH1, CH2, CH3 and
CH4 respectively.
When setting 8 ch, output in a format similar to the 2 ch and 4 ch output as shown below.
Data is sent MSB first. For details, see drive timing in each mode in the section of "Readout Drive Mode".
2 ch
8 ch
EAV
4th
EAV
3rd
EAV
3rd
EAV
4th
EAV
4th
EAV
3rd
EAV
3rd
EAV
4th
EAV
4th
EAV
4th
EAV
4th
EAV
2nd
EAV
2nd
EAV
2nd
EAV
2nd
EAV
4th
EAV
3rd
EAV
3rd
EAV
3rd
EAV
3rd
66
EAV
2nd
EAV
2nd
EAV
2nd
EAV
2nd
P 8n
EAV
1st
EAV
1st
P 8n+1
P 8n+2
EAV
1st
EAV
1st
P 8n+3
EAV
1st
EAV
1st
EAV
1st
P 8n+4
P 8n+6
P 8n+7
Output Format of Low voltage LVDS Serial 2 ch / 4 ch / 8 ch
EAV
1st
・・・
・・・
P 8n+5
・・・
・・・
・・・
・・・
・・・
P2
P3
P4
P5
P6
P7
・・・
P0
P1
SAV
4th
SAV
4th
SAV
4th
SAV
4th
SAV
4th
SAV
3rd
SAV
4th
SAV
4th
SAV
3rd
SAV
3rd
SAV
3rd
SAV
2nd
SAV
2nd
SAV
1st
SAV
3rd
EAV
4th
EAV
3rd
EAV
2nd
FR
AM
EAV
1st
O
S
EAV
3rd
Te
SAV
3rd
EAV
3rd
EAV
2nd
SAV
2nd
EAV
4th
EAV
2nd
EAV
1st
P 4n+3
CH8
SAV
2nd
EAV
3rd
EAV
1st
P 4n+2
・・・
gi
EAV
2nd
P 4n+1
・・・
P3
SAV
1st
P 4n
EAV
1st
・・・
P2
SAV
4th
SAV
1st
・・・
P1
SAV
4th
SAV
3rd
CH7
SAV
1st
P0
SAV
4th
SAV
3rd
SAV
2nd
lo
SAV
4th
SAV
3rd
SAV
2nd
SAV
1st
no
SAV
3rd
SAV
2nd
SAV
1st
CH4
ch
SAV
2nd
SAV
1st
CH3
CH6
EAV
4th
SAV
1st
CH2
CH5
EAV
4th
CH1
SAV
2nd
CH4
DCK
SAV
1st
4 ch
es
CH3
SAV
2nd
c.
SAV
4th
SAV
3rd
SAV
3rd
In
SAV
2nd
SAV
2nd
SAV
1st
SAV
1st
EAV
4th
EAV
4th
CH2
SAV
1st
EAV
3rd
EAV
3rd
・・・
EAV
2nd
・・・
P1
EAV
2nd
P0
SAV
4th
P 2n
SAV
4th
SAV
3rd
EAV
1st
SAV
3rd
SAV
2nd
EAV
1st
SAV
2nd
CH2
CH1
P 2n+1
CH1
SAV
1st
DCK
SAV
1st
DCK
IMX174LQJ-C
Output Pin Bit Width Selection
The output pin width can be selected from 10-bit or 12-bit output using register ADBIT, ODBIT. Sync code is output
according to bit width setting of these register.
Register List of Bit Width Selection
Register details
Register
Chip ID
Address
Bit
Initial
value
14h
[0]
1h
0h: 10 bit
1h: 12 bit
1Ch
[0]
1h
0h: 10 bit
1h: 12 bit
ADBIT
02h
ODBIT
Remarks
Setting value
Set same value to both
ADBIT and ODBIT
…
…
P0
CHx
(x=1-8)
P1
DCK
MSB First
…
P1[0]
c.
P1[1]
P1[2]
P1[3]
P1[4]
In
P1[5]
P1[6]
es
P1[7]
P1[8]
P1[9]
P0[0]
P0[1]
P0[2]
P0[3]
P0[4]
P0[5]
P0[6]
P0[7]
CHx
(x=1-8)
P0[8]
P0[9]
DCK
lo
gi
Example of Data format in low-voltage LVDS serial 10-bit output
no
ch
…
P1[0]
P1[1]
P1[2]
P1[4]
P1[5]
P1[6]
P1[7]
P1[8]
P1[9]
P1[10]
P1[11]
P0[0]
P0[1]
P0[2]
S
P0[4]
P0[5]
P0[6]
O
P0[7]
P0[8]
P0[9]
P0[10]
FR
AM
CHx
(x=1-8)
P0[11]
DCK
P0[3]
Te
MSB First
P1[3]
…
…
P0
CHx
(x=1-8)
P1
DCK
Example of Data format in low-voltage LVDS serial 12-bit output
Output Signal Range
The sensor output has either a 10-bit or 12-bit gradation, but output is not performed over the full range, and the
maximum output value is the “3FFh - 1” (10-bit output) and the “FFFh - 1” (12-bit output). The minimum value is
001h. The output range for each output gradation is shown in the table below. The maximum level and the
minimum level are output only in the sync code. See the item of “Sync Codes” in the section of “Operating Modes”
for the sync codes.
Output Gradation and Output Range
Output value
Output gradation
Min.
Max.
10 bit
001h
3FEh
12 bit
001h
FFEh
67
IMX174LQJ-C
Register Hold Setting
Register setting can be transmitted with divided to several frames and it can be reflected globally at a certain frame
by the register REGHOLD. Setting REGHOLD = 1 at the start of register communication period prevents the
registers that are set thereafter from reflecting at the frame reflection timing. The registers that are set when setting
REGHOLD = 1 are reflected globally by setting REGHOLD = 0 at the end of communication period of the desired
frame to reflect the register.
Register List of Register Hold
Register
REGHOLD
Register details
Chip ID
Address
02h
0Ch
Bit
Initial
value
[0]
1h
Setting value
0h: Invalid
1h: Valid (Register hold)
: Communication period
XVS
REGHOLD = 1
Register setting D
Register setting A
Register setting B
Register setting C
In
c.
XHS
REGHOLD = 0
Register A
is not reflected.
Register C
is not reflected.
ch
no
lo
gi
es
Register B
is not reflected.
FR
AM
O
S
Te
Register Hold Setting
68
Register A
Register B
Register C
Register D
are reflected.
IMX174LQJ-C
Mode Transition
The Mode transition between operations is shown below. These examples shown in case that setting is completed
within one communication timing.
List of Mode Transition
Transition
State
→
→
→
→
ROI
WUXGA
UXGA
WUXGA
UXGA
Via the Standby state
is unnecessary
ROI
- Transition between modes other than the above
- Change the input frequency of INCK
- Change the data rate (change the register FREQ)
- Change the number of output channels (change the register OPORTSEL)
- Change the bit width (change the register ADBIT, ODBIT)
O
S
Te
ch
no
lo
gi
es
In
c.
When changing input INCK frequency, care should be taken not to be input pulses whose width are shorter than
the High / Low level width in front and behind of the INCK pulse at the frequency change. If the pulses above
generate at the frequency change, change INCK frequency during system reset in the state of XCLR = Low, and
then perform system clear in the state of XCLR = High following the item of "Power on sequence" in the section of
"Power on / off sequence". Execute initial setting again because the register settings become default state after
system clear.
FR
AM
*1
Via the standby state
is necessary
69
IMX174LQJ-C
Power-on and Power-off Sequence
Power-on sequence
Follow the sequence below to turn On the power supplies.
1.
2.
3.
4.
Turn On the power supplies so that the power supplies rise in order of 1.2 V power supply (DVDD) →1.8 V power
supply (OVDD) → 3.3 V power supply (AVDD). In addition, all power supplies should finish rising within 200 ms.
The register values are undefined immediately after power-on, so the system must be cleared. Hold XCLR at
Low level for 500 ns or more after all the power supplies have finished rising. (The register values after a
system clear are the default values.)
In addition, hold XCE to High level during this period. Rise XCE after 1.8 V power supply (OV DD), so hold XCE
at High level until INCK is input.
Start the input of INCK after turning the level of XCLR into the high.
Make the sensor setting by register communication after the system clear. A period of 0 µs or more should be
provided after setting XCLR High before inputting the communication enable signal XCE.
≤ 200 ms
≥ 0 ms
≥ 0 ms
3.3 V power supply (AVDD)
In
c.
3.15 V
≥ 1 µs
≥ 0.5 µs
Te
ch
INCK
≥ 20 µs
O
S
XCLR
Rise up after OVDD
FR
AM
XVS/XHS
1.2 V power supply (DVDD)
no
lo
≥ 0 ms
gi
1.1 V
XCE
1.8 V power supply (OVDD)
es
1.7 V
In slave mode: Rise up after OVDD
In master mode: Depend on the OVDD supply rise.
Power-on Sequence
70
IMX174LQJ-C
Power-off Sequence
Turn Off the power supplies so that the power supplies fall in order of 3.3 V power supply (AVDD) → 1.8 V power
supply (OVDD) → 1.2 V power supply (DVDD). In addition, all power supplies should start to falling within 200 ms.
Set each digital input pin (INCK, XCE, SCK, SDI, XCLR, XMASTER, XTRIG, XVS, XHS) to 0 V or high impedance
before the 1.8 V power supply (OVDD) falls.
≤ 200 ms
≥ 0 ms
≥ 0 ms
3.3 V power supply (AVDD)
3.15 V
1.8 V power supply (OVDD)
1.7 V
1.2 V power supply (DVDD)
1.1 V
FR
AM
O
S
Te
ch
no
lo
gi
es
In
c.
Power-off Sequence
71
IMX174LQJ-C
Sensor Setting Flow
Setting Flow in Sensor Slave Mode
The figure below shows operating flow in sensor slave mode.
For details of "Power on" to "System clear", see the item of "Power on sequence" in this section. For details of
"Standby cancel" to "Wait for image stabilization", see the item of "Standby mode". “Standby setting (power save
mode) can be made by setting the STANDBY register to “1” during “Operation”.
Start
Pin settings
Power-ON
System clear
XCLR pin: Low → High
In
c.
INCK input
gi
es
Register initial settings
Standby setting
(Power save mode)
STANDBY = 1
Te
ch
Standby cancel
STANDBY = 0
no
lo
Register settings
FR
AM
O
S
Wait for internal regulator stabilization
> 1 ms
Global shutter
(Normal mode)
Global shutter
(Trigger mode)
XVS / XHS
input start
XTRIG
input start
XTRIG
input stop
Wait for image stabilization
> 8 frames
Register changes
Shutter
Gain
Other
Streaming
Streaming
Sensor Setting Flow (Sensor Slave Mode)
72
XVS / XHS
input stop
IMX174LQJ-C
Sensor Flow in Sensor Master Mode
The figure below shows operating flow in sensor master mode.
For details of "Power on" to "System clear", see the item of "Power on sequence" in this section. For details of
"Standby cancel" to "Wait for image stabilization", see the item of "Standby mode". In master mode, “Master mode
start” by setting the master mode start register XMSTA to “0” after “Wait for internal regulator stabilization”.
“Standby setting (power save mode) can be made by setting the STANDBY register to “1” during “Operation”. This
time, set "master mode stop" by setting XMSTA to "1".
Start
Pin settings
Power-ON
System clear
XCLR pin: Low → High
c.
INCK input
es
In
Register initial settings
no
Standby setting
(Power save mode)
STANDBY = 1
Te
ch
Standby cancel
STANDBY = 0
lo
gi
Register settings
O
S
Wait for internal regulator stabilization
> 1 ms
Master mode stop
XMSTA = 1
FR
AM
Master mode start
XMSTA = 0
Wait for image stabilization
> 8 frames
Register changes
Shutter
Gain
Other
Streaming
Sensor Setting Flow (Sensor Master Mode)
73
IMX174LQJ-C
Peripheral Circuit
Power Pins
AVDD
3.3 V
AVDD
3.3 V
DVDD
1.2 V
OVDD
1.8 V
IMX174
A4
0.1 μF
0.1 μF
A5
VDDH2
VDDH16
F1
A6
VDDH3
VDDH17
F10
0.1 μF
0.1 μF
4.7 μF
0.1 μF
22 μF
0.1 μF
4.7 μF
0.1 μF
A8
B4
B5
0.1 μF
4.7 μF
0.1 μF
VSSH1
VDDH9
VDDH10
C2
VDDH11
VDDH12
VSSH2
B7
VSSH3
B8
VDDH14
0.1 μF
E11
0.1 μF
VDDH15
VDDL2
VDDM2
K1
E7
VDDL3
VDDM3
L1
F4
VDDL4
VSSL1
D5
F8
VDDL5
0.1 μF
1.0 μF
0.1 μF
1.0 μF
0.1 μF
1.0 μF
0.1 μF
G4
G8
VSSH4
B9
VSSH5
C3
VSSH6
C10
VSSH7
D10
VSSH8
E8
H4
1.0 μF
J11
VSSH9
E9
E10
VSSH11
F2
VSSH12
F9
gi
VSSH10
VSSH13
G9
VSSH14
G10
VDDL6
VDDL7
lo
4.7 μF
GND
K11
L11
0.1 μF
VSSL2
D6
VSSL3
G3
VSSL4
H3
VSSL5
H10
VSSL6
J2
VSSL7
J10
VSSL8
K10
VSSL9
L10
VSSM1
K2
0.01 μF
1.0 μF
0.01 μF
1.0 μF
VDDL8
0.1 μF
H11
VDDH13
0.1 μF
D11
0.1 μF
B6
0.1 μF
D1
4.7 μF
G11
4.7 μF
E6
0.1 μF
VDDH8
C1
C11
4.7 μF
VDDH6
0.1 μF
4.7 μF
VDDH19
H1
0.1 μF
F11
0.1 μF
A9
4.7 μF
VDDH5
VDDH18
VDDM1
c.
22 μF
VDDH4
VDDL1
In
0.1 μF
4.7 μF
4.7 μF
E5
0.1 μF
es
22 μF
22 μF
1.0 μF
0.1 μF
A7
4.7 μF
4.7 μF
1.0 μF
no
22 μF
IMX174
B3
VDDL9
VDDL10
VDDL11
VDDL12
VSSM2
L2
VSSM3
N3
VSSM4
N9
GND
ch
4.7 μF
VDDH7
Te
4.7 μF
VDDH1
GND
O
S
GND
FR
AM
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume
responsibility for any problems arising out of the use of these circuits or for any infringement of third party and other
right due to same.
74
IMX174LQJ-C
I/O signal pins
IMX174
10 Ω
J1
INCK
IMX174
10 Ω
TOUT1
C6
DLOPA
10 Ω
Low voltage LVDS receiver
+
K4
100 Ω
10 Ω
J3
XCLR
K3
XMASTER
TOUT2
C7
SDO
J4
10 Ω
DLOMA
L4
DLOPB
K5
Ch7
10 Ω
+
100 Ω
10 Ω
J5
XCE
J6
SCK
10 Ω
VCAP
DLOMB
L5
DLOPC
M4
A3
0.22 μF
10 Ω
SDI
J8
XTRIG
VCP1
E1
VRL1
D2
VRL2
D3
VRL3
E2
VRL4
E3
VRL5
F3
4.7 μF
10 Ω
OVDD
1.8 V
+
100 Ω
GND
J7
Ch5
DLOMC
N4
DLOPD
M5
Ch3
4.7 μF
+
100 Ω
Ch1
GND
DLOMD
N5
DLOPE
M7
10 kΩ
H8
XHS
G1
VRL6
G2
VRL7
H2
4.7 μF
DLOPF
es
VCP2
4.7 μF
10 kΩ
10 Ω
H9
XVS
lo
no
ch
Te
+
M8
100 Ω
DLOMF
N8
DLOPG
K7
gi
GND
Ch2
N7
In
DLOME
OVDD
1.8 V
+
100 Ω
c.
10 Ω
Ch4
+
100 Ω
DLOMG
L7
DLOPH
K8
Ch6
+
FR
AM
O
S
100 Ω
DLOMH
L8
DLCKP
M6
Ch8
+
100 Ω
DLCKM
DCK
N6
Terminal resistance: 100Ω
Isometric wiring of differential signal
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume
responsibility for any problems arising out of the use of these circuits or for any infringement of third party and other
right due to same.
75
IMX174LQJ-C
Spot Pixel Specifications
(Tj = 60 ˚C)
Maximum distorted pixels in each zone
Type of distortion
Level
0 to II'
Black and white
30 % ≤
D
5.6 mV ≤
D
pixels at high light
White pixels in
the dark
Black pixels at
Ineffective
OB
OB
≤ 680 mV
method
No evaluation criteria applied
0
Remarks
1
No evaluation
120
D
signal saturated
Note)
17
Measurement
Effective
2
criteria applied
No evaluation criteria applied
1/30 s storage
3
1. Zone is specified based on all-pixel drive mode
2. D…Spot pixel level
3. See the Spot Pixel Pattern Specifications for the specifications in which pixel and black pixel are close.
6
OB side ignored area
(1, 7)
4
Effective OB
lo
60
(237, 127)
no
184
ch
(661, 311)
Zone Ⅱ’
gi
56
(93, 67)
(1936, 10)
es
(1, 11)
(1936, 6)
In
(1, 1)
c.
Sport Pixel Zone Definition
Zone Ⅱ
Zone Ⅰ
Zone 0
144
424
616
424
144
92
FR
AM
O
S
92
Te
616
(1276, 926)
184
(1700, 1110)
60
(1844, 1170)
56
(1936, 1226)
76
IMX174LQJ-C
Notice on White Pixels Specifications
In
c.
After delivery inspection of CMOS image sensors, cosmic radiation may distort pixels of CMOS image sensors,
and then distorted pixels may cause white point effects in dark signals in picture images. (Such white point
effects shall be hereinafter referred to as "White Pixels".) Unfortunately, it is not possible with current scientific
technology for CMOS image sensors to prevent such White Pixels. It is recommended that when you use CMOS
image sensors, you should consider taking measures against such White Pixels, such as adoption of automatic
compensation systems for White Pixels in dark signals and establishment of quality assurance standards.
Unless the Seller's liability for White Pixels is otherwise set forth in an agreement between you and the Seller,
Sony Corporation or its distributors (hereinafter collectively referred to as the "Seller") will, at the Seller's
expense, replace such CMOS image sensors, in the event the CMOS image sensors delivered by the Seller
are found to be to the Seller's satisfaction, to have over the allowable range of White Pixels as set forth above
under the heading "Spot Pixels Specifications", within the period of three months after the delivery
date of such CMOS image sensors from the Seller to you; provided that the Seller disclaims and will not
assume any liability after you have incorporated such CMOS image sensors into other products.
Please be aware that Seller disclaims and will not assume any liability for (1) CMOS image sensors fabricated,
altered or modified after delivery to you, (2) CMOS image sensors incorporated into other products, (3) CMOS
image sensors shipped to a third party in any form whatsoever, or (4) CMOS image sensors delivered to you
over three months ago. Except the above mentioned replacement by Seller, neither Sony Corporation nor its
distributors will assume any liability for White Pixels. Please resolve any problem or trouble arising from or in
connection with White Pixels at your costs and expenses.
es
[For Your Reference] The Annual Number of White Pixels Occurrence
Te
ch
no
lo
gi
The chart below shows the predictable data on the annual number of White Pixels occurrence in a single-story
building in Tokyo at an altitude of 0 meters. It is recommended that you should consider taking measures against
the annual White Pixels, such as adoption of automatic compensation systems appropriate for each annual
number of White Pixels occurrence.
The data in the chart is based on records of past field tests, and signifies estimated number of White Pixels
calculated according to structures and electrical properties of each device. Moreover, the data in the chart is
for your reference purpose only, and is not to be used as part of any CMOS image sensor specifications.
S
Example of Annual Number of Occurrence
Annual number of occurrence
5.6 mV or higher
10.0 mV or higher
24.0 mV or higher
50.0 mV or higher
72.0 mV or higher
4.6
2.9
1.5
0.9
0.7
FR
AM
O
White Pixel Level (in case of integration time = 1/30 s)
(Tj = 60 ˚C)
pcs
pcs
pcs
pcs
pcs
Note 1) The above data indicates the number of White Pixels occurrence when a CMOS image sensor is left
for a year.
Note 2) The annual number of White Pixels occurrence fluctuates depending on the CMOS image sensor storage
environment (such as altitude, geomagnetic latitude and building structure), time (solar activity effects)
and so on. Moreover, there may be statistic errors. Please take notice and understand that this is an
example of test data with experiments that have being conducted over a specific time period and in
a specific environment.
Note 3) This data does not guarantee the upper limits of the number of White Pixels occurrence.
For Your Reference:
The annual number of White Pixels occurrence at an altitude of 3,000 meters is from 5 to 10 times more than that
at an altitude of 0 meters because of the density of the cosmic rays. In addition, in high latitude geographical areas
such as London and New York, the density of cosmic rays increases due to a difference in the geomagnetic
density, so the annual number of White Pixels occurrence in such areas approximately doubles when compared
with that in Tokyo.
77
IMX174LQJ-C
Measurement Method for Spot Pixels
After setting to standard imaging condition II, and the device driver should be set to meet bias and clock voltage
conditions. Configure the drive circuit according to the example and measure.
1.
Black or white pixels at high light
After adjusting the luminous intensity so that the average value VG of the Gb / Gr signal outputs is 1016 mV,
measure the local dip point (black pixel at high light, ViB) and peak point (white pixel at high light, ViK) in the
Gr / Gb / R / B signal output Vi (i = Gr / Gb / R / B), and substitute the value into the following formula.
Spot pixel level D = ((ViB or ViK) / Average value of Vi) × 100 [%]
White pixel
ViB
ViK
Vi (i = R, G, B, VG = 1016 mV )
Black pixel
In
c.
Signal output waveform of R / G / B channel
White pixels in the dark
Set the device to a dark setting and measure the local peak point of the signal output waveform, using the
average value of the dark signal output as a reference.
3.
Black pixels at signal saturated
Set the device to operate in saturation and measure the local dip point, using the OB output as a reference.
Black Pixel
Vsat ( Min. = 850 mV )
OB output
O
S
Level D
Te
ch
no
lo
gi
es
2.
FR
AM
Signal output waveform of R / G / B channel
78
IMX174LQJ-C
Spot Pixel Pattern Specification
White Pixel, Black Pixel and Bright Pixel are judged from the pattern whether they are allowed or rejected, and
counted.
List of White Pixel, Black Pixel and Bright Pixel Pattern
1
●
2
●
White pixel
Black pixel
Bright pixel
●
Rejected
Rejected
Rejected
Rejected
Rejected
Rejected
Allowed
Allowed
Allowed
●
● ●
es
In
3
Pattern
c.
No.
Allowed
Allowed
Allowed
Allowed
lo
Rejected
gi
●
4
ch
no
●
●
●
Te
Allowed
O
S
5
FR
AM
Note) 1. “● ” shows the position of white pixel, black pixel and bright pixel.
White pixel, black pixel and bright pixel are specified separately according the pattern.
(Example: If a black pixel and a white pixel is in the pattern No.1 respectively, they are not judged to
be rejected.)
2. When one or more spot pixels indicated “Rejected” is selected and removed.
3. Spot pixels indicated “Allowed” are not the subject of selected rejection. They are counted including
the number of allowable spot pixels by zone.
4. Spot pixels other than described in the table above are all counted including the number of allowable
spot pixels by zone.
79
S
O
FR
AM
es
gi
lo
no
ch
Te
c.
In
IMX174LQJ-C
Marking
80
IMX174LQJ-C
Notes On Handling
1. Static charge prevention
Image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
(1) Either handle bare handed or use non-chargeable gloves, clothes or material.
Also use conductive shoes.
(2) Use a wrist strap when handling directly.
(3) Install grounded conductive mats on the floor and working table to prevent the generation of static
electricity.
(4) Ionized air is recommended for discharge when handling image sensors.
(5) For the shipment of mounted boards, use boxes treated for the prevention of static charges.
2. Protection from dust and dirt
Image sensors are packed and delivered with care taken to protect the element glass surfaces from
harmful dust and dirt. Clean glass surfaces with the following operations as required before use.
no
lo
gi
es
In
c.
(1) Perform all lens assembly and other work in a clean environment (class 1000 or less).
(2) Do not touch the glass surface with hand and make any object contact with it.
If dust or other is stuck to a glass surface, blow it off with an air blower.
(For dust stuck through static electricity, ionized air is recommended.)
(3) Clean with a cotton swab with ethyl alcohol if grease stained. Be careful not to scratch the glass.
(4) Keep in a dedicated case to protect from dust and dirt. To prevent dew condensation, preheat or
precool when moving to a room with great temperature differences.
(5) When a protective tape is applied before shipping, remove the tape applied for electrostatic
protection just before use. Do not reuse the tape.
ch
3. Installing (attaching)
FR
AM
O
S
Te
(1) If a load is applied to the entire surface by a hard component, bending stress may be generated
and the package may fracture, etc., depending on the flatness of the bottom of the package.
Therefore, for installation, use either an elastic load, such as a spring plate, or an adhesive.
(2) The adhesive may cause the marking on the rear surface to disappear.
(3) If metal, etc., clash or rub against the package surface, the package may chip or fragment and
generate dust.
(4) Acrylate anaerobic adhesives are generally used to attach this product. In addition, cyanoacrylate
instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives to hold
the product in place until the adhesive completely hardens. (Reference)
(5) Note that the sensor may be damaged when using ultraviolet ray and infrared laser for mounting it.
81
IMX174LQJ-C
4. Recommended reflow soldering conditions
The following items should be observed for reflow soldering.
(1) Temperature profile for reflow soldering
Control item
Profile (at part side surface)
1. Preheating
150 to 180 °C
60 to 120 s
2. Temperature up (down)
+4 °C/s or less (– 6 °C/s or less)
3. Reflow temperature
Over 230 °C
10 to 30 s
Max. 5 °C/s
4. Peak temperature
Max. 240 ± 5 °C
Temperature
Peak 240 ± 5 °C
230 °C
Max. 5 °C/s
180 °C
– 6 °C/s or less
+4 °C/s
or less
c.
10 to 30 s
In
150 °C
60 to 120 s
Preheating
Time
gi
es
Reflow
lo
(2) Reflow conditions
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AM
(3) Others
O
S
Te
ch
no
(a) Make sure the temperature of the upper surface of the seal glass resin adhesive portion of the
package does not exceed 245 °C.
(b) Perform the reflow soldering only one time.
(c) Finish reflow soldering within 72 h after unsealing the degassed packing.
Store the products under the condition of temperature of 30 °C or less and humidity of
70 % RH or less after unsealing the package.
(d) Perform re-baking only one time under the condition at 125 °C for 24 h.
(a) Carry out evaluation for the solder joint reliability in your company.
(b) After the reflow, the paste residue of protective tape may remain around the seal glass.
(The paste residue of protective tape should be ignored except remarkable one.)
(c) Note that X-ray inspection may damage characteristics of the sensor.
5. Others
(1) Do not expose to strong light (sun rays) for long periods, as the color filters of color devices will
be discolored.
(2) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage
or use in such conditions.
(3) This product is precision optical parts, so care should be taken not to apply excessive mechanical
shocks or force.
(4) Note that imaging characteristics of the sensor may be affected when approaching strong
electromagnetic wave or magnetic field during operation.
(5) Note that image may be affected by the light leaked to optical black when using an infrared cut
filter that has transparency in near infrared ray area during shooting subjects with high luminance.
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IMX174LQJ-C
Package Outline
FR
AM
O
S
Te
ch
no
lo
gi
es
In
c.
(Unit: mm)
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IMX174LQJ-C
List of Trademark Logos and Definition Statements
* Exmor is a trademark of Sony Corporation. The Exmor is a version of Sony's high performance CMOS image sensor with
high-speed processing, low noise and low power dissipation by using column-parallel A/D conversion.
FR
AM
O
S
Te
ch
no
lo
gi
es
In
c.
* Pregius is a trademark of Sony Corporation. The Pregius is global shutter pixel technology for active pixel-type CMOS image sensors that use
Sony’s low-noise CCD structure, and realizes high picture quality.
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