NAND Error Correction Code
Choices
Pete Feeley
Strategic Marketing – NAND
Micron Technology, Inc
©2006 Micron Technology, Inc. All rights reserved. Products are warranted only to meet Micron’s production data sheet specifications. Information, products
and/or specifications are subject to change without notice. All information is provided on an “AS IS” basis without warranties of any kind. Dates are estimates
only. Drawings not to scale. Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective
owners.
San José, CA USA
August 2006
1
NAND Error Correction Choices
 Leading edge NAND requires multiple bit error
correction
• Hamming codes only correct single bit errors
• Reed-Solomon
• Binary BCH
 Metrics
• Overhead requirements
• Correction performance
 Reed-Solomon and binary BCH have different
underlying structures: one is symbol-based and
the other is binary
San José, CA USA
August 2006
2
Comparing Symbol-Based to
Binary Error Coding
Symbol-Based Code
Symbol
Symbol
Symbol
Symbol
Binary Code
Symbol
Coding
Sector
 Symbol length: m = 4 bits
Coding
Sector
 Symbol length: m = 1 bit
 Code length: n = 5 symbols
 Code length: n = 20 symbols
 Bit errors = 7
 Bit errors = 7
 Symbol errors = 4
 Symbol errors = 7
 Error correction: t = 4
 Error correction: t = 7
 Max error pattern: t * m = 16 bits
 Max error pattern: t * m = 7 bits
Note – Code examples were shortened for demonstration purposes. Actual codes have strict relationships among the parameters that define the code like n, m and t.
San José, CA USA
August 2006
3
Comparing Symbol-Based to
Binary Error Coding
•Common ECC Choices for MLC NAND
Reed-Solomon
Symbol length: m = 9 bits
Code length: n = 470 symbols
(528 bytes)
Error correction: t = 4
Redundancy1
requirements: 2tm = 72 bits
Max error pattern: t *m = 36 bits
RS requires 39% more code
redundancy for a given error
correction.
Binary BCH
Symbol length: m = 1 bit
Code length: n = 4224 symbols
(528 bytes)
Error correction: t = 4
Redundancy1
requirements: 13t = 52 bits
Max error pattern: t *m = 4 bits
RS can correct more bit errors
but what does that mean for
NAND Flash?
Note: (1) Redundancy is also referred as code overhead or parity and for NAND is typically stored in the spare area
San José, CA USA
August 2006
4
Comparing Error Correction
Performance
Comparison of correction performance must be done in the context
of the channel error conditions

NAND error events are random and uncorrelated

For NAND, Reed-Solomon corrects a few percent more error
conditions than binary BCH

A few percent change in error correction garners a generally
insignificant improvement in the application bit error rate
Error Performance Improvement:
Reed-Solomon vs. Binary BCH

10%
9%
8%
7%
t=8
6%
5%
4%
t=6
3%
t=4
2%
1%
t=1
t=2
0%
1.E-01 1.E-03 1.E-05 1.E-07 1.E-09 1.E-11 1.E-13 1.E-15
San José, CA USA
August 2006
Raw NAND Bit Error Rate
Typical Application
Bit Error Rates(1)
Designed
Error
Correction
Level
ReedSolomon
Binary
BCH
t=1
2.34e-15
2.34e-15
t=2
7.69e-15
7.73e-15
t=4
3.41e-15
3.47e-15
t=6
3.59e-14
3.72e-14
t=8
3.09e-15
3.28e-15
Notes:
1. Bit error rate is the ratio of error bits to the total number of bits read.
5
Conclusions
 Binary BCH is a better ECC solution for
NAND than Reed-Solomon
• 39% Reduction in code redundancy
• Practically identical application-level performance
San José, CA USA
August 2006
6
Thank You!
Contact Information
Peter Feeley
Micron Technology
pfeeley@micron.com
208-363-2693
©2006 Micron Technology, Inc. All rights reserved. Products are warranted only to meet Micron’s production data sheet specifications. Information, products
and/or specifications are subject to change without notice. All information is provided on an “AS IS” basis without warranties of any kind. Dates are estimates
only. Drawings not to scale. Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective
owners.
San José, CA USA
August 2006
7