ECP2036 Microprocessors System and Interfacing
5.1
Chapter 5: Interrupt System
8051 INTERRUPT ORGANIZATION
The 8051 has five interrupt sources (The 8052 has six). These include two external interrupts ( INT0 and INT1),
two timer interrupts, and a serial port interrupt. All interrupts are disabled after a system reset and are enabled
individually by software.
External Interrupts
( INT0 & INT1)
These can either be level activated or transition-activated. Selection is done through
the bits IT0 and IT1 in the special function register TCON. IT0 (IT1) = 0 selects
level activated interrupt while IT0 (IT1) = 1 selects transition activated interrupt. For
these interrupts the bits that actually generate the interrupts are IE0 and IE1 flag bits.
The CPU samples these external interrupts once each machine cycle, and therefore
an input high or low should hold for at least 12 oscillator periods to ensure sampling.
If the interrupt is set to be transition-activated, the external source has to hold the
interrupt request pin high for at least one machine cycle, and then hold it low for at
least one machine cycle to ensure that the transition is seen. If the interrupt is set as
level activated, the external interrupt request has to remain active until the requested
interrupt is actually generated. There after the interrupt request has to be removed
before the end of the interrupt service routine, or else another interrupt will be
generated.
The vector addresses for INT0 & INT1are respectively 0003H and 0013H. The
diagram below shows the schematic of these external interrupt sources.
0
ITx
INTx
1
IEx
Interrupt
source
The flag that generates the external interrupt is cleared by hardware when the CPU
vectors to the service routine if the interrupt is transition-activated. If the interrupt is
level activated, then the interrupt flag has to be cleared by user software.
Timer Port Interrupts
Timer 0 and Timer 1 interrupts are generated by the timer interrupt flags TF0 and
TF1. These interrupt flags are set when their respective timer / counter registers
(except Timer 0 in mode 3) rollover. When the CPU vectors to a timer interrupt
service routine on-chip hardware clears the interrupt flag that generates the interrupt.
The vector addresses for TF0 and TF1 are respectively 000BH and 001BH.
Serial Port Interrupt
This interrupt is generated by the logical OR of the serial port Receive Interrupt Flag
bit (RF) and the Transmit Interrupt Flag bit (TF). Neither of these flags is cleared by
hardware when the CPU vectors to the service routine. The interrupt service routine
will normally have to determine which of these flags generated the interrupt, and
clears that bit. The vector address for this interrupt is 0023H.
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ECP2036 Microprocessors System and Interfacing
5.2
Chapter 5: Interrupt System
INTERRUPT ENABLE
All the bits that generate interrupts can be set or cleared by software. This we do by writing the appropriate bit
pattern to the Interrupt Enable Register (IE) at address 0A8H, which is one of the special function registers. This
register contains a bit which allows us to enable or disable the interrupt system globally irrespective of the
individual interrupt enable bit setting. The format of the Interrupt Enable Register for the 8051 is as shown
below.
IE
EA
-
-
ES
ET1 EX1 ET0 EX0
Bit Position
Symbol
Bit Address
Description
(ENABLE=1, DISABLE=0)
IE.7
EA
AFH
Global enable/disable.
EA = 1, each individual source is enabled/disabled by
setting/clearing its enable bit.
EA = 0, disable all interrupts.
IE.6
-
AEH
Undefined
IE.5
-
ADH
Not implemented in 8051. ET2 for 8052.
IE.4
ES
ACH
Serial port interrupt enable bit.
IE.3
ET1
ABH
Timer 1 interrupt enable bit.
IE.2
EX1
AAH
External interrupt enable bit.
IE.1
ET0
A9H
Timer 0 interrupt enable bit.
IE.0
EX0
A8H
External interrupt enable bit.
Task #0: Write the assembly codes to enable timer 1 interrupt.
Solution: Two bits must be set to enable any interrupt: the individual enable bit and the global enable bit.
SETB ET1
SETB EA
5.3
; enable Timer 1 interrupt
; set global enable bit
INTERRUPT PRIORITY
In the event of two or more simultaneous interrupts or an interrupt occurring while another interrupt is being
serviced, there are two ways to schedule the interrupts: to use a programmable two-level priority scheme or a
fixed polling sequence.
We can individually program each interrupt source to be at one of the two priority levels by setting or clearing a
bit in the Interrupt Priority (IP) special function register (at address 0B8H). A “1” in the interrupt priority bit
concern sets a high priority and a “0” sets a low priority for that source. The following diagram shows the
structure of the Interrupt Priority register.
IP
-
-
-
PS
PT1 PX1 PT0 PX0
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ECP2036 Microprocessors System and Interfacing
Chapter 5: Interrupt System
Bit Position
Symbol
Bit Address
Description
(HIGHER LEVEL=1, LOWER LEVEL=0)
IP.7
-
-
Undefined
IP.6
-
-
Undefined
IP.5
-
BDH
Not implemented in 8051. PT2 for 8052.
IP.4
PS
BCH
Serial port interrupt priority bit.
IP.3
PT1
BBH
Timer 1 interrupt priority bit.
IP.2
PX1
BAH
External interrupt priority bit.
IP.1
PT0
B9H
Timer 0 interrupt priority bit.
IP.0
PX0
B8H
External interrupt priority bit.
A low priority interrupt can itself be interrupted by a high priority interrupt, but not by another low priority
interrupt. However, no interrupt source, whether of high or low priority, can interrupt a high priority interrupt
source. If two interrupt request of different priority levels are received simultaneously, the CPU services the
request of the higher priority interrupt source. If however the CPU receives interrupt requests of the same level,
it performs an internal polling sequence to determine which request to service. Thus within each priority level
there is a second priority structure which is determined by the polling sequence. The polling sequence is as
follows.
Interrupt Polling Sequence
5.4
Source
Priority Within Level
1
IE0
highest
2
TF0
3
IE1
4
TF1
5
RI + TI
Lowest (8051)
6
TF2 + EXF2
Lowest (8052)
PROCESSING INTERRUPTS
The CPU samples the interrupt flags at S5P2 (state 5 phase 2) of every machine cycle. In the next machine cycle
the CPU polls the samples. If one of the flags was set at S5P2 of the preceding cycle, the CPU will find it in the
polling cycle, and the interrupt system will generate a LCALL (long call) to the appropriate service routine. The
hardware generated LCALL can be blocked by any of the following conditions:
1.
2.
3.
An interrupt of equal or higher priority level is already in progress.
The current machine cycle in which the polling is done is not the final machine cycle in the execution of
the instruction in progress. (This condition is necessary to ensure that the current instruction is completed
before vectoring to the service routine.)
The instruction in progress is RETI or any write to IE or IP registers.
The polling cycle is repeated with each machine cycle. The flag values polled are those present at S5P2 of the
previous machine cycle. Note that when a blocking condition that caused the CPU not to respond to an active
interrupt flag is removed, and if the active interrupt flag now becomes inactive, the CPU will not service the
originally denied interrupt. This means that the CPU does not “remember” an interrupt flag, which was once
active but not serviced. The CPU treats each polling cycle as being new.
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ECP2036 Microprocessors System and Interfacing
Chapter 5: Interrupt System
What follows is a schematic of the interrupt timing diagram.
MC1
S5P2
MC2
MC3
MC4
S6
Interrupt
latched
Interrupts are polled
Long call to interrupt vector address
Interrupt service routine
When an interrupt occurs and is accepted by the CPU, the main program is interrupted. The following actions
occur:
1. The current instruction completes execution
2. The PC is saved on the stack
3. The current interrupt status is saved internally
4. Interrupts are blocked at the level of the interrupt
5. The PC is loaded with the vector address of the ISR (Interrupt Service Routine)
6. The ISR executes
The ISR executes and takes action in response to the interrupt. The ISR finishes with a RETI (return from
interrupt) instruction. This retrieves the old PC value from the stack and restores the old interrupt status.
Execution of the main program continues where it left off.
5.5
INTERRUPT VECTORS
When an interrupt is accepted, the value loaded into the PC is called the interrupt vector. It is the address of
the start of the ISR for the interrupting source. The interrupt vectors are given below:
Interrupt Source
Flag
Vector address
System Reset
RST
0000H
External 0
IE0
0003H
Timer 0
TF0
000BH
External 1
IE1
0013H
Timer 1
TF1
001BH
Serial Port
RI & TI
0023H
Timer 2 (8052)
TF2 or EXF2
002BH
Note that the system reset can be considered as an interrupt source, since it interrupts the main program and
loads the PC value with 0000H.
When “vectoring to an interrupt”, the flag that caused the interrupt is automatically cleared by hardware, except
for RI & TI in serial port interrupts, and TF2 & EXF2 in Timer 2 interrupts (8052). These bits must be cleared
by software in ISR.
In summary, to use the interrupts in the 8051 family it takes the following steps:
1.
2.
3.
Set the EA (enable all) bit in the IE register to “1”.
Set the corresponding individual interrupt enable its in the IE register to “1”.
Begin the interrupt service routine (ISR) at the corresponding vector address of that interrupt.
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ECP2036 Microprocessors System and Interfacing
Chapter 5: Interrupt System
Task #1: (Timer Interrupt)
Write a program using interrupts to simultaneously create a 7 kHz and a 500 Hz square wave on P1.7 and P1.6.
It is assumed that the 8051 is operating at 12 MHz. The two timers (T0 and T1) are used to generate the
necessary interrupts to toggle the two port pins at 7 kHz and 500 Hz to give the square wave output.
Solution:
7kHz square wave → P1.7 needs to toggle every 1/(2×7000) = 71µs < 256µs
→ Timer 0 is set to mode 2 (auto-reload) with its high counter loaded with –71 to give an interrupt every 71 µs.
500Hz square wave → P1.6 needs to toggle every 1/(2×500) = 1ms > 256µs
→ Timer 1 is set to mode 1 with both TH0 and TL0 loaded with – 1000 counts.
The program is shown below.
; A sample program using interrupts to simultaneously create a 7 kHz and
; a 500 Hz square wave on P1.7 and P1.6
ORG
LJMP
ORG
LJMP
ORG
LJMP
ORG
MAIN: MOV
MOV
SETB
SETB
MOV
SJMP
0000H
MAIN
000BH
T0_ISR
001BH
T1_ISR
; bypass interrupt vector table
; Timer 0 vector interrupt address
; Timer 1 vector interrupt address
0030H
TMOD, #12H
TH0, #-71
TR0
TF1
IE, #8AH
$
; main program start address
; Timer 0 mode 2 & timer 1 mode 1
; load timer 0 high counter register
CPL
RETI
P1.7
; toggle port 1 pin 7
CLR
MOV
MOV
SETB
CPL
RETI
TR1
TH1, #0FCH
TL1, #18H
TR1
P1.6
; force timer 1 interrupt
; enable both timer interrupts
; Wait for interrupt
T0_ISR:
T1_ISR:
; Set to 1ms
END
Note that:
1. The timer 1 interrupt service routine stops the timer, re-initializes the counter registers, restarts the timer,
and then toggle the port pin. The re-initialization is necessary because in mode 1 the counter registers are
not reloaded automatically.
2.
The $ in the line SJMP $ is a special assembler symbol that means current location counter value.
3.
The codes:
MOV
MOV
TH1, #0FCH
TL1, #18H
can be replaced by
MOV
MOV
TH1, #HIGH(-1000)
TL1, #LOW(-1000)
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ECP2036 Microprocessors System and Interfacing
Chapter 5: Interrupt System
Task #2: (External Interrupt)
Assume that the INT1 pin is connected to a switch that is normally high. Whenever it goes low, it should turn on
an LED. The LED is connector to P1.3 and is normally off. When it is turned on it should stay on for a fraction
of a second. As long as the switch is pressed low, the LED should stay on. Write a program to perform the
above-mentioned task.
Solution:
; A sample program using external interrupt INT1 to turn on a LED
ORG
LJMP
ORG
SETB
MOV
BACK: DJNZ
CLR
RETI
0000H
MAIN
0013H
P1.3
R3, #255
R3, BACK
P1.3
ORG
MAIN: MOV
SJMP
0030H
; main program start address
IE, #10000100B ; enable external INT1
$
; Wait for interrupt
; bypass interrupt vector table
; INT1 ISR
; turn on LED
; keep LED on for a while (~0.5ms)
; turn off the LED
END
Task #3: (Serial Interrupt)
Write a program using interrupts to read data from P1 and write it to P2 continuously while transmitting a copy
of it to the serial COM port. The incoming data from serial port is sent to P0.
Assume that XTAL = 11.0592MHz. Set the baud rate at 9600.
Solution:
; A sample program using serial interrupt
ORG
LJMP
ORG
LJMP
0000H
MAIN
0023H
SERIAL
; bypass interrupt vector table
; jump to serial ISR
ORG
MAIN: MOV
MOV
MOV
MOV
MOV
SETB
BACK: MOV
MOV
MOV
SJMP
0030H
P1, #0FFH
TMOD, #20H
TH1, #0FDH
SCON, #50H
IE, #10010000B
TR1
A, P1
SBUF, A
P2, A
BACK
; main program start address
; make P1 an input port
; Timer 1, mode 2, auto relaod
; 9600 baud rate
; 8-bit, 1 stop, REN enable
; enable serial interrupt
; start timer 1
; read data from port 1
; give a copy to SBUF
; write to P2
; repeat again
ORG
SERIAL:JB
MOV
MOV
CLR
RETI
TRANS:CLR
RETI
END
0100H
TI, TRANS
A, SBUF
P0, A
RI
; jump if TI is high
; otherwise due to receive
; send serial data to P0
TI
5-6