FET (Field Effect Transistors)
FET
JFET
Junction FET
MOSFET Metal-Oxide S/C FET
CMOS
Complementary MOSFET
VMOS
Vertical MOSFET
270
Comparison of FET and BJT
1. Majority carriers are current carriers in FET
•
•
Electrons in n-channel FET
Holes in p-channel FET
Unipolar device
2. In BJT both majority and minority carriers are current carriers. BJT
is a bipolar device.
3. BJT is current controlled device.
FET is voltage controlled device.
4. FET has high input impedance than BJT.
5. MOS occupy small silicon area on the IC chip.
6. MOS manufacturing process is relatively simple.
7. FET has less noisy than BJT.
271
Junction FET (JFET)
JFET
n-channel
p-channel
D (Drain)
G (Gate)
p+
n
p+
S (Source)
D
G
p
n+
n+
S
272
The maximum current is defined as IDSS and occurs when VGS = 0 and
VDD ≥ |VP|.
D
ID=IDSS
+
G
VDD ≥ |VP|
S
For the gate-to-source voltages VGS less than (more negative than) the
pinch-off level, the drain current is zero. (ID=0)
D
G
+
VGG
VGS = -VGG
ID=0
+
VDD ≥ |VP|
S
|VGG| ≥ |VP|
273
For all levels of VGS between 0V and the pinch off level, the current ID will
range between IDSS and 0A.
0 ≤ ID ≤ IDSS
D
G
+
VGG
+
VDD ≥ |VP|
S
|VP| ≥ |VGG| ≥ 0
274
Transfer Characteristics
0 ≤ ID ≤ IDSS
D
G
VDD ≥ |VP|
S
|VP| ≥ |VGG| ≥ 0
ID
IDSS
Linear
region
+
VGG
+
VDS = VGS − VP
VGS=0
Saturation
region
VGS= -1V
VGS=VP
VGS VP
cut-off
VDS
n - channel
275
ID
n – channel JFET
IG  0
IDSS
Linear
region
FET Biasing
for VGS  0 (VP  0)
VDS = VGS − VP
VGS=0
Saturation
region
VGS= -1V
Cutoff : ID(off) = 0 for VGS ≤ VP
VGS=VP
VGS VP
VDS
cut-off
n - channel
Linear :
I DSS
I D  lin   2  2 VGS –VP VDS –VDS 2 
VP
for VGS  V P  V DS  0
Saturation :
 VGS 
I D  sat  =I DSS  1 

VP 

or
2
for V DS  VGS V P  0
λ : channel length modulation
2
 VGS 
I D  sat  =I DSS  1 
  1+  VDS 
VP 

for V DS  VGS  V P  0
276
IG  0
ISD
for VSG  0 (VP  0)
IDSS
Linear
region
p – channel JFET
VSD = VSG + VP
VSG=0
Saturation
region
VSG= -1V
Cutoff : ISD(off) = 0 for VSG ≤ -VP
VSG=VP
VSG VP
p - channel
Linear :
I SD  lin  
VSD
cut-off
I DSS
2


2
V
+V
V
–V


SG
P
SD
SD 
2 
VP
for V SG  V P  V SD  0
Saturation :
 VSG 
I SD  sat  =I DSS  1+

VP 

or
2
for V SD  V SG  VP  0
2
 VSG 
I SD  sat  =I DSS  1+
  1+  VSD 
VP 

for V SD  V SG  V P  0
277
Metal-Oxide S/C FET (MOSFET)
MOSFET
Depletion
n-channel
p-channel
Enhancement
n-channel
p-channel
278
Depletion Type p-channel MOS
Source
Gate
Si02
Drain
Si02
p
p+
Diffusion
p-
Metal
contact
Si02
p+
channel
n- substrate
Substrate (SS)
D
SS
G
S
D
D
Substrate internally connected
G
G
S
S
to the source.
279
Transfer Characteristics
ID
ID
VGS= -1V
Depletion mode
Enhancement
mode
IDSS
IDSS
VGS=0
VGS=1
VGS=VT
VT
VDS
VGS
p - channel
Source
Si02
Gate
Drain
Si02
p
p+
Diffusion
p-
Metal
contact
Si02
p+
channel
n- substrate
Substrate (SS)
280
Depletion Type n-channel MOS
Source
Gate
Si02
Drain
Si02
p
n+
Diffusion
n-
Metal
contact
Si02
n+
channel
p- substrate
Substrate (SS)
D
G
SS
S
D
D
Substrate internally connected
G
G
S
S
to the source.
281
Transfer Characteristics
ID
ID
VGS=1
Depletion mode
IDSS
IDSS
VGS=0
Enhancement
mode
VGS= -1V
VGS=VP
VDS
VGS
VT
n - channel
Source
Si02
Gate
Drain
Si02
p
n+
Diffusion
n-
Metal
contact
Si02
n+
channel
p- substrate
Substrate (SS)
282
Enhancement Type n-channel MOS
Source
Gate
Si02
Drain
Si02
p
n+
Diffusion
Metal
contact
Si02
n+
channel
p- substrate
substrate
D
D
SS
G
S
G
D
Substrate internally
connected to the Source
G
S
S
283
Transfer Characteristics
ID
ID(max)
ID
VGS
VGS=VT
VT
VDS
VGS
n - channel
Source
Si02
Gate
Drain
Si02
p
n+
Diffusion
channel
Metal
contact
Si02
n+
p- substrate
substrate
284
Enhancement Type p-channel MOS
Source
Gate
Si02
Drain
Si02
p
p+
Diffusion
Metal
contact
Si02
p+
channel
n- substrate
substrate
D
D
SS
G
S
D
Substrate internally
connected to the Source
G
G
S
S
285
Transfer Characteristics
ID
ID(max)
ID
|VGS|
VGS=VT
VGS
VT
VSD
p - channel
Source
Si02
Gate
Drain
Si02
p
p+
Diffusion
channel
Metal
contact
Si02
p+
n- substrate
substrate
286
Device Transconductance Parameter, kn
 nC OX
kn 
2
W

 L
 k'W 
  
 2 L
μn
: Electron mobility
Cox
: Gate capacitance per unit area ≡
εox
: Permittivity of SiO2
tox
: Thickness of gate oxide
ε0x
t 0x
287
NMOS
iD
For all regions, I G  0
Cutoff : VGS ≤ VT , ID(off) = 0
Linear :
VGS ≥ VT and VDS ≤ VGS – VT
iD
Saturation :
VGS ≥ VT and VDS ≥ VGS – VT
i D  sat  =kn VGS  VT 
2
Linear
region
i D  lin   kn  2 VGS –VT VDS –VDS 2 
VT
VGS
VDS = VGS − VT
Saturation
region
or
i D  sat  =kn VGS  VT   1+ VDS 
2
λ : Channel length modulation parameter
cut-off
VDS
288
PMOS
Cutoff : VSG ≤ -VT , ID(off) = 0
Linear :
VSG > -VT and VSD ≤ VSG + VT
i D  lin   k p  2 VSG +VT VSD –VSD 2 
Saturation :
VSG > -VT and VSD ≥ VSG + VT
i D  sat  =k p VSG +VT 
2
or i D (sat)=k p VSG +VT   1+ VSD 
2
Threshold-voltage values for the four types of NMOS and PMOS transistors.
NMOS
PMOS
Enhancement-Mode
VTN>0
VTP<0
Depletion-Mode
VTN≤0
VTP≥0
289
Example: Determine ID and VD and draw the dc load line.
18V
Applying KVL to input
2k
VGG  RG I G  VGS  0
I DSS  8mA
VP   4V
 0
2M

VGS 
2V 

I D = I DSS  1 
  8mA  1 
  2mA
VP 
4V 


2
VDD  RD I D  VDS  0 dc load line equation
ID(mA)
9
8
VD  VDD  RD I D  18  2k   2mA  14V
when I D  0
Q
VGS -4
VGS  2V
Applying KVL to output
+
2V
2

-2
2
Q
14 18 VDS(V)
 VDS  18V
when VDS  0  I D  9 mA
292
DC Analysis
Self Bias Configuration
VDD
RD
RG
VGS  RG I G  RS I D  0
C2
C1
Vin
Applying KVL to input
VO
RS

VGS   RS I D
Applying KVL to output
VDD   RD  RS  I D  VDS  0
ID
IDSS
Q
VGS VP
VGSQ
VDD
IDQ
 RD  RS 
Q
VDSQ
293
VDS
Example: Determine VGSQ,
Applying KVL to input
IDQ and VDSQ and draw the
VGS  RG I G  RS I D  0  VGS  1.6k   I D
dc load line.
12V
2.2k
I DSS  6mA
VP  6V
 0
IG
1M
1.6k

VGS 
I D = I DSS  1 

V
P 

2
2

 VGS VGS
-VGS
 VGS 

 6mA  1+
= 6mA  1+


36
3
6
1.6k




 12.975V
2
VGS  15.75VGS  36  0  VGS  
  2.775V
VGS  VP  VGS  2.775V
2
VGS 2.775V
 1.73mA

ID =
1.6k
1.6k
294
Applying KVL to output
VDD   RD  RS  I D  VDS  0
12  3.8k  I D  VDS  0
VDSQ  12  3.8k   1.73mA  5.426V
when I D  0
 VDS  12V
when VDS  0  I D  3.16mA
ID(mA)
6
3.16
Q
VGS -6
-2.775
1.73
Q
5.426
12 VDS(V)
295
VDD
R1
VDD
RD
RG  R1 R2
RD
VG 
RG
R2
RS
VG
+
VDD
R2
R1  R2
RS I D  VG
RS
ID
Applying KVL to input
IDSS
VG  RG I G  VGS  RS I D  0
VGS  VG  RS I D
Applying KVL to output
Q
VGS VP
VDD   RD  RS  I D  VDS  0
VGSQ
VDD
 RD  RS 
Q
IDQ
VG
VDSQ
VDS
296
Example: The transistor parameters: VP = 2V, IDSS = 4mA.
Determine IDQ, VSGQ, and VSDQ.
5V
1mA
I DQ  1mA
I DQ
+
1V
5V
 VSG 
= I DSS  1+

V
P 

2
 V 
1mA  4 mA  1+ SG 
2 

2
VSG  1V
VS  VSG  1V  0V
VS  VSD  5V  VSD  5V
297
Example:
Applying KVL to input
Find VGS, ID, and VDS.
10V
20k
kn  100 A / V 2
VTN  3V
 0
VGS
VGS  RS I D  0  I D 
20k
2
I D  k n VGS  VT 
VGS
2
2
 100  A V VGS  3V 
20k
VGS
2
 VGS
 6VGS  9
2
2
VGS
 6.5VGS  9  0
6.5  6.52  4  9  4.5V
VGS 

2
 2V
VGSQ  2V
298
2V
ID 
 100  A
20k
VDS  10  RS I D  10  20k  100  A  8V
VDS  VGS  VT for saturation region
8  2  3  1
ID
0.9
0.5
Q
VGS -3
Q
-2
8
10
VDS
299
Example:
Find VGS, ID, VD and VDS.
1 M  I G  VGS
14V
1.2k
1M
0.43k
k n  375  A / V
VTN  4V
 0
Applying KVL to input
2
VGS
 RS I D  0  I D 
0.43 k
VGS
2
 375  A V 2 VGS  4 
0.43k
VGS
2
 VGS
 8VGS  16
0.16
2
VGS
 14.2VGS  16  0
14.2  14.2 2  4  16  12.965V
VGS 

2
 1.235V
VGSQ  1.235V
300
1.235V
ID 
 2.87 mA
0.43k
VD  14  RD I D  14  1.2k  2.87 mA  10.556V
VDSQ  14   RS  RD  I D  14  1.63k  2.87 mA  9.32V
ID(mA)
8.59
6
Q
VGS -4
-1.235
2.87
Q
9.32
14
VDS
301
Example:
Applying KVL to input
Find VGS, ID, and VDS.
22V
1
1.2k
1M
0.51k
k n  550  A / V 2
VT  4V
 0
22  1.2k  I D  1 M  I G  VGS  0.51  I D  0
22  VGS
ID 
1.71k
22  VGS
2
2
 550  A / V VGS  4 
1.71k
22  VGS
2
2
 VGS  4   VGS
 8VGS  16
0.95
VG2S  6.95VGS  7.16  0
6.95  6.952  4  7.16  0.91V
VGS 

2
 7.86V
302
VGSQ  7.86V
FET Current Sources
JFET Current Source
Current sources are also fundamental elements in JFET ICs. The
simplest method of forming a current source is to connect the gate and
source terminals of an JFET, as shown in Figure.
+
VDS

IO
RO
34
+
VDS

IO
RO
The device will remain biased in the saturation region as long as
VDS  VDS ( sat )  VGS - VP  VP
In the saturation region, the current is
 VGS 
I D  I DSS  1 
VP 

I O  I DSS
2
 1  VDS   I DSS  1  VDS 
The output resistance looking into the drain is,
RO 
VDS
1
 rd 
I D
 I DSS
35
Example: Calculate the current through 2k load in the circuit
VDD
VDD
2k
2k
I DSS  1mA
VP  -1.5V
  0.01V 1
IO
R
VDS  VP  1.5V
I O  I DSS  1mA
RO  rd 
1
1

 100k 
1
 I DSS 0.01V  1mA
I D  I DSS  1  VDS   1mA  1  0.01V 1  1.5V   1.015mA
36
Basic Two Transistor MOSFET Current Source
Figure shows a basic two-transistor
NMOS current source (mirror). The
V
drain and gate terminals of the NMOS
+
RO
IREF
ID2=IO
transistor M1 are connected, which
means that M1 always biased in the
saturation region. Assuming λ=0, we
M1
+
VGS

V-
M2
can write the reference current as
I D 1  I REF  k n1 VGS  VTN 1 
2
Solving for VGS yields
VGS 
I REF
 VT 1
k n1
37
V+
For the drain current to be independent
of the drain-to-source voltage (λ=0),
Transistor
always
biased
in
RO
IREF
the
saturation region. The load current is
M1
+
VGS
M2

then
I O  k n 2 VGS  VT 2 
ID2=IO
V-
2
Substituting VGS into the load current equation, we have

I O  kn 2 



I REF
 VT 1  VT 2 

k n1

2
38
V+
If M1 and M2 are identical transistors,
then VT1 = VT2 and kn1 = kn2
RO
IREF
ID2=IO
I O  I REF
The relationship between the load current
and the reference current changes if the
width-to-length, or aspect ratios, of the two
M1
+
VGS
M2

V-
transistors change.
If the transistor are matched except for the aspect ratios, we find
W / L  2
IO 
I REF
W / L 1
The ratio between the load and reference currents is directly proportional
to the aspect ratios and gives designers versatility in their circuit designs.
39
Output Resistance
V+
The stability of the load current can
ID2=IO
RO
IREF
be described in terms of the output
resistance. The output resistance, RO
M1
VDS
1
RO 
 rd 
I O
 IO
+
VGS
M2

V-
MOSFET current sources require a large output resistance for
excellent stability.
40