K. E. Society’s
Rajarambapu Institute of Technology (RIT), Rajaramnagar (Islampur)
(Estd.1983)
(An Autonomous Institute, affiliated to Shivaji University, Kolhapur)
Accredited with ‘A’ Grade by NAAC
Funded by TEQIP & World Bank
Ranked 75th across all over India and 7th all over Maharashtra by NIRF (2016)
Virtual Internship Program
(Collaboration with Global Engineering Dean’s Council India Chapter)
on
VLSI FRONT END DESIGN AND VERIFICATION
(22th June to 22th July 2020)
Eligibility Criteria:
All undergraduate/graduate students of Electronics and
Telecommunication, Electrical and Computer Engineering, who want to make their career in
VLSI front end design and verification.
Outcomes of Program:
After completing this internship program participants will be able to:
1. Design industry grade solutions to real time problems by applying knowledge of
digital design
2. Develop front end solution models using Hardware Descriptive Language (HDL)
3. Create verification environment using System Verilog testbench
4. Analyze code coverage and functional coverage of designed model by high end
verification tool like QUESTAR.
5. Implement digital systems using Xilinx VIVADO and perform hardware validation on
FPGA to meet design specification.
6. Prepare for interview related to VLSI Design and Verification openings.
Specific Note: Requires Xilinx Vivado and Questasim tool to access all features. (License
version is preferred)
Max. Number of Participants: Min 22 Nos.
Duration of the Internship Program: 5 Weeks (150 Hrs).
Date: 22th June to 22th July 2020
Registration fees for students of RIT, Rajaramnagar and diploma students: Rs. 2000 /Registration fees for other students: Rs. 3000 /-
Registration link: https://forms.gle/m9iCDZJQjw4sxDcH8
Certification: Joint certificate with GEDC and grade will be issued after successful completion
of course.
Prerequisites: The basic knowledge of Digital Design, Digital Integrated Circuits, and
programming language like C or C++ is beneficial. However, the availability of synthesis and
verification tools like Xilinx VIVADO, Questasim and FPGA boards like Zynq 7000 SoC,
Nexys/Basys provides more hands-on experience.
Software/Hardware Required:
Simulation and Synthesis Tools: Multisim/Proteus, Xilinx VIVADO
Front End Design and Verification Tools: Mentor Graphics Tools Frontend HEP2- QuestaSim®
FPGA Development Boards : Zedboard(Zynq 7000), Nexys 4 DDR, Basys3, PYNQ
Introduction / Relevance / Need: The proposed course deals with the current industry
requirements in VLSI front design namely digital system design, RTL modelling, Software
verification and hardware testing of digital circuits/systems. This benefits for the students to get
exposure to industry opportunities and acquainted with industrial work culture similarly,
researchers to contribute in solving social problems with technology to benefit the larger
community and product developers to reach quick time to market. This course also provides
experiential learning with industrial grade advanced tools and hardware that leads students to
carry out the project and make their career in VLSI industry.
Duration
Course Content
VLSI FRONT END DESIGN AND VERIFICATION
Module Name
Week 1
D1
Digital Primer
D2
Advanced
Digital System
Design
V1
VLSI Primer
Week 2
V2
HDL
Programming
Module Content
 Introduction to
Combinational Circuits.
 Introduction to
Sequential Circuits.
 Introduction to PLDs
 Synchronous Finite
State Machine Design
 Data-path elements Arithmetic Structures
 Design Capture and
Simulation
 Design Examples
 Introduction to VLSI
based Embedded
systems
 Introduction to Logic
Families
 VLSI Design Flow
(Frontend and Backend)
Total
 Hardware Modeling
Overview,
 HDL language concepts
 Modules and Ports
 Dataflow Modeling
 Introduction to Test
benches
 Operators
 Procedural Statements
 Controlled Operation
Statements
 Coding for Finite State
Machines
 Coding For Synthesis
 Tasks and Functions
 Advanced HDL Test
benches
Theory
Hrs
Lab Work
/ Activity
Hrs
6 hours
--
Mode
of
Teaching
Online
Online
10
hours
6 hours
Online
4 hours
4 hours
20
10
Online
14
hours
15 hours
P1
Synopsis
Preparation
 Finalization of mini
projects and synopsis
preparation
Total
 FPGA Architecture Basic Components of
FPGA (LUT,CLB,
Switch Matrix, IOB),
FPGA Architecture of
different families: 7series and UltraScale
devices.
Week 3
V3

FPGA Design

Week 4




V4
System Verilog



FPGA Design Flow –
Xilinx Vivado tool Flow,
Reading Reports,
Implementing IP cores,
Debugging Using Vivado
Analyzer.
Optimal FPGA Design HDL Coding Techniques
for FPGA, FPGA Design
Techniques, Synthesis
Techniques,
Implementation Options.
Total
Introduction to
Verification and
Verification Plan
Verification Tools
Stimulus and Response
SystemVerilog Basics –
Introduction to
SystemVerilog,
Enhancement made in
SystemVerilog over
Verilog,
Interface and Modports
Introduction to Bus
Functional Models
Verification environment
and its components
SystemVerilog for
Online
1 hour
-
15
15
Online
15
hours
15 hours
15
15
Online
12
hours
15 hours
Week 5
Verification SystemVerilog Event
Ordering, Clocking block
and Program block,
OOP's Concept of
SystemVerilog Parameterized classes,
Virtual interface,
Constrained
Randomization
techniques, Functional
Coverage,
SystemVerilog
Assertions
a) Introduction to UVM
b) UVM Classes
c) UVM Factory
d) Sequence Item,
Sequencer, Virtual
V5
Sequences
UVM
e) Transaction Level
Modeling
f) UVM Reporting Methods
g) Development of
Reusable Verification
Environment
Total
 Introduction to
MATLAB Simulink
V6
HDL coder
HIL
 FPGA in loop (FIL),
Hardware in loop (HIL)
debugging
 Miniproject
(Few Probable Projects
are listed )
P2
 UART Implementation.
 Basic Image Processing
Miniproject
Algorithm
Implementation
Implementation using
MATLAB and FPGA.
and Evaluation
 Memory Design.
 Design & Verification of
Microprocessor/Microcontroller.
Evaluation:
Online
3
hours
-
15
15
Online
3 hours
3 hours
Online
2 hours 22 hours
1. MOODLE platform will be used for
discussion forum, sharing resources
etc.
2. Mini project will be evaluated based
on rubrics
3. The evaluation of mini project is
divided into four phases
Phase 1: Synopsis writing –will be
evaluated for 20 marks
Phase 2: Mid review- will be evaluated
for 20 marks
Phase 3: Report writing and
submission- will be evaluated for 20
marks
Phase 4: Final project submission and
presentation- will be evaluated for 40
marks
4. Final score will be awarded based on
weightages as 10%, 20% and 70% to
attendance, continuous assessment and
miniproject respectively. The overall
percentage of passing is 40%.
Total
Grand Total (150 Hrs)
05
25
Laboratory Details
Module name
D2
Week 1
Advanced Digital
System Design
Laboratory Details
1. Simulation of
combinational and
sequential circuits using
proteus/ multisim
a. Adders/ Subtractor
b. Multiplexers
Duration
6 hours
c. Encoder/Decoder
d. Counters/ Shift Registers
(LFSR)
e. Finite State Machines
V1
VLSI Primer
a. Demonstration of Xilinx
VIVADO Tool
4 hours
b. Simple examples to get
familiar with tool
V2
Week 2
HDL programming
V3
Week 3
FPGA Design
V5
Week 4
System Verilog
Modelling, simulation and
performance parameter
analysis of following in
different style of description
a. Adders/ Subtractor
b. Multiplexers
c. Encoder/Decoder
d. Counters
e. Finite state machines
f. Modelling of processor
Synthesis and
Implementation of .
a. Multiplexers
b. Counters
c. Interfacing of Seven
segment display
d. Development of
embedded systems on
FPGA using hard and
Soft IP cores
e. Programming of Zynq
SoC
f. Use of RAM Memory
block
a. Demonstration of
Questasim Tool
b. Verification of
Combinational circuits
c. Verification of
Sequential circuits
d. Verification of digital
modules using OOP
test bench
15 hours
15 hours
15 hours
V7
HIL
Week 5
P2
Mini project
Implementation and
Evaluation
e. Modelling and
Verification of LFSR
f. Verification of Single
port and Dual port
RAM Memories
g. Code coverage and
Functional coverage
analysis
a. Demonstration of
FIL/HIL in MATLAB
Simulink and FPGA by
resource persons
b. DSP Example
c. Mini project
implementation by
students
d. Demonstration of VLSI
mini projects by
students
e. Evaluation by resource
persons
3 hours
22 hours
Resource Faculties
Sr. No.
Name
1.
Prof. Sachin M
Magadum
2.
Prof. Mrs. V S Patil
3.
Prof. R T Patil
4.
Mr. Sohel Langardar
5.
Mr. Sandeep Alatagi
Area of Expertise
VLSI Design and Verification, Digital sensor design,
Embedded Systems
https://www.ritindia.edu/index.php/departments/electronicstele-communication-engg/faculty-new-etc/item/380-mr-sm-magadum
Ph. D in VLSI
https://www.ritindia.edu/index.php/departments/electronicstele-communication-engg/faculty-new-etc/item/374-mrs-vs-patil
Expertise in Electronics System Design, Microcontrollers
https://www.ritindia.edu/index.php/departments/electronicstele-communication-engg/faculty-new-etc/item/369-mr-r-tpatil
Verification Engineer , Micron Technology, Hyderabad
CoreEl Technologies Pvt. Ltd. Pune
For more details faculties please visit:
https://www.ritindia.edu/ETCE/index.php/faculty-mba/teaching-faculty
Course Incharge:
Dr. M. S. Patil
Email id: mahadev.patil@ritindia.edu
E-PAYMENT DETAILS – HDFC Bank
1) Name of Account Holder
: KES RAJARAMBAPU INSTITUTE OF TECH UG
2) Bank Account Number
: 50100190482387
3) Bank Name
: HDFC Bank
4) Bank Branch Name
: Islampur Branch
5) Account Type
: Saving Account
6) IFSC Code
: HDFC0002455
7) Swift Code
: HDFCINBB
7) MICR Code
: 415211001
8) Bank Branch Address
:HDFC BANK ,Islampur Branch,
Vashikar Bandhu Building, Gandhi Chowk,
Near Main Post office, Islampur Dist: Sangli 415409,
Maharashtra, India