PH506_LABREPORT_3_21510110_21-22
Experiment: Op-Amp, FET and MOSFET
Student Name (Roll no.): Sushil Kumar (21510110)
Date of Experiment: 25/02/2022
Date of report submission: 18/02/2022
Objective: (I) To verify addition and subtraction using inverting and non-inverting OpAmp.
(II) To study the drain characteristics of FET and MOSFET.
Theory:
Op-Amp: An operational amplifier (often op-amp or op-amp) is a DC-coupled
high-gain electronic voltage Fig-1: Symbolic diagram of an Op-Amp amplifier with a
differential input and, usually, a single-ended output. It has many applications. We can use an
op-amp as- Amplifier, Adder, Subtractor (or Differentiator), Differential, Integrator, etc.
It is available in an Integrated circuit (IC) form – IC 741 and IC 714. IC 741 is an 8-pin IC
where 4 are input pins, and 1 pin (pin 6) is used for Output. Pin7 and 4 provide the bias
voltage of +VCC and -VCC to the IC. Input voltage is given to pin 2 (Inverting) and 3 (noninverting). The input pin on which feedback is applied decides if the amplifier is Inverting
or Non-inverting.
Figure 1- IC 741 OP-AMP
The basic two mathematical operations, Addition, and Subtraction using an Op-amp is
described below: Adder circuit via Op-Amp: An adder is an electronic circuit that produces an output equal
to the sum of the applied inputs. Shown below is the op-amp-based adder circuit.
PH506_LABREPORT_3_21510110_21-22
Figure 2- Adder circuit using IC 741
Thus, the Output is the amplified sum of the input voltages V1 and V2. The negative sign
appears due to inverting amplifier.
If ‘Rf’ and ‘R’ are of the same magnitude, Output becomes Vo = -(V1 + V2).
Subtractor circuit via Op-Amp: A subtractor is an electronic circuit that gives an output
equal to the difference of the applied inputs. Shown below is the circuit used for Op-Amp
based subtractor.
Figure 3- Subtractor circuit using IC 741
Therefore, the Output is the amplified difference of the input applied at the inverting
and non-inverting amplifier. This amplifier is thus also called a Differential Amplifier.
Now, if Rf = R, then,
Vo = (V2 - V1)
Field Effect Transistor (FET)
A field-effect transistor (FET) is a voltage-controlled current device. Its name field-effect
comes from the fact that the current flowing through the device is controlled by the electric
PH506_LABREPORT_3_21510110_21-22
field setup due to the application of external potential. They are of two types: Junction FET
(JFET) and Metal-oxide semiconductor FET (MOSFET). Both can be fabricated as discrete
and integrated circuits. MOSFETs can be made extremely small compared to Bipolar
junction transistors (BJTs), and digital memory circuits can easily be implemented with
them; that's why they are preferred. It can be either have an N-type channel or a P-type
channel.
A BJT uses both types of charge carriers (electrons and holes) for current conduction; on
the other hand, FET uses majority charge carriers in the channel, whatever it may be. Since
charge carriers have only one polarity, these transistors are called Unipolar.
Field Effect Transistor: Structure and Working
It is an n-type Silicon (Si) bar with heavily doped p-type regions deposited on its sides. This
p-region forms the gate, which is connected. The bar acts as a resistor between its two
terminals, Source and Drain. Gate controls the current flow from source to drain—the
region between the two gates where the majority carriers move from source to drain forms
the channel.
Figure 4- Typical structure of FET
Formation of channel: Drain is made positive concerning the source, due to which charge
carriers (majority: electrons in case of n-type) flow from source to drain, forming Drain
current, ID. The charges thus pass-through two p-type gates whose voltage can be
controlled.
A reverse bias is applied to the gates, which increases the width of the depletion layer where
no mobile carriers can be found. The path of the electrons thus becomes constricted. The
current ID reduces. It is noted that the width of the depletion layer does not increase
uniformly. As the current flows through the bar, a potential drop occurs along its length. The
reverse bias is not identical across the length. The reverse bias and thus the width of the
depletion layer is more on the gate and drain side than that on the source end of the bar.
Channel is narrower on the drain side. Increasing the reverse bias of the gate results in
channel blocking, pinching off the current flow at some pinch-off voltage VP. The width only
reduces to a particular constant minimum value. Thus, we obtain a constant current through
this small width.
PH506_LABREPORT_3_21510110_21-22
Figure 5- Working of FET: Under reverse bias of VGS
FET characteristics: We have two types of characteristics – Drain Characteristics
and Transfer Characteristics.
Drain Characteristics: The variation of drain current ID with drain-to-source voltage
VDS for a constant gate-to-source VGS.
Transfer Characteristics: A transfer characteristic is one quantity in Output plotted against an
input quantity. It is the variation of drain current with ground-to-source VGS for a constant
drain-to-source VDS.
Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET): Structure and
Working
A MOSFET differs from FET only in insulation between its gate terminal and the channel
region. It is, therefore, also called Insulated-Gate FET (IGFET). The gate current is
extremely small (approx. 10-15 A). They are of two types: Depletion type (DE MOSFET)
and Enhancement type (EN MOSFET). They differ in the way of conductivity of channel
changes with VGS.
A high resistance p-type silicon block forms the body (for physical support). Two heavily
doped n-type wells are created on the surface. An insulating material – SiO2, is deposited
along the surface. Two metal contacts penetrate it to form Source and Drain terminals
connecting two wells.
Formation of channel: The body is connected to the source. Gate is a positive concerning
source; it repels the hole below it, leaving immobile carriers. Also, it attracts electrons from
the n-type wells, which creates an N-region near the body's surface. This region acts as a
channel for the current flow from drain to source when positive voltage VDS is applied. The
voltage applied to the gate should attain a minimum value to accumulate electrons necessary
for conduction. This is called Threshold voltage VT. It is typically 1 to 3 volts.
After channel formation, application of small voltage VDS causes electrons and thus drain
current (ID)to flow from source to drain.
PH506_LABREPORT_3_21510110_21-22
Figure 6- N-type channel MOSFET
MOSFET Characteristics: Same as FET, it has a drain and transfer characteristics.
Drain Characteristics: The variation of drain current ID with drain-to-source voltage
VDS for a constant gate-to-source VGS.
Transfer Characteristics: It is the variation of drain current with ground-to-source VGS for a
constant drain-to-source VDS.
Apparatus and Materials:
For Op-Amp
1. OMEGA TYPE OAD-14 OP-AMP KIT: It has an IC-741 embedded in it. A total of
100 experiments can be performed on this board including basic operational amplifier
circuit, source followers, function generator, filters, limiters, comparators,
instrumentation amplifier, and many more.
2. Connecting Wires
3. Digital Multi-meter.
For FET and MOSFET
1. Nevis 6512A understanding characteristics of MOSFET, FET & UJT is an experimental
board that has common source n-type JFET followed by a three-section R-C phase shift
network, Enhancement-mode channel MOSFET, and a UJT in it. It can be used to plot
transistor characteristics, and calculate its parameter like resistance, transconductance,
etc. It has inbuilt power supplies of various potentials. It is a complete circuit on its
own.
2. Connecting Wires
Procedure:
For Op-Amp
1. Use the figures shown above for making connections for the Adder circuit as well as the
Subtractor circuit. Use power supply of ± 15 V.
PH506_LABREPORT_3_21510110_21-22
2. Set voltages V1 and V2 as per choice and measure them using a multi-meter. Note down
the readings for both.
3. Now, using a multi-meter measure the output voltage using pin 6 and ground terminal.
Also, write the theoretical value of sum and difference.
For FET drain characteristics
1. Make connections using the connecting cables as per the manual. Rotate the
potentiometer screws entire to the left. Switch on the power supply.
2. Using Potentiometer screw P1 set the value of Gate voltage VGS to some constant.
3. Remove the voltmeter from the gate terminal and fix it onto the drain terminal to
measure Drain voltage VDS.
4. Vary the drain voltage using potentiometer screw P2 and note the corresponding
drain current ID.
5. Now, do the same keeping different values of gate voltage VGS
constant. 6. Plot a graph between VDS and ID for different VGS.
For MOSFET drain characteristics
1. Make connections for MOSFET using the manual. Rotate the potentiometer screws to
the left entirely. Switch on the power supply.
2. Using potentiometer P1 set a constant value of gate voltage VGS. Then remove the
voltmeter connection from the gate terminal of the MOSFET and connect it to its drain
terminal. Voltmeter now measures drain voltage VDS.
3. Vary potentiometer P2 to increase the drain voltage VDS and note the readings for the
drain current ID.
4. Repeat the same for other values of gate voltage VGS.
5. Plot a graph between VDS and ID for different VGS.
Experimental Data:
R1=R2 = 1Ω
And V= 15.6v
Table 1: ADDER using Inverting Op-Amp.
S.NO. V1 (volts)
V2 (volts)
1
2
3
4
5
6
1.00
1.25
1.50
1.75
1.75
1.75
0.25
0.50
0.75
1.00
1.25
1.50
Theoretical
value VT
(V1 + V2)
1.25
1.75
2.25
2.75
3.00
3.25
Experimental
value VE
(V1 + V2)
1.27
1.77
2.28
2.78
3.03
3.28
Error =
|VT − VE|
0.02
0.02
0.03
0.03
0.03
0.03
PH506_LABREPORT_3_21510110_21-22
7
8
9
2.00
1.30
2.05
1.75
1.75
1.75
3.75
3.05
3.80
3.78
3.08
3.83
0.03
0.03
0.03
Experimental
value VE
(V2 - V1)
1.82
1.68
1.51
1.42
1.33
1.27
1.20
1.13
0.97
Error =
|VT − VE|
Table 2: SUBTRACTOR using Non-Inverting Op-Amp.
S.NO. V1 (volts)
V2 (volts)
1
2
3
4
5
6
7
8
9
2.10
2.00
1.80
1.70
1.60
1.53
1.45
1.37
1.19
0.25
0.25
0.25
0.25
0.25
0.25
0.25
0.25
0.25
Theoretical
value VT
(V2 - V1)
1.85
1.75
1.55
1.45
1.35
1.28
1.20
1.12
0.94
0.03
0.07
0.04
0.03
0.02
0.01
0.00
0.01
0.03
Table 3: MOSFET DRAIN CHARACTERISTIC CURVE
S.NO.
1
2
3
4
5
6
7
8
9
10
11
12
VDS
(volt)
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
VGS = 5 V
IDS (mA)
0.00
1.50
3.10
4.60
6.20
7.80
9.30
10.90
12.10
13.40
14.40
14.50
VGS = 6 V
IDS (mA)
0.00
1.40
2.90
4.50
6.00
7.50
9.20
10.60
12.80
13.60
14.10
16.20
VGS = 7 V
IDS (mA)
0.00
1.40
2.90
4.40
5.90
7.10
8.90
10.50
12.20
13.60
15.20
16.60
VGS = 8 V
IDS (mA)
0.00
1.50
3.00
4.50.
6.00
7.50
9.00
10.50
12.10
13.70
15.30
16.70
PH506_LABREPORT_3_21510110_21-22
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
3.00
3.25
3.50
3.75
4.00
4.25
4.50
4.75
5.00
5.25
5.50
5.75
6.00
6.25
6.50
7.00
8.00
9.00
10.00
11.00
12.00
13.00
14.00
15.00
16.00
17.00
18.00
19.00
20.00
21.00
22.00
23.00
24.00
25.00
26.00
27.00
28.00
14.50
14.50
14.50
14.50
14.50
-----------------------------------------------------------------------------------------------------------------------------------------------------------------
18.20
19.60
20.20
21.20
22.70
24.20
25.40
25.60
25.70
25.70
25.70
25.70
25.70
25.80
25.80
25.80
25.80
-----------------------------------------------------------------------------------------------------
18.10
21.20
22.80
24.30
26.00
27.40
28.90
30.40
32.00
33.00
34.80
35.50
36.30
36.35
36.40
36.40
36.40
-----------------------------------------------------------------------------------------------------
18.20
19.70
21.40
22.80
24.30
25.80
27.40
30.40
32.90
35.10
37.50
39.90
42.40
44.40
46.50
48.70
50.40
50.50
50.60
50.70
50.80
51.00
51.20
51.40
51.40
51.40
51.40
51.40
51.40
51.60
51.80
51.90
51.90
51.90
51.90
51.90
51.90
PH506_LABREPORT_3_21510110_21-22
Table 4: FET DRAIN CHARACTERISTIC CURVE
S.
No.
Output
voltage
VDS
(volts)
Output Drain current ID (mA) at a constant value
of input voltage
VGS = 0 V
VGS = -1 V
VGS = -2 V
1
0
0
0
0
2
0.5
42.5
50.7
35.5
3
1
80.3
95.8
55.6
4
1.5
108
119.2
65.3
5
2
128.1
135.3
69.9
6
2.5
136.4
143.6
73.9
7
3
149.5
146.6
75.6
8
3.5
153.5
152.9
76.8
9
4
157.2
155.2
77.5
10
4.5
158
155.2
78.4
11
5
158
155.2
79.3
12
5.5
158
155.2
80
13
6
80.5
14
6.5
81.4
15
7
81.4
16
7.5
81.4
17
8
81.6
18
8.5
81.6
PH506_LABREPORT_3_21510110_21-22
GRAPH 1: PLOT FOR MOSFET DRAIN CHARACTERISTIC CURVE
PH506_LABREPORT_3_21510110_21-22
GRAPH 2: PLOT FOR FET DRAIN CHARACTERISTIC CURVE
PH506_LABREPORT_3_21510110_21-22
Result:
Discussion:
References: