MICROPROGRAMMED
CONTROL
1
CONTROL
UNIT
– Initiate sequences of microoperations
• Control signal (that specify microoperations) in a bus-organized system
– groups of bits that select the paths in multiplexers, decoders, and arithmetic logic units
– Finite Number Of Different Types Of Microoperations
Two major types of Control Unit
– Hardwired
• generated by hardware using conventional logic
• The control logic is implemented with gates, F/Fs, decoders, and other digital circuits
• + Fast operation, - Wiring change(if the design has to be modified)
–
Microprogramming
• an elegant and systematic method
• The control information is stored in a control memory, and the control memory is
programmed to initiate the required sequence of microoperations
• + Any required change can be done by updating the microprogram in control memory,
• - Slow operation
Microprogrammed Control Unit
–
During any given time, certain microoperations are to be initiated, while
others remain idle.
– Control Word
• The control variables at any given time can be represented by a string
of 1's and 0's.
• Programmed to perform various operations on the components of the
system
– Microprogrammed control unit
• A control unit whose binary control variables are stored in memory is
called a microprogrammed control unit
Control Unit Implementation
• Hardwired
Control Data
Memory
IR
Status F/Fs
Control Unit's State
Timing State
Ins. Cycle State
Combinational
Control
Logic Circuits
Points
CPU
Control Unit Implementation
• Microprogrammed
Memory
CAR: Control Address Register
CDR: Control Data Register
Instruction code
Next Address
Generator
(sequencer)
CAR
Control
Memory
CDR
Decoding
Circuit
.
.
Control
signals
Microprogrammed Control Unit
• Control memory
– A memory is part of a control unit
– Memory contains control words
• Microinstructions :Control Word in Control Memory
• The microinstruction specifies one or more microoperations
• Control words stored in control memory
• Specify control signals for execution of microoperations
• Microprogram
– Sequence of microinstructions
– Dynamic microprogramming : Control Memory = RAM
» RAM can be used for writing (to change a writable control memory)
» Microprogram is loaded initially from an auxiliary memory such as a
magnetic disk
– Static microprogramming : Control Memory = ROM
» Control words in ROM are made permanent during the hardware production.
Control Memory
• Read-only memory (ROM)
• Content of word in ROM at given address specifies microinstruction
• Each computer instruction initiates series of microinstructions (microprogram) in
control memory
• These microinstructions generate microoperations to
–
–
–
–
Fetch instruction from main memory
Evaluate effective address
Execute operation specified by instruction
Return control to fetch phase for next instruction
• Computer Memory (employs a microprogrammed control unit)
– Main Memory : for storing user program (Machine instruction/data)
– Control Memory : for storing microprogram (Microinstruction)
Address
Control
memory
(ROM)
Control word
(microinstruction)
Microprogrammed Control Organization
External
input
Next Address
Generator
(sequencer)
CAR
Control
Memory
(ROM)
CDR
• Control memory
– Contains microprograms (set of microinstructions)
– Microinstruction contains
• Bits initiate microoperations
• Bits determine address of next microinstruction
• Control address register (CAR)
– Specifies address of next microinstruction
• Next address generator (microprogram sequencer)
– Determines address sequence for control memory
• Microprogram sequencer functions
– Increment CAR by one
– Transfer external address into CAR
– Load initial address into CAR to start control operations
Control
word
Microprogrammed Control Organization
• Control data register (CDR)- or pipeline register
– Holds microinstruction read from control memory
– Allows execution of microoperations specified by control
word simultaneously with generation of next
microinstruction
• Control unit can operate without CDR
9
Microprogram Routines
• Routine
– Group of microinstructions stored in control memory
• Each computer instruction has its own microprogram routine to
generate microoperations that execute the instruction
• The hardware that controls the address sequencing of the
control memory must be capable of sequencing the
microinstructions within a routine and be able to branch from
one routine to another.
Address sequencing – Steps
• Initial address is loaded into the control address
register when power is turned on
– The address of the first microinstruction that activates
instruction fetch routine.
– The fetch routine may be sequenced by incrementing
control address register through the rest of
microinstructions
– At the end of the fetch routine, the instruction is in
instruction register of the computer
the
the
its
the
Address sequencing – Steps
• Control memory next go through the routine that determines the effective
address of the operand
– addressing modes, indirect address and index registers
– branch microinstruction
– address of the operand is available in the memory address register
•
Generate the microoperations that execute the instruction fetched from memory
– It depend on the operation code part of the instruction.
– Each instruction has its own microprogram routine stored in a given location of control memory.
– Transformation from the instruction code bits to an address in control memory
where the routine is located is referred to as a mapping process.
• Execution of the instruction is completed, control must return to the fetch routine.
Microprogram Routines
• Subroutine
– Sequence of microinstructions used by other routines to accomplish
particular task
• Example
– Subroutine to generate effective address of operand for memory reference
instruction
• Subroutine register (SBR)
– Stores return address during subroutine call
13
Conditional Branching
• Branching from one routine to another depends on status bit
conditions
• Status bits provide parameter info such as
– Carry-out of adder
– Sign bit of number
– Mode bits of instruction
• Info in status bits can be tested and actions initiated based on their
conditions: 1 or 0
• Unconditional branch
– Fix value of status bit to 1
14
Mapping of Instruction
• Each computer instruction has its own microprogram
routine stored in a given location of the control memory
• Mapping
– Transformation from instruction code bits to address in control
memory where routine is located
Mapping of Instruction
• Example
– Mapping 4-bit operation code to 7-bit address
OP-codes of Instructions
ADD 0000
AND 0001
LDA
0010
Mapping bits
0 xxxx 00
Control
memory
Address
0 0000 00
ADD Routine
0 0001 00
AND Routine
0 0010 00
LDA Routine
16
Address Sequencing
• Address sequencing capabilities required in control unit
– Incrementing CAR
– Unconditional or conditional branch, depending on status
bit conditions
– Mapping from bits of instruction to address for control
memory
– Facility for subroutine call and return
Address Sequencing
Instruction code
Mapping
logic
Status
bits
Branch
logic
MUX
Multiplexers
select
Subroutine
Register
(SBR)
Control Address Register
(CAR)
Incrementer
Control memory (ROM)
select a status
bit
Branch address
Microoperations
Address Sequencing
Selection of address for control memory :
• Multiplexer
 CAR Increment
 JMP/CALL
 Mapping
 Subroutine Return
• CAR : Control Address Register
– CAR receive the address from 4 different paths
1) Incrementer
2) Branch address from control memory
3) Mapping Logic
4) SBR : Subroutine Register
• SBR : Subroutine Register
– Return Address can not be stored in ROM
– Return Address for a subroutine is stored in SBR
Problems
•
The Address Sequencing system uses a control memory of 1024 words of 32 bits each. The
microinstruction has three fields. The microoperations field has 16 bits.
– a. How many bits are there in the branch address field and the select field?
– b. If there are 16 status bits in the system, how many bits of the branch logic are used to select a
status bit?
– c. How many bits are left to select an input for the multiplexers?
• a) Control memory = 210 × 32
• b) 4 bits
• c) 2 bits
Problems
The control memory in Address Sequencer has 4096 words of 24 bits each.
a. How many bits are there in the control address register?
b. How many bits are there in each of the four inputs shown going into the
multiplexers?
c. What are the number of inputs in each multiplexer and how many
multiplexers are needed?
• a) Control memory = 212 × 24
• b) 12 bits
• c) 12 bits, each 4 to 1 line
Problems
Using the mapping procedure , give the first
microinstruction address for the following operation
code:
(a) 0010; (b) 1011; (c) 1111.
– 0 0010 00 – 08 -- 8
– 0 1011 00 – 2C -- 44
– 0 1111 00 – 3C -- 60
Problems
Formulate a mapping procedure that provides eight consecutive
microinstructions for each routine. The operation code has six bits
and the control memory has 2048 words.
• Opcode – 6 bits
• Control memory – 2048 words – 211
• 00 xxxxxx 000 – 00 000000 000 -- 000
• 00 xxxxxx 000 – 00 000001 000 -- 008
• 00 xxxxxx 000 – 00 000010 000 -- 010
• 00 xxxxxx 000 – 00 000011 000 -- 018
• 00 xxxxxx 000 – 00 000100 000 -- 020
MICROPROGRAM
EXAMPLE
The designer's task is to generate the microcode for the
control memory.
This code generation is called microprogramming and is a
process similar to conventional machine language
programming.
• Computer Configuration
– memory units
•
a main memory for storing instructions and data
•
a control memory for storing the microprogram.
COMPUTER CONFIGURATION
• MEMORY UNITS
a main memory for storing instructions and data
• a control memory for storing the microprogram.
•
MUX
10
0
AR
Address
10
0
Memory
2048 x 16
PC
MUX
6
0
SBR
6
0
15
0
DR
CAR
Control memory
128 x 20
Arithmetic
logic and
shift unit
Control unit
15
0
AC
• REGISTERS
• PROCESSOR
• PC
• AR
• DR
• AC
• CONTROL UNIT
• CAR
• SBR
• The transfer of information among the registers in the
processor is done through multiplexers rather than a common
bus
• DR can receive information from AC, PC, or memory.
• AR can receive information from PC or DR
• PC can receive information only from AR.
• The
arithmetic,
logic,
and
shift
unit
performs
microoperations with data from AC and DR and places the
result in AC.
• Memory receives its address from AR. Input data written to
memory come from DR, and data read from memory can go
only to DR.
MACHINE INSTRUCTION FORMAT
Machine instruction format
15 14
11 10
Opcode
I
0
Address
Sample machine instructions
Symbol
ADD
BRANCH
STORE
EXCHANGE
OP-code
0000
0001
0010
0011
Description
AC  AC + M[EA]
if (AC < 0) then (PC  EA)
M[EA]  AC
AC  M[EA], M[EA]  AC
EA is the effective address
Microinstruction Format
3
F1
3
F2
3
F3
2
CD
2
BR
7
AD
F1, F2, F3: Microoperation fields
CD: Condition for branching
BR: Branch field
AD: Address field
Microprogram
MICROINSTRUCTION FIELD DESCRIPTIONS - F1,F2,F3
F1
000
001
010
011
100
101
110
111
Microoperation Symbol
None
NOP
AC  AC + DRADD
AC  0
CLRAC
AC  AC + 1 INCAC
AC  DR
DRTAC
AR  DR(0-10) DRTAR
AR  PC
PCTAR
M[AR]  DR WRITE
F3
000
001
010
011
100
101
110
111
F2
000
001
010
011
100
101
110
111
Microoperation Symbol
None
NOP
AC  AC - DR SUB
AC  AC  DR OR
AC  AC  DR AND
DR  M[AR] READ
DR  AC
ACTDR
DR  DR + 1 INCDR
DR(0-10)  PC PCTDR
Microoperation Symbol
None
NOP
AC  AC  DR XOR
AC  AC’
COM
AC  shl AC SHL
AC  shr AC SHR
PC  PC + 1 INCPC
PC  AR
ARTPC
Reserved
Microprogram
MICROINSTRUCTION FIELD DESCRIPTIONS - CD, BR
CD
00
01
10
11
Condition
Always = 1
DR(15)
AC(15)
AC = 0
BR
00
Symbol
JMP
01
CALL
10
11
RET
MAP
Symbol
U
I
S
Z
Comments
Unconditional branch
Indirect address bit
Sign bit of AC
Zero value in AC
Function
CAR  AD if condition = 1
CAR  CAR + 1 if condition = 0
CAR  AD, SBR  CAR + 1 if condition = 1
CAR  CAR + 1 if condition = 0
CAR  SBR (Return from subroutine)
CAR(2-5)  DR(11-14), CAR(0,1,6)  0
Microprogram
SYMBOLIC MICROINSTRUCTIONS
• Symbols are used in microinstructions as in assembly language
• A symbolic microprogram can be translated into its binary equivalent by a microprogram assembler.
Sample Format
five fields:
label; micro-ops; CD; BR; AD
Label:
may be empty or may specify a symbolic address terminated with a colon
Micro-ops: consists of one, two, or three symbols separated by commas
CD:
one of {U, I, S, Z}, where U: Unconditional Branch
I: Indirect address bit
S: Sign of AC
Z: Zero value in AC
BR:
one of {JMP, CALL, RET, MAP}
AD:
one of {Symbolic address, NEXT, empty}

Label
FETCH:

Microoperation
ORG 64
PCTAR
READ, INCPC
DRTAR
 

CD
BR
AD
U
U
U
JMP
JMP
MAP
NEXT
NEXT
0
Microprogram
SYMBOLIC MICROPROGRAM - FETCH ROUTINE During FETCH, Read an instruction from memory and decode the instruction and update PC
Sequence of microoperations in the fetch cycle:
AR  PC
DR  M[AR], PC  PC + 1
AR  DR(0-10), CAR(2-5)  DR(11-14), CAR(0,1,6)  0
Symbolic microprogram for the fetch cycle:
FETCH:
ORG 64
PCTAR
READ, INCPC
DRTAR
U JMP NEXT
U JMP NEXT
U MAP
Binary equivalents translated by an assembler
Binary
address
1000000
1000001
1000010
F1
110
000
101
F2
000
100
000
F3
000
101
000
CD
00
00
00
BR
00
00
11
AD
1000001
1000010
0000000
Microprogram
SYMBOLIC MICROPROGRAM
• Control Storage: 128 20-bit words
• The first 64 words: Routines for the 16 machine instructions
• The last 64 words: Used for other purpose (e.g., fetch routine and other subroutines)
• Mapping:
OP-code XXXX into 0XXXX00, the first address for the 16 routines are
0(0 0000 00), 4(0 0001 00), 8, 12, 16, 20, ..., 60
Partial Symbolic Microprogram
Label
ADD:
BRANCH:
OVER:
STORE:
EXCHANGE:
FETCH:
INDRCT:
Microops
CD
BR
AD
ORG 0
NOP
READ
ADD
I
U
U
CALL
JMP
JMP
INDRCT
NEXT
FETCH
ORG 4
NOP
NOP
NOP
ARTPC
S
U
I
U
JMP
JMP
CALL
JMP
OVER
FETCH
INDRCT
FETCH
ORG 8
NOP
ACTDR
WRITE
I
U
U
CALL
JMP
JMP
INDRCT
NEXT
FETCH
ORG 12
NOP
READ
ACTDR, DRTAC
WRITE
I
U
U
U
CALL
JMP
JMP
JMP
INDRCT
NEXT
NEXT
FETCH
ORG 64
PCTAR
READ, INCPC
DRTAR
READ
DRTAR
U
U
U
U
U
JMP
JMP
MAP
JMP
RET
NEXT
NEXT
NEXT
Microprogram
BINARY MICROPROGRAM
Micro Routine
ADD
BRANCH
STORE
EXCHANGE
FETCH
INDRCT
Address
Decimal Binary
0
0000000
1
0000001
2
0000010
3
0000011
4
0000100
5
0000101
6
0000110
7
0000111
8
0001000
9
0001001
10
0001010
11
0001011
12
0001100
13
0001101
14
0001110
15
0001111
64
65
66
67
68
1000000
1000001
1000010
1000011
1000100
F1
000
000
001
000
000
000
000
000
000
000
111
000
000
001
100
111
Binary Microinstruction
F2
F3
CD
000
000
01
100
000
00
000
000
00
000
000
00
000
000
10
000
000
00
000
000
01
000
110
00
000
000
01
101
000
00
000
000
00
000
000
00
000
000
01
000
000
00
101
000
00
000
000
00
BR
01
00
00
00
00
00
01
00
01
00
00
00
01
00
00
00
AD
1000011
0000010
1000000
1000000
0000110
1000000
1000011
1000000
1000011
0001010
1000000
1000000
1000011
0001110
0001111
1000000
110
000
101
000
101
000
100
000
100
000
00
00
11
00
10
1000001
1000010
0000000
1000100
0000000
000
101
000
000
000
This microprogram can be implemented using ROM
00
00
00
00
00
Design of Control Unit
DESIGN OF CONTROL UNIT
- DECODING ALU CONTROL INFORMATION microoperation fields
F1
F2
F3
3 x 8 decoder
3 x 8 decoder
3 x 8 decoder
76 54 3 21 0
7 6 54 3 21 0
76 54 321 0
AND
ADD
Arithmetic
logic and
shift unit
From
From
PC
DR(0-10)
DRTAR
PCTAR
DRTAC
Select
Load
Load
AC
DR
AC
0
1
Multiplexers
AR
Clock
Design of Control Unit
MICROPROGRAM SEQUENCER
- NEXT MICROINSTRUCTION
ADDRESS LOGIC
-
Branch, CALL Address
External
(MAP)
S1S0
00
01
10
11
Address Source
CAR + 1, In-Line
SBR RETURN
CS(AD), Branch or CALL
MAP
Address
source
selection
Clock
RETURN form Subroutine
In-Line
3 2 1 0
S1 MUX1
S0
SBR
L
Subroutine
CALL
Incrementer
CAR
Control Storage
MUX-1 selects an address from one of four sources and routes it into a CAR
- In-Line Sequencing  CAR + 1
- Branch, Subroutine Call  CS(AD)
- Return from Subroutine  Output of SBR
- New Machine instruction  MAP
Design of Control Unit
MICROPROGRAM SEQUENCER
- CONDITION AND BRANCH CONTROL -
1
From I
CPU S
MUX2
Z
L
Test
BR field
of CS
Select
T
Input
I0 logic
I
1
L(load SBR with PC)
for subroutine Call
S0 for next address
S1 selection
CD Field of CS
Input Logic
I0I1T
000
001
010
011
10x
11x
Meaning Source of Address
In-Line
JMP
In-Line
CALL
RET
MAP
CAR+1
CS(AD)
CAR+1
CS(AD) and SBR <- CAR+1
SBR
DR(11-14)
S0 = I0
S1 = I0I1 + I0’T
L = I0’I1T
S1S0
L
00
10
00
10
01
11
0
0
0
1
0
0
Design of Control Unit
MICROPROGRAM SEQUENCER
External
(MAP)
L
I
Input
I0
logic
1
T
1
I
S
Z
3 2 1 0
S1 MUX1
S0
SBR
Incrementer
MUX2
Test
Select
Clock
CAR
Control memory
Microops
...
CD
BR
AD
...
Load