Architecture of 8086
A Microprocessor is an Integrated Circuit with all the functions of a CPU however, it
cannot be used stand alone since unlike a microcontroller it has no memory or
peripherals.
8086 does not have a RAM or ROM inside it. However, it has internal registers for
storing intermediate and final results and interfaces with memory located outside it
through the System Bus.
In case of 8086, it is a 16-bit Integer processor in a 40 pin, Dual Inline Packaged IC.
The size of the internal registers(present within the chip) indicate how much information
the processor can operate on at a time (in this case 16-bit registers) and how it moves
data around internally within the chip, sometimes also referred to as the internal data
bus.
8086 provides the programmer with 14 internal registers, each 16 bits or 2 Bytes wide.
Memory segmentation:
 To increase execution speed and fetching speed, 8086 segments the memory.
 It’s 20 bit address bus can address 1MB of memory, it segments it into 16 64kB
segments.
 8086 works only with four 64KB segments within the whole 1MB memory.
The internal architecture of Intel 8086 is divided into 2 units: The Bus Interface Unit
(BIU), and The Execution Unit (EU). These are explained as following below.
1. The Bus Interface Unit (BIU):
It provides the interface of 8086 to external memory and I/O devices via the System Bus.
It performs various machine cycles such as memory read, I/O read etc. to transfer data
between memory and I/O devices.
BIU performs the following functions
It generates the 20 bit physical address for memory access.
It fetches instructions from the memory.
 It transfers data to and from the memory and I/O.
 Maintains the 6 byte prefetch instruction queue(supports pipelining).
BIU mainly contains the 4 Segment registers, the Instruction Pointer, a prefetch queue
and an Address Generation Circuit.
Instruction Pointer (IP):
 It is a 16 bit register. It holds offset of the next instructions in the Code Segment.
 IP is incremented after every instruction byte is fetched.
 IP gets a new value whenever a branch instruction occurs.
 CS is multiplied by 10H to give the 20 bit physical address of the Code Segment.
 Address of the next instruction is calculated as CS x 10H + IP.

Example:
CS = 4321H IP = 1000H
then CS x 10H = 43210H + offset =
44210H
This is the address of the instruction.
Code Segment register:
CS holds the base address for the Code Segment. All programs are stored in the Code
Segment and accessed via the IP.
Data Segment register:
DS holds the base address for the Data Segment.
Stack Segment register:
SS holds the base address for the Stack Segment.
Extra Segment register:
ES holds the base address for the Extra Segment.
Address Generation Circuit:
 The BIU has a Physical Address Generation Circuit.
 It generates the 20 bit physical address using Segment and Offset addresses using the
formula:
Physical Address
= Segment Address x 10H + Offset Address
6 Byte Pre-fetch Queue:
 It is a 6 byte queue (FIFO).
 Fetching the next instruction (by BIU from CS) while executing the current
instruction is called pipelining.
 Gets flushed whenever a branch instruction occurs.
2. The Execution Unit (EU):
The main components of the EU are General purpose registers, the ALU, Special purpose
registers, Instruction Register and Instruction Decoder and the Flag/Status Register.
1. Fetches instructions from the Queue in BIU, decodes and executes arithmetic and
logic operations using the ALU.
2. Sends control signals for internal data transfer operations within the microprocessor.
3. Sends request signals to the BIU to access the external module.
4. It operates with respect to T-states (clock cycles) and not machine cycles.
8086 has four 16 bit general purpose registers AX, BX, CX and DX. Store intermediate
values during execution. Each of these have two 8 bit parts (higher and lower).
 AX register:
It holds operands and results during multiplication and division operations. Also an
accumulator during String operations.

BX register:
It holds the memory address (offset address) in indirect addressing modes.

CX register:
It holds count for instructions like loop, rotate, shift and string operations.

DX register:
It is used with AX to hold 32 bit values during multiplication and division.
Arithmetic Logic Unit (16 bit):
Performs 8 and 16 bit arithmetic and logic operations.
Special purpose registers (16-bit):
 Stack Pointer:
Points to Stack top. Stack is in Stack Segment, used during instructions like PUSH,
POP, CALL, RET etc.
 Base Pointer:
BP can hold offset address of any location in the stack segment. It is used to access
random locations of the stack.
 Source Index:
It holds offset address in Data Segment during string operations.
 Destination Index:
It holds offset address in Extra Segment during string operations.
Instruction Register and Instruction Decoder:
The EU fetches an opcode from the queue into the instruction register. The instruction
decoder decodes it and sends the information to the control circuit for execution.
Flag/Status register (16 bits):
It has 9 flags that help change or recognize the state of the microprocessor.
6 Status flags:
1. carry flag(CF)
2. parity flag(PF)
3. auxiliary carry flag(AF)
4. zero flag(Z)
5. sign flag(S)
6. overflow flag (O)
Status flags are updated after every arithmetic and logic operation.
3 Control flags:
1. trap flag(TF)
2. interrupt flag(IF)
3. direction flag(DF)
These flags can be set or reset using control instructions like CLC, STC, CLD, STD, CLI,
STI, etc.
The Control flags are used to control certain operations.
Pin diagram of 8086 microprocessor
Pin diagram of 8086 microprocessor is as given below:
Intel 8086 is a 16-bit HMOS microprocessor. It is available in 40 pin DIP chip. It uses a
5V DC supply for its operation. The 8086 uses 20-line address bus. It has a 16-line data
bus. The 20 lines of the address bus operate in multiplexed mode. The 16-low order
address bus lines have been multiplexed with data and 4 high-order address bus lines
have been multiplexed with status signals.
AD0-AD15 : Address/Data bus. These are low order address bus. They are multiplexed
with data. When AD lines are used to transmit memory address the symbol A is used
instead of AD, for example A0-A15. When data are transmitted over AD lines the symbol
D is used in place of AD, for example D0-D7, D8-D15 or D0-D15.
A16-A19 : High order address bus. These are multiplexed with status signals.
S2, S1, S0 : Status pins. These pins are active during T4, T1 and T2 states and is returned
to passive state (1,1,1 during T3 or Tw (when ready is inactive). These are used by the
8288 bus controller for generating all the memory and I/O operation) access control
signals. Any change in S2, S1, S0 during T4 indicates the beginning of a bus cycle.
S2
S1
S0
Characteristics
0
0
0
Interrupt acknowledge
0
0
1
Read I/O port
0
1
0
Write I/O port
0
1
1
Halt
1
0
0
Code access
1
0
1
Read memory
1
1
0
Write memory
S2
S1
S0
Characteristics
1
1
1
Passive state
A16/S3, A17/S4, A18/S5, A19/S6 : The specified address lines are multiplexed with
corresponding status signals.
A17/S4
A16/S3
Function
0
0
Extra segment access
0
1
Stack segment access
1
0
Code segment access
1
1
Data segment access
BHE’/S7 : Bus High Enable/Status. During T1 it is low. It is used to enable data onto the
most significant half of data bus, D8-D15. 8-bit device connected to upper half of the
data bus use BHE (Active Low) signal. It is multiplexed with status signal S7. S7 signal
is available during T2, T3 and T4.
RD’: This is used for read operation. It is an output signal. It is active when low.
READY : This is the acknowledgement from the memory or slow device that they have
completed the data transfer. The signal made available by the devices is synchronized by
the 8284A clock generator to provide ready input to the microprocessor. The signal is
active high(1).
INTR : Interrupt Request. This is triggered input. This is sampled during the last clock
cycles of each instruction for determining the availability of the request. If any interrupt
request is found pending, the processor enters the interrupt acknowledge cycle. This can
be internally masked after resulting the interrupt enable flag. This signal is active high(1)
and has been synchronized internally.
NMI : Non maskable interrupt. This is an edge triggered input which results in a type II
interrupt. A subroutine is then vectored through an interrupt vector lookup table which is
located in the system memory. NMI is non-maskable internally by software. A transition
made from low(0) to high(1) initiates the interrupt at the end of the current instruction.
This input has been synchronized internally.
INTA : Interrupt acknowledge. It is active low(0) during T2, T3 and Tw of each interrupt
acknowledge cycle.
MN/MX’ : Minimum/Maximum. This pin signal indicates what mode the processor will
operate in.
RQ’/GT1′, RQ’/GT0′ : Request/Grant. These pins are used by local bus masters used to
force the microprocessor to release the local bus at the end of the microprocessor’s
current bus cycle. Each of the pin is bi-directional. RQ’/GT0′ have higher priority than
RQ’/GT1′.
LOCK’ : Its an active low pin. It indicates that other system bus masters have not been
allowed to gain control of the system bus while LOCK’ is active low(0). The LOCK
signal will be active until the completion of the next instruction.
TEST’ : This examined by a ‘WAIT’ instruction. If the TEST pin goes low(0), execution
will continue, else the processor remains in an idle state. The input is internally
synchronized during each of the clock cycle on leading edge of the clock.
CLK : Clock Input. The clock input provides the basic timing for processing operation
and bus control activity. Its an asymmetric square wave with a 33% duty cycle.
RESET : This pin requires the microprocessor to terminate its present activity
immediately. The signal must be active high(1) for at least four clock cycles.
Vcc : Power Supply( +5V D.C.)
GND : Ground
QS1,QS0 : Queue Status. These signals indicate the status of the internal 8086
instruction queue according to the table shown below
QS1
QS0
Status
0
0
No operation
0
1
First byte of op code from queue
1
0
Empty the queue
1
1
Subsequent byte from queue
DT/R : Data Transmit/Receive. This pin is required in minimum systems, that want to
use an 8286 or 8287 data bus transceiver. The direction of data flow is controlled through
the transceiver.
DEN : Data enable. This pin is provided as an output enable for the 8286/8287 in a
minimum system which uses transceiver. DEN is active low(0) during each memory and
input-output access and for INTA cycles.
HOLD/HOLDA : HOLD indicates that another master has been requesting a local bus
.This is an active high(1). The microprocessor receiving the HOLD request will issue
HLDA (high) as an acknowledgement in the middle of a T4 or T1 clock cycle.
ALE : Address Latch Enable. ALE is provided by the microprocessor to latch the address
into the 8282 or 8283 address latch. It is an active high(1) pulse during T1 of any bus
cycle. ALE signal is never floated, is always integer.
Architecture of 8086
A Microprocessor is an Integrated Circuit with all the functions of a CPU however, it
cannot be used stand alone since unlike a microcontroller it has no memory or
peripherals.
8086 does not have a RAM or ROM inside it. However, it has internal registers for
storing intermediate and final results and interfaces with memory located outside it
through the System Bus.
In case of 8086, it is a 16-bit Integer processor in a 40 pin, Dual Inline Packaged IC.
The size of the internal registers(present within the chip) indicate how much information
the processor can operate on at a time (in this case 16-bit registers) and how it moves
data around internally within the chip, sometimes also referred to as the internal data
bus.
8086 provides the programmer with 14 internal registers, each 16 bits or 2 Bytes wide.
Memory segmentation:
 To increase execution speed and fetching speed, 8086 segments the memory.
 It’s 20 bit address bus can address 1MB of memory, it segments it into 16 64kB
segments.
 8086 works only with four 64KB segments within the whole 1MB memory.
The internal architecture of Intel 8086 is divided into 2 units: The Bus Interface Unit
(BIU), and The Execution Unit (EU). These are explained as following below.
1. The Bus Interface Unit (BIU):
It provides the interface of 8086 to external memory and I/O devices via the System Bus.
It performs various machine cycles such as memory read, I/O read etc. to transfer data
between memory and I/O devices.
BIU performs the following functions
It generates the 20 bit physical address for memory access.
 It fetches instructions from the memory.
 It transfers data to and from the memory and I/O.
 Maintains the 6 byte prefetch instruction queue(supports pipelining).
BIU mainly contains the 4 Segment registers, the Instruction Pointer, a prefetch queue
and an Address Generation Circuit.
Instruction Pointer (IP):
 It is a 16 bit register. It holds offset of the next instructions in the Code Segment.
 IP is incremented after every instruction byte is fetched.

IP gets a new value whenever a branch instruction occurs.
 CS is multiplied by 10H to give the 20 bit physical address of the Code Segment.
 Address of the next instruction is calculated as CS x 10H + IP.
Example:
CS = 4321H IP = 1000H
then CS x 10H = 43210H + offset =
44210H
This is the address of the instruction.
Code Segment register:
CS holds the base address for the Code Segment. All programs are stored in the Code
Segment and accessed via the IP.
Data Segment register:
DS holds the base address for the Data Segment.
Stack Segment register:
SS holds the base address for the Stack Segment.
Extra Segment register:
ES holds the base address for the Extra Segment.
Address Generation Circuit:
 The BIU has a Physical Address Generation Circuit.
 It generates the 20 bit physical address using Segment and Offset addresses using the
formula:
Physical Address
= Segment Address x 10H + Offset Address
6 Byte Pre-fetch Queue:
 It is a 6 byte queue (FIFO).
 Fetching the next instruction (by BIU from CS) while executing the current
instruction is called pipelining.
 Gets flushed whenever a branch instruction occurs.
2. The Execution Unit (EU):
The main components of the EU are General purpose registers, the ALU, Special purpose
registers, Instruction Register and Instruction Decoder and the Flag/Status Register.
1. Fetches instructions from the Queue in BIU, decodes and executes arithmetic and
logic operations using the ALU.
2. Sends control signals for internal data transfer operations within the microprocessor.
3. Sends request signals to the BIU to access the external module.
4. It operates with respect to T-states (clock cycles) and not machine cycles.
8086 has four 16 bit general purpose registers AX, BX, CX and DX. Store intermediate
values during execution. Each of these have two 8 bit parts (higher and lower).

AX register:
It holds operands and results during multiplication and division operations. Also an
accumulator during String operations.

BX register:
It holds the memory address (offset address) in indirect addressing modes.

CX register:
It holds count for instructions like loop, rotate, shift and string operations.

DX register:
It is used with AX to hold 32 bit values during multiplication and division.
Arithmetic Logic Unit (16 bit):
Performs 8 and 16 bit arithmetic and logic operations.
Special purpose registers (16-bit):
 Stack Pointer:
Points to Stack top. Stack is in Stack Segment, used during instructions like PUSH,
POP, CALL, RET etc.
 Base Pointer:
BP can hold offset address of any location in the stack segment. It is used to access
random locations of the stack.
 Source Index:
It holds offset address in Data Segment during string operations.
 Destination Index:
It holds offset address in Extra Segment during string operations.
Instruction Register and Instruction Decoder:
The EU fetches an opcode from the queue into the instruction register. The instruction
decoder decodes it and sends the information to the control circuit for execution.
Flag/Status register (16 bits):
It has 9 flags that help change or recognize the state of the microprocessor.
6 Status flags:
1. carry flag(CF)
2. parity flag(PF)
3. auxiliary carry flag(AF)
4. zero flag(Z)
5. sign flag(S)
6. overflow flag (O)
Status flags are updated after every arithmetic and logic operation.
3 Control flags:
1. trap flag(TF)
2. interrupt flag(IF)
3. direction flag(DF)
These flags can be set or reset using control instructions like CLC, STC, CLD, STD, CLI,
STI, etc.
The Control flags are used to control certain operations.
Intel 8086 is a 16-bit HMOS microprocessor. It is available in 40 pin DIP chip. It uses a
5V DC supply for its operation. The 8086 uses 20-line address bus. It has a 16-line data
bus. The 20 lines of the address bus operate in multiplexed mode. The 16-low order
address bus lines have been multiplexed with data and 4 high-order address bus lines
have been multiplexed with status signals.
AD0-AD15 : Address/Data bus. These are low order address bus. They are multiplexed
with data. When AD lines are used to transmit memory address the symbol A is used
instead of AD, for example A0-A15. When data are transmitted over AD lines the symbol
D is used in place of AD, for example D0-D7, D8-D15 or D0-D15.
A16-A19 : High order address bus. These are multiplexed with status signals.
S2, S1, S0 : Status pins. These pins are active during T4, T1 and T2 states and is returned
to passive state (1,1,1 during T3 or Tw (when ready is inactive). These are used by the
8288 bus controller for generating all the memory and I/O operation) access control
signals. Any change in S2, S1, S0 during T4 indicates the beginning of a bus cycle.
S2
S1
S0
Characteristics
0
0
0
Interrupt acknowledge
0
0
1
Read I/O port
0
1
0
Write I/O port
0
1
1
Halt
1
0
0
Code access
1
0
1
Read memory
S2
S1
S0
Characteristics
1
1
0
Write memory
1
1
1
Passive state
A16/S3, A17/S4, A18/S5, A19/S6 : The specified address lines are multiplexed with
corresponding status signals.
A17/S4
A16/S3
Function
0
0
Extra segment access
0
1
Stack segment access
1
0
Code segment access
1
1
Data segment access
BHE’/S7 : Bus High Enable/Status. During T1 it is low. It is used to enable data onto the
most significant half of data bus, D8-D15. 8-bit device connected to upper half of the
data bus use BHE (Active Low) signal. It is multiplexed with status signal S7. S7 signal
is available during T2, T3 and T4.
RD’: This is used for read operation. It is an output signal. It is active when low.
READY : This is the acknowledgement from the memory or slow device that they have
completed the data transfer. The signal made available by the devices is synchronized by
the 8284A clock generator to provide ready input to the microprocessor. The signal is
active high(1).
INTR : Interrupt Request. This is triggered input. This is sampled during the last clock
cycles of each instruction for determining the availability of the request. If any interrupt
request is found pending, the processor enters the interrupt acknowledge cycle. This can
be internally masked after resulting the interrupt enable flag. This signal is active high(1)
and has been synchronized internally.
NMI : Non maskable interrupt. This is an edge triggered input which results in a type II
interrupt. A subroutine is then vectored through an interrupt vector lookup table which is
located in the system memory. NMI is non-maskable internally by software. A transition
made from low(0) to high(1) initiates the interrupt at the end of the current instruction.
This input has been synchronized internally.
INTA : Interrupt acknowledge. It is active low(0) during T2, T3 and Tw of each interrupt
acknowledge cycle.
MN/MX’ : Minimum/Maximum. This pin signal indicates what mode the processor will
operate in.
RQ’/GT1′, RQ’/GT0′ : Request/Grant. These pins are used by local bus masters used to
force the microprocessor to release the local bus at the end of the microprocessor’s
current bus cycle. Each of the pin is bi-directional. RQ’/GT0′ have higher priority than
RQ’/GT1′.
LOCK’ : Its an active low pin. It indicates that other system bus masters have not been
allowed to gain control of the system bus while LOCK’ is active low(0). The LOCK
signal will be active until the completion of the next instruction.
TEST’ : This examined by a ‘WAIT’ instruction. If the TEST pin goes low(0), execution
will continue, else the processor remains in an idle state. The input is internally
synchronized during each of the clock cycle on leading edge of the clock.
CLK : Clock Input. The clock input provides the basic timing for processing operation
and bus control activity. Its an asymmetric square wave with a 33% duty cycle.
RESET : This pin requires the microprocessor to terminate its present activity
immediately. The signal must be active high(1) for at least four clock cycles.
Vcc : Power Supply( +5V D.C.)
GND : Ground
QS1,QS0 : Queue Status. These signals indicate the status of the internal 8086
instruction queue according to the table shown below
QS1
QS0
Status
0
0
No operation
0
1
First byte of op code from queue
1
0
Empty the queue
1
1
Subsequent byte from queue
DT/R : Data Transmit/Receive. This pin is required in minimum systems, that want to
use an 8286 or 8287 data bus transceiver. The direction of data flow is controlled through
the transceiver.
DEN : Data enable. This pin is provided as an output enable for the 8286/8287 in a
minimum system which uses transceiver. DEN is active low(0) during each memory and
input-output access and for INTA cycles.
HOLD/HOLDA : HOLD indicates that another master has been requesting a local bus
.This is an active high(1). The microprocessor receiving the HOLD request will issue
HLDA (high) as an acknowledgement in the middle of a T4 or T1 clock cycle.
ALE : Address Latch Enable. ALE is provided by the microprocessor to latch the address
into the 8282 or 8283 address latch. It is an active high(1) pulse during T1 of any bus
cycle. ALE signal is never floated, is always integer.
Memory Segmentation
Segmentation is the process in which the main memory of the computer is logically
divided into different segments and each segment has its own base address. It is basically
used to enhance the speed of execution of the computer system, so that the processor is
able to fetch and execute the data from the memory easily and fast.
Need for Segmentation –
The Bus Interface Unit (BIU) contains four 16 bit special purpose registers (mentioned
below) called as Segment Registers.
 Code segment register (CS): is used for addressing memory location in the code
segment of the memory, where the executable program is stored.
 Data segment register (DS): points to the data segment of the memory where the
data is stored.
 Extra Segment Register (ES): also refers to a segment in the memory which is
another data segment in the memory.
 Stack Segment Register (SS): is used for addressing stack segment of the memory.
The stack segment is that segment of memory which is used to store stack data.
The number of address lines in 8086 is 20, 8086 BIU will send 20bit address, so as to
access one of the 1MB memory locations.
The four segment registers actually contain the upper 16 bits of the starting addresses of
the four memory segments of 64 KB each with which the 8086 is working at that instant
of time.
A segment is a logical unit of memory that may be up to 64 kilobytes long. Each segment
is made up of contiguous memory locations. It is an independent, separately addressable
unit. Starting address will always be changing. It will not be fixed.
Note that the 8086 does not work the whole 1MB memory at any given time. However, it
works only with four 64KB segments within the whole 1MB memory.
Below is the one way of positioning four 64 kilobyte segments within the 1M byte
memory space of an 8086.
Types Of Segmentation –
1. Overlapping Segment – A segment starts at a particular address and its maximum
size can go up to 64kilobytes. But if another segment starts along with this
64kilobytes location of the first segment, then the two are said to be Overlapping
Segment.
2. Non-Overlapped Segment – A segment starts at a particular address and its
maximum size can go up to 64kilobytes. But if another segment starts before this
64kilobytes location of the first segment, then the two segments are said to be NonOverlapped Segment.
Rules of Segmentation Segmentation process follows some rules as follows:
 The starting address of a segment should be such that it can be evenly divided by 16.
 Minimum size of a segment can be 16 bytes and the maximum can be 64 kB.
Advantages of the Segmentation The main advantages of segmentation are as
follows:
 It provides a powerful memory management mechanism.
 Data related or stack related operations can be performed in different
segments.
 Code related operation can be done in separate code segments.
 It allows to processes to easily share data.
 It allows to extend the address ability of the processor, i.e. segmentation
allows the use of 16 bit registers to give an addressing capability of 1
Megabytes. Without segmentation, it would require 20 bit registers.
 It is possible to enhance the memory size of code data or stack segments
beyond 64 KB by allotting more than one segment for each area.
General purpose registers in 8086
microprocessor
General purpose registers are used to store temporary data within the microprocessor.
There are 8 general purpose registers in 8086 microprocessor.
Figure – General Purpose Registers
1. AX – This is the accumulator. It is of 16 bits and is divided into two 8-bit registers
AH and AL to also perform 8-bit instructions.
It is generally used for arithmetical and logical instructions.
Example:
ADD AX, AX (AX = AX + AX)
2. BX – This is the base register. It is of 16 bits and is divided into two 8-bit registers
BH and BL to also perform 8-bit instructions.
It is used to store the value of the offset.
Example:
MOV BL, [500] (BL = 500H)
3. CX – This is the counter register. It is of 16 bits and is divided into two 8-bit registers
CH and CL to also perform 8-bit instructions.
It is used in looping and rotation.
Example:
MOV CX, 0005
LOOP
4. DX – This is the data register. It is of 16 bits and is divided into two 8-bit registers
DH and DL to also perform 8-bit instructions.
It is used in multiplication an input/output port addressing.
Example:
MUL BX (DX, AX = AX * BX)
5. SP – This is the stack pointer. It is of 16 bits.
It points to the topmost item of the stack. If the stack is empty the stack pointer will
be (FFFE)H. It’s offset address relative to stack segment.
6. BP – This is the base pointer. It is of 16 bits.
It is primary used in accessing parameters passed by the stack. It’s offset address
relative to stack segment.
7. SI – This is the source index register. It is of 16 bits.
It is used in the pointer addressing of data and as a source in some string related
operations. It’s offset is relative to data segment.
8. DI – This is the destination index register. It is of 16 bits.
It is used in the pointer addressing of data and as a destination in some string related
operations. It’s offset is relative to extra segment.
Flag register of 8086 microprocessor
The Flag register is a Special Purpose Register. Depending upon the value of result after
any arithmetic and logical operation the flag bits become set (1) or reset (0).
Figure – Format of flag register
There are total 9 flags in 8086 and the flag register is divided into two types:
(a) Status Flags and (b) Control Flags
(a) Status Flags – There are 6 flag registers in 8086 microprocessor which become set(1)
or reset(0) depending upon condition after either 8-bit or 16-bit operation. These flags are
conditional/status flags. 5 of these flags are same as in case of 8085 microprocessor and
their working is also same as in 8085 microprocessor. The sixth one is the overflow flag.
The 6 status flags are:
1.
2.
3.
4.
Sign Flag (S)
Zero Flag (Z)
Auxiliary Cary Flag (AC)
Parity Flag (P)
5. Carry Flag (CY)
These first five flags are defined here
6. Overflow Flag (O) – This flag will be set (1) if the result of a signed operation is too
large to fit in the number of bits available to represent it, otherwise reset (0). After any
operation, if D[6] generates any carry and passes to D[7] OR if D[6] does not
generates carry but D[7] generates, overflow flag becomes set, i.e., 1. If D[6] and
D[7] both generate carry or both do not generate any carry, then overflow flag
becomes reset, i.e., 0.
Example: On adding bytes 100 + 50 (result is not in range -128…127), so overflow
flag will set.
MOV AL, 50 (50 is 01010000 which is positive)
MOV BL, 32 (32 is 00110010 which is positive)
ADD AL, BL (82 is 10000010 which is negative)
Overflow flag became set as we added 2 +ve numbers and we got a -ve number.
(b) Control Flags – The control flags enable or disable certain operations of the
microprocessor. There are 3 control flags in 8086 microprocessor and these are:
1. Directional Flag (D) – This flag is specifically used in string instructions.
If directional flag is set (1), then access the string data from higher memory location
towards lower memory location.
If directional flag is reset (0), then access the string data from lower memory location
towards higher memory location.
2. Interrupt Flag (I) – This flag is for interrupts.
If interrupt flag is set (1), the microprocessor will recognize interrupt requests from
the peripherals.
If interrupt flag is reset (0), the microprocessor will not recognize any interrupt
requests and will ignore them.
3. Trap Flag (T) – This flag is used for on-chip debugging. Setting trap flag puts the
microprocessor into single step mode for debugging. In single stepping, the
microprocessor executes a instruction and enters into single step ISR.
If trap flag is set (1), the CPU automatically generates an internal interrupt after each
instruction, allowing a program to be inspected as it executes instruction by
instruction.
If trap flag is reset (0), no function is performed.