From May 2008 High Frequency Electronics
Copyright © 2008 Summit Technical Media, LLC
High Frequency Design
SYNTHESIZER DESIGN
Building a Microwave
Frequency Synthesizer —
Part 1: Getting Started
By Alexander Chenakin
Phase Matrix, Inc.
T
he frequency synthesizer is a key
building block of
virtually any microwave
test and measurement,
communication or monitoring
system
[1-5].
Synthesizers come in a
variety of forms ranging from a tiny PLL chip
to a bench-top signal generator. Traditionally
we imagine them as a connectorized metal box
or “brick” which can be put into a more complex instrument or subsystem.
This series of articles presents an overview
of microwave frequency synthesizer technologies and design techniques with a specific
focus on the synthesizer “brick” modules. It
starts with general requirements and specifications followed by a review of the main synthesizer architectures. Direct analog, direct
digital, and indirect techniques are compared
in terms of performance, circuit complexity,
and cost impact. A simple, single-loop PLL
example is used to demonstrate the most
important aspects of the design process from a
general block diagram and component selection to schematic, board layout, assembling,
and testing. The design trade-offs are further
analyzed and complemented with a detailed
review of the most advanced synthesizer solutions including DDS-based and multiloop
schemes.
Synthesizer design methods
have evolved over time,
and this series of articles
offers an update on wellestablished and recentlydeveloped techniques
Reviewing the Specifications
A frequency synthesizer can be treated as
a black box that translates one (or more) input
base (reference) frequency to a number of output frequencies as shown in Figure 1. The box
contains individual components such as volt58
High Frequency Electronics
Figure 1 · The fundamental concept of a
frequency synthesizer.
age-controlled oscillators, frequency dividers,
multipliers, phase detectors, mixers, amplifiers, etc., which being properly connected,
perform this translation function. Although all
synthesizers exhibit significant differences as
a result of specific applications, they share
basic characteristics and design objectives as
listed below. The synthesizer’s characteristics
are divided into a few groups depicting its frequency and timing (i.e., frequency coverage,
resolution, stability, switching speed); spectral
purity (i.e., harmonics, spurious, phase noise);
output power (i.e., output power, flatness, control range). In addition to these signal-related
behaviors, a specification defines how it interfaces to the outside world (control interface,
bias, power consumption, size, etc.).
Frequency Coverage or Range and
Frequency Resolution or Step Size are the fundamental synthesizer specifications set by a
particular application. Some applications (e.g.,
test and measurement) require wide bandwidth and fine frequency resolution while others need a relatively narrowband (10-20%)
coverage with a rough step or just a single
fixed frequency.
Frequency Stability is determined by the
High Frequency Design
SYNTHESIZER DESIGN
Figure 2 · Synthesizer time base and synchronization.
Figure 3 · Harmonics.
Figure 4 · Switched filter bank.
reference signal, which can be internal or external to the synthesizer.
The synthesizer usually includes a
temperature-compensated (TCXO) or
ovenized (OCXO) crystal oscillator
that serves as both an internal time
base and low phase noise source
(Figure 2). The internal time base
(usually 10 MHz) can be locked to an
external reference signal or used by
itself for synchronization of external
equipment. It is also good practice to
use mechanical or electronic frequency adjustment means to compensate
for internal time base aging.
Switching or Tuning Speed determines how fast the synthesizer jumps
from one desired frequency to another and is normally specified as time
spent by the synthesizer between
jumps. The switching speed is determined by a particular synthesizer
scheme and is usually a trade-off
among other synthesizer parameters,
such as step size, spurious, or phase
noise.
Harmonics appear in the synthesizer spectrum as multiples of the
output frequency due to signal distortion in non-linear components
such as an amplifier (Figure 3).
Harmonics usually do not cause serious trouble since they are very well
separated from the main signal. The
levels of –20 to –30 dBc are acceptable in many cases, although they
should be reduced to –50 or –60 dBc
in some harmonic-sensitive applications or test and measurement
instruments. For a narrowband synthesizer, it is easily achieved by
putting a low-pass filter at the output; a switched filter bank (Figure 4)
is required for synthesizer band-
60
High Frequency Electronics
widths reaching or exceeding an
octave.
Sub-Harmonics are created at frequencies that are “sub-harmonically”
related to the main signal as shown
in Figure 5. A typical example is a
frequency doubler, which is often
used to extend the output frequency
range. As a non-linear device, the
doubler generates a number of harmonics of the incoming signal.
Moreover, it usually employs a balanced configuration that tends to
suppress the odd harmonics and,
therefore, accent the desired second
harmonic. Since the second harmonic
becomes our main signal, all the odd
products do not meet the harmonic
relationship in respect to the desired
output anymore and are specified as
sub-harmonics. Another example is
divider leakage, which can be found
in PLL circuits as shown in Figure 6.
Spurious Signals or Spurs are
undesired artifacts created by synthesizer components at discrete frequencies that are not harmonically
related to the output (Figure 7).
Spurious can come from different
sources such as PLL reference spurs,
DDS spurs, mixer sidebands and LO
leakages, some internal auxiliary signals or even external signals coming
through bias and control interface
circuits. Although the spurs look randomly positioned in the synthesizer
spectrum, their location is determined by a particular synthesizer
architecture and frequency plan. In
contrast to harmonics, the spurs are
much more troublemaking products
that can limit the ability of receiving
systems to resolve and process a
desired signal. They can be located
very close to the main tone and,
therefore, cannot be filtered. Thus,
the spurious level has to be minimized, typically to –60 dBc relative to
the main signal, although many
applications require bringing this
level down to –70, –80 dBc and even
below.
Phase Noise is another measure of
the synthesizer frequency instability,
High Frequency Design
SYNTHESIZER DESIGN
Figure 5 · Sub-harmonic generation scheme.
which manifests itself as random frequency fluctuations around the
desired tone (Figure 7). It is one of
the major parameters that ultimately
limits the sensitivity of receiving systems. Synthesizer close-in phase
noise strictly depends on the reference signal as well as the particular
architecture used to derive its output
from the reference. Indirect synthesizers also rely on tunable oscillator
noise, which can supersede the multiplied reference noise at high frequency offsets. Phase noise minimization
is a primary design concern; it
requires a specific effort and is usually a trade-off between other synthesizer parameters.
Output Power can range in wide
limits depending on a particular
application. A typical scenario
assumes the frequency synthesizer
as an LO source driving a frequency
mixer in a variety of up- and downconversion schemes. This normally
requires +10 to +17 dBm output signal, although some applications need
more power. The output power can be
controlled with an attenuator as
shown in Figure 8. The same control
can be used to reduce output power
variations versus frequency (specified as output power flatness) by
applying a proper correction voltage
setting, stored in synthesizer memory. A more precise control can be
achieved with a closed-loop automatic level control scheme (ALC) by
62
High Frequency Electronics
Figure 6 · Another sub-harmonic example.
Figure 7 · Spurious and phase noise in the output spectrum.
adding a directional coupler and
detector, which generates a correction
signal that is fed back to the attenuator (Figure 9). This configuration
does not depend on the amplifier gain
and power variations; it is also less
sensitive to the output load mismatch
due to the coupler directivity.
The Control Interface should be
fast, versatile, and easy to use.
Although, there is no set industry
Figure 8 · Output power control
using an attenuator.
standard for “brick” level products,
serial peripheral interface (SPI) is
the most prevalent, offering full
duplex communication, relatively
high throughput and flexibility. RS232 is a simple and useful interface
used when the distance from the
Figure 9 · Closed-loop digital ALC.
High Frequency Design
SYNTHESIZER DESIGN
Figure 10 · Synthesizer design trade-offs.
master controller exceeds SPI capability. Another very desirable interface is universal serial bus (USB),
which allows instant deployment or
just evaluation of the synthesizer
from a laptop computer. All the mentioned interfaces require a CPU or
microcontroller internal to the synthesizer to perform data communication or translation functions. The
designer should be very careful
selecting a processor to keep the processing time at a minimum. Ideally,
the synthesizer should have a direct
access option; in other words, the
ability to communicate directly with
the components within the synthesizer. Another way to eliminate the processing time is utilizing a “list mode”
that defines a list of frequencies to
jump between. Knowing these frequencies, one can pre-calculate and
memorize all necessary parameters
required to control individual components of the synthesizer.
Other specifications cover bias,
power consumption, mechanical and
environmental characteristics as well
as some special features such as a
dual output, various modulation
options, etc.
Design Challenges
The microwave industry feels persistent pressure to deliver higher performance, higher functionality, smaller size, lower power consumption, and
lower cost synthesizer designs. What
parameters are the most important?
64
High Frequency Electronics
Figure 11 · Direct analog synthesizer concept.
Although the answer strictly depends
on a particular application, frequency
coverage, resolution, spectral purity,
and switching speed require most of
the designer’s effort as illustrated in
Figure 10. The ideal synthesizer
should be preferably broadband with
a fine frequency resolution that
allows addressing a bigger number of
potential applications. On other hand,
the phase noise and spurious are even
more important parameters since
they determine the ultimate performance of a microwave system driven
by the synthesizer. However, the
major technology challenge is in
increasing the synthesizer tuning
speed as dictated by the ongoing
increase of the data rates of modern
microwave systems. The time spent
by the synthesizer jumping between
the frequencies becomes more and
more valuable since it cannot be used
for data processing. While many
microwave systems still work adequately with millisecond switching
speed, new equipment demands
microsecond operation together with
similar performance (phase noise,
spurious) of the low speed designs [2,
3]. Obviously, this presents serious
design difficulties and trade-offs.
Another challenge is cost reduction.
Although it is considered to be a
“standard” requirement, it drastically
narrows the designer’s choices. These
particular requirements—fast switching speed, excellent spectral purity,
and low cost—are the key drivers in
the development of new frequency
synthesizers.
The synthesizer characteristics
heavily depend on a particular technology. While reviewing traditional
frequency synthesizer architectures,
we specifically address the current
technology trend toward increasing
the synthesizer tuning speed,
improving the spectrum purity as
well as reducing its complexity and
cost. The main architectures along
with their characteristics and tradeoffs are described below.
Direct Analog Synthesizers
The direct analog synthesizer is
today's most advanced technique
offering unprecedented speed and
phase noise performance [6, 7]. The
desired signal is obtained by mixing
base
frequencies
followed
by
switched filters as depicted in Figure
11. The base frequencies can be
extracted from low-frequency (crystal, SAW) or high-frequency (CRO,
DRO, metal cavity, sapphire, etc.)
oscillators by frequency multiplication, division, or phase locking.
The key advantage of the direct
analog technique is extremely fast
switching speed, ranging from microto nanoseconds. Another distinct
advantage is the ability to generate
very low phase noise output due to
the usage of the components (e.g.,
mixers) with negligibly low residual
noise in comparison with the base
frequency sources. Thus, the direct
Figure 12 · Direct analog synthsizer with extended coverage.
Figure 13 · Direct digital synthsizer (DDS).
analog synthesizer phase noise mainly depends on the noise of the available reference sources and can be
potentially very low.
The main disadvantage of the
indicated topology is limited frequency coverage and step size. In our
example (Figure 11) only eighteen
output frequencies can be generated
even by utilizing both mixer sidebands. The number of output frequencies can be increased by using a
higher number of base frequencies
and/or mixer stages as shown in
Figure 12. However, this rapidly
increases the design complexity and
overall component count.
Another serious problem is a large
amount of undesired mixing products
that have to be carefully planned and
filtered out. Special attention should
be paid to switched filter isolation
and leakages too. Although a large
variety of mixing and filtering organization schemes is possible, they
tend to be hardware intensive if a
small frequency step and wide coverage are required. Therefore, while
this approach offers excellent tuning
speed and phase noise characteristics, its usage is limited to applications where fairly high cost can be
tolerated.
Direct Digital Synthesizers
In contrast to traditional analog
concepts, direct digital synthesizers
(DDS) utilize digital processing to
construct an output signal waveform
from a base (clock) frequency [8, 9].
Initially, a digital representation of a
desired signal is created (Figure 13),
then it is reconstructed with a digital-to-analog converter (DAC) to a
sinusoidal or any other desired
shape. This process is extremely fast
(mainly limited by the digital control)
that results in very high switching
speeds, comparable with direct analog schemes. DDS also provides reasonably low phase noise even showing an improvement (limited by its
residual noise floor) over the phase
noise of the clock source itself.
However, the most valuable DDS feature is its exceptionally fine frequency resolution, which is determined by
the length of the DDS phase accumu-
Figure 14 · DDS output spectrum.
lator. Sub-Hz levels are easily
achieved.
The main disadvantages are limited usable bandwidth and inadequate
spurious performance. While DDS
starts working from nearly DC, its
highest frequency is limited by the
Nyquist criteria to within one half of
the clock frequency. Moreover, a practical design requires an output lowpass filter for reconstructing the signal waveform, which further decreases the highest operation frequency to
about 40% of the clock signal. Another
serious problem is a high spurious
content (Figure 14) due to quantization and DAC conversion errors,
which generally prohibits direct multiplication of the DDS output.
Due to the mentioned bandwidth
and spurious limitations, the DDS
technique alone is rarely utilized at
microwave frequencies. Rather DDS
is used as a fine frequency resolution
block in direct analog and indirect
architectures.
Indirect Synthesizers
Indirect frequency synthesizers
utilize phase-lock loop (PLL) techniques offering smaller step size and
lower complexity in comparison with
direct analog schemes [10-22]. A typical single-loop PLL synthesizer
includes a tunable voltage-controlled
oscillator (VCO) generating a signal
that is fed back to a phase detector
through a frequency divider with a
variable frequency division ratio N as
May 2008
65
High Frequency Design
SYNTHESIZER DESIGN
Figure 16 · PLL phase noise.
Figure 15 · PLL block diagram and noise sources.
shown in Figure 15. The other input
of the phase detector is a reference
signal equal to a desirable step size.
Also, the reference frequency can be
divided down by another divider to
reduce the step size. The phase detector compares the signals at both
inputs and generates an error voltage, which following filtering and
amplification, slews the frequency of
the VCO to the lock frequency given
by FOUT = FPD × N, where FPD is the
comparison frequency at the phase
detector input.
The major advantages of this
scheme are reduced levels of spurious
signals owing to the low-pass filter
action of the loop and much lower
level of complexity compared to the
direct analog synthesizers. The main
disadvantages are longer frequency
switching time (which is inversely
proportional to the loop bandwidth
and consequently step size) and considerably higher phase noise in comparison with direct analog techniques.
The synthesizer noise outside the
PLL filter bandwidth is mainly
determined by the VCO free-running
noise as shown in Fig. 16. The phase
noise within the loop filter bandwidth is given by £ = £PD + 20 log N,
where £PD is the cumulative phase
noise of the reference signal, phase
66
High Frequency Electronics
detector, reference and feedback
divider, loop filter and amplifier
referred to the phase detector input
(Fig. 15). Thus, the close-in phase
noise depends on the reference as
well residual noise of individual synthesizer components and is further
degraded by large division ratios
required to provide a high-frequency
output with a fine resolution.
The single-loop synthesizer’s
characteristics can be improved with
a number of techniques such as fractional-N as well as employing a frequency conversion (mixing) within
the synthesizer feedback path.
Although these solutions complicate
the synthesizer schematic, the complexity can be balanced to a high-performance and reasonably priced
design.
Next Month
This article will be continued in
the next issue, reviewing individual
components used in the synthesizer
design.
References
1.
J.
Browne,
“Frequency
Synthesizers Tune Communications
Systems,” Microwaves & RF, March
2006.
2. A. Chenakin, “Frequency
Synthesis: Current Solutions and
New Trends,” Microwave Journal,
May 2007.
3. J. Regazzi, and R. Gill “Signal
Generator Melds Speed With Low
Phase Noise,” Microwaves & RF,
October 2006.
4. M. Piloni, A. Milani, and M.
Baggioli, “A New Millimeter-wave
Synthesizer for Point to Point Radio
supporting High Data Rates using
Complex Modulation Formats,” 35th
European Microwave Conf. Proc.,
October 2005, pp. 229-232.
5. J. Browne, “Synthesizers
Squeeze Into Smaller Spaces,”
Microwaves & RF, March 2008.
6. V. Manassewitsch, Frequency
Synthesizers Theory and Design,
John Wiley & Sons, 1987.
7. Z. Galani and R. Campbell, “An
Overview of Frequency Synthesizers
for Radars,” IEEE Transactions on
Microwave Theory and Techniques,
vol. MTT-39, May 1991, pp. 782-790.
8. V. Kroupa, Direct Digital
Frequency Synthesizers, John Wiley
& Sons, 1998.
9. J. Vankka and K. Halonen,
Direct Digital Synthesizers: Theory,
Design and Applications, Springer,
2001.
10.
V.
Kroupa,
Frequency
Synthesis Theory, Design and
Applications, John Wiley & Sons,
1973.
11. U. Rohde, Microwave and
Wireless Synthesizers: Theory and
Design, John Wiley & Sons, 1997.
12. C. Vaucher, Architectures for
RF Frequency Synthesizers, Springer,
2002.
13. J. Crawford, Frequency
Synthesizer Design Handbook, Artech
House, 1994.
14. J. Klapper and J. Frankle,
Phased-locked
and
Frequency
Feedback Systems, John Wiley &
Sons, 1972.
15. W. Egan, Phase-Lock Basics,
John Wiley & Sons, 1998.
16. F. Gardner, Phaselock
Techniques, John Wiley & Sons, 2005.
17. W. Egan, Frequency Synthesis
by Phase Lock, John Wiley & Sons,
1999.
18. R. Best, Phase-Locked Loops—
Design, Simulation, and Applications, McGraw-Hill, 2003.
19. U. Rohde, Digital PLL
Frequency Synthesizers: Theory and
Design, Prentice Hall, 1982.
20. A. Blanchard, Phase-Locked
Loops: Application to Coherent
Receiver Design, John Wiley & Sons,
1976.
21. J. Crawford, Advanced PhaseLock Techniques, Artech House, 2007
22. V. Kroupa, Phase Lock Loops
and Frequency Synthesis, John Wiley
& Sons, 2003.
Author Information
Dr. Alexander Chenakin is the
Director of the Frequency Synthesis
Group at Phase Matrix, Inc.,
www.phasematrix.com. He earned
his degree from Kiev Polytechnic
Institute and has worked in a variety
of technical and managerial positions
around the world. He has led the
development of advanced products
for Celeritek (since acquired by
Teledyne), Nextek, Micro Lambda
Wireless, General Electronic Devices,
and other companies. In 2005 Dr.
Chenakin joined Phase Matrix, Inc.,
where he oversees the development
of advanced frequency synthesizer
products for test and measurement
applications. He is an invited lector
for the 2008 IEEE International
Frequency Control Symposium tutorials. He can be reached by telephone
at 408-954-6409 or by e-mail at
achenakin@phasematrix.com.
Editor’s Note—Readers are reminded
that all technical articles are included in the Archives section of our web
site: www.highfrequencyelectronics.
com. PDF versions of articles are
placed in the Archives approximately
one month after they are published in
the printed and online editions of
High Frequency Electronics.
May 2008
67
From June 2008 High Frequency Electronics
Copyright © Summit Technical Media, LLC
High Frequency Design
SYNTHESIZER DESIGN
Building a Microwave
Frequency Synthesizer—
Part 2: Component Selection
By Alexander Chenakin
Phase Matrix, Inc.
A
s discussed in the
previous article, a
frequency synthesizer can be thought of as
a black box containing
various components (e.g.,
oscillators, phase detectors, frequency dividers,
multipliers, mixers, amplifiers, etc.), which
being properly connected, translate an input
reference signal to a number of output frequencies. The synthesizer implementation as
well as its ultimate performance depends
heavily on characteristics of the individual
components used in the design. Although
there is no set definition for the term “components” (they can be actually complex conectorized modules), in this article we will mostly
refer them as surface-mount parts, which can
be placed on a printed circuit board. The characteristics and behavior of the main synthesizer parts are reviewed from the perspective
of their use in practical synthesizer designs.
This series of articles
continues with a review of
individual components from
the perspective of their
practical use in microwave
frequency synthesizers
Reference Oscillator
A reference oscillator is one of the most
important parts that defines stability and
phase noise characteristics of frequency synthesizer. Various reference oscillator schemes
are possible as shown in Figure 17. A 10 MHz
temperature-compensated crystal oscillator
(TCXO) provides low size and cost benefits for
low- to moderate-performance applications.
Better stability and noise characteristics are
achieved by using an oven-compensated crystal oscillator (OCXO), but this is a more
expensive and bulky part with a higher power
consumption. It is worth mentioning, that
using a higher frequency OCXO (e.g., 100
18
High Frequency Electronics
Figure 17 · Some common reference frequency generation schemes.
MHz instead of 10 MHz) can potentially result
in a better synthesizer noise. There is a comparable noise floor for both parts, but the high
frequency reference requires a significantly
lower overall multiplication factor.
Even better phase noise performance at
higher frequency offsets (100 kHz and above)
can be obtained with additional low-noise
oscillators (e.g., SAW, CRO, or DRO) locked to
the main OCXO. The chain of oscillators
(which can include two or even more parts)
provides the lowest phase noise profile at any
frequency offset and can be used in high-end
synthesizer designs. The high-frequency oscillators are usually purchased parts, although,
they can be built as a part of the synthesizer
design to minimize the overall size and cost.
However, building a low-noise microwave
oscillator (e.g. a DRO) with adequate phase
noise performance is not a trivial task; it
requires careful design and optimization.
The phase noise behavior of a microwave
oscillator (shown conceptually in Figure 18)
High Frequency Design
SYNTHESIZER DESIGN
Figure 18 · Oscillator block diagram
Figure 19 · Oscillator phase noise characteristics.
oscillator phase noise behavior in the frequency offset
domain. Although the formula defines four basic frequency offset regions, in microwave oscillators the 1/f term is
usually ignored due to 1/f2 noise domination that leads to
a “classical” oscillator phase noise profile shown in Figure
19. For offset frequencies higher than the resonator half
bandwidth f0/2Q, the phase noise is mainly determined by
the available RF power level and active device thermal
noise. This region shows nearly flat response called “noise
floor.” For frequencies between the half bandwidth and
flicker corner frequency fa , the phase noise increases at
20 dB per decade. In the last region, where the flicker
noise dominates, the phase noise increases at 30 dB per
decade.
This graph gives simplified, but nevertheless, very
helpful visualization of the phase noise behavior as well
as some intuitive ideas how to reduce its appearance in
the oscillator output spectrum. Clearly, utilizing low flicker noise devices (e.g. silicon bipolar transistors) and
applying a high-Q frequency resonator technology are
effective, and commonly used ways to minimize the phase
noise. Alternatively, the entire noise curve can be shifted
down by increasing the oscillator signal-to-thermal noise
ratio. This can be practically achieved by maintaining a
higher power level in front of the resonator or/and reducing the active device noise factor, while the active device
gain should be set to its optimum value (determined be
the resonator coupling). Oscillator design methods and
phase noise reduction techniques are described in [28-32].
VCO or YIG?
Figure 20 · A YIG resonator placed between poles of
an electromagnet.
has been extensively investigated [23-27] and can be represented as follows:
where: G is active device gain, F is active device noise factor, k is Boltzman's constant, T is temperature, P is RF
power applied to the resonator, Q is resonator loaded Qfactor, f0 is oscillation frequency, fa is active device flicker
corner frequency, f is offset frequency. This expression is
essentially a modified Leeson’s equation that depicts the
20
High Frequency Electronics
Historically, high-performance PLL synthesizers have
relied on YIG-oscillators featuring broadband operation
and excellent phase noise characteristics. The YIG is an
acronym for yittrium iron garnet, a ferrite material that
displays a unique, high-Q frequency resonance characteristic when exposed to a magnetic field [33-37]. The YIG
resonator represents a small (8-20 mils in diameter)
sphere placed between two poles of cylindrically reentrant electromagnet and coupled with small wire loops
(Fig. 20). Frequency tuning is possible since the resonant
frequency of the spherical YIG resonator in uniform magnetic field is a function of the magnetic field strength. The
basic relationship between the resonant frequency f and
magnetic field strength H is given by: f = g H, where: g =
2.8 MHz/Oe is a physical constant called gyromagnetic
ratio. Therefore, the resonant frequency is in direct proportion to the magnetic field, which can be controlled by
changing DC current injected into the electromagnet tuning coil. Practical usable frequency range of pure YIG resonators lies between 2 and 50 GHz. While the higher frequency is mainly limited by the magnet saturation and
high power dissipation, lower limit is governed by the YIG
saturation magnetization. Lower operating frequencies (a
High Frequency Design
SYNTHESIZER DESIGN
few hundred MHz) are obtainable adding special dopes
(such as gadolinium) that, however, degrades the Q-characteristics.
The YIG resonators offer a relatively high Q (greater
than 4,000 at 10 GHz) that results in low phase noise performance. The YIG oscillators also feature very linear
(and repeatable) tuning characteristics that simplify the
synthesizer coarse tuning algorithm in multiloop
schemes. The main disadvantages are high power consumption, large size, high cost, and especially low tuning
speed due to high inductance of the tuning coil. Typical
achievable switching time is in a milliseconds range.
An alternative solution is a voltage-controlled oscillator (VCO) based on either lumped LC or distributed
microstrip resonators. Unfortunately, Q-factors of these
resonators are not so high; typical values are between a
few tens and few hundreds dependent on a particular
technology and tuning range. The frequency tuning is
achieved using varactor diodes, whose capacitance
depends on the applied tuning voltage. Unlike YIGs the
VCOs are extremely fast; microseconds operation is easily achieved. VCOs are currently available as tiny ICs,
whose size, power consumption and cost is negligible in
comparison with the YIG devices. However, the noise performance is considerably worse because of the lower Q of
the utilized resonators (which is further degraded by the
varactor diodes).
What technology is more preferable? The VCO clearly
dominates in low-cost, low- to moderate-performance
designs. However, for high-performance, broadband, lownoise applications (e.g., test and measurement) the
answer is not so obvious. YIG-based solutions are usually
simpler since the YIG-oscillator can forgive and mask
many design imperfections. One can relatively easy
achieve respectable phase noise performance with a simple single or dual-loop PLL by locking the YIG with a 10
kHz loop bandwidth and relying on its free-running noise
at higher frequency offsets. Obtaining comparable noise
performance with a VCO is much more challenging task
since the designer can only rely on the reference oscillator and PLL characteristics. At a 100 MHz output frequency, today’s commercial OCXOs perform at –160 to
–176 dBc/Hz at 20 to 100 kHz offset. These numbers can
be potentially translated to –120 to –136 dBc/Hz at a 10
GHz output. This theoretical performance corresponds to
or even exceeds the performance of the best YIG oscillators at the same offset frequencies. However, it is very
hard (if possible at all) to provide such an ideal translation since some noise degradation always occurs. Thus,
achieving YIG-comparable noise characteristics for a
VCO-based design is not a trivial task that calls for
advanced multiloop solutions and also requires a great
deal of effort to treat various “secondary” effects (e.g. voltage regulator noise, etc.). Nevertheless, the current tech22
High Frequency Electronics
Figure 21 · Analog regenerative divider concept.
Figure 22 · Divider output spectrum.
nology trend toward faster tuning and lower cost puts the
VCO in a better position for many practical scenarios.
Frequency Multipliers
Frequency multipliers are used to multiply reference
signals or to extend synthesizer operating frequency
bands. The device behavior and practical implementation
is very well treated in [6, 17, 38]. It should be highlighted
that a frequency- modulated signal is affected by the frequency multiplication process; i.e., phase noise and PM
spurs are degraded at 20logN rate, where N is the multiplication factor. Thus, the designer’s primary concern is to
avoid any extra degradation above the baseline of 20logN.
From this point of view, passive, diode-based solutions are
obviously preferred.
Frequency Dividers
A frequency divider is an essential part in a PLL synthesizer. It works in the exact opposite way that multiplier does, i.e., it brings phase noise and spurious improvement at the same 20logN rate. Digital dividers (e.g., counters) are the most commonly used devices. The residual
noise is probably the main concern since the divided sig-
High Frequency Design
SYNTHESIZER DESIGN
[38]. Similar to frequency multipliers,
passive (diode-based) solutions are
obviously preferable.
Phase Detectors
Figure 23 · Spur propagation through the signal chain.
Figure 24
detector.
·
Sampling phase
Figure 25
detector.
nal can easily hit into the divider
noise floor. On the other hand, analog
dividers (e.g. a regenerative scheme
shown in Figure 21) provide the best
noise performance but are rarely
used due to their narrowband behavior as well as sensitivity to circuit
parameters and signal level [39-41].
It is worth mentioning that the
digital frequency divider tends to
suppress even harmonics and accents
odd products as shown in Figure 22.
This is simply because the output of a
digital counter is a square-wave signal that ideally contains odd harmonics only. This feature can be utilized
to obtain fraction frequency multiplication and division coefficients (e.g.,
3/2, 3/4, 5/4, etc.) that can be desirable in certain cases.
·
Digital phase-frequency
Mixers
Mixers are utilized in direct analog architectures as well as indirect
schemes where frequency offsetting
(mixing) is involved. In contrast to
frequency dividers and multipliers,
an ideal mixer provides a frequency
shift without disturbing signal spurious and phase noise characteristics.
A propagation of an FM-modulated
signal with –60 dBc spurious level
through a hypothetical, ideal multiplier-mixer-divider chain is illustrated in Figure 23 (it assumes that the
signal has a pure close-in PM spur;
practical scenarios are usually more
complicated since AM-to-PM conversion and other effects can take place).
Mixers are available in IC form and
can be also built from discrete parts
A phase detector compares two
signals and generates a voltage,
which is a measure of the phase difference between the signals [17]. The
phase detector residual noise is one
of the key parameter that affects the
performance of a PLL synthesizer.
From this point of view, a balanced
mixer can be a good candidate for
low-noise designs, especially if a high
reference signal is used. A harmonic
(sampling) mixer can be used as
phase detector as well. It combines
an SRD multiplier and mixing diodes
in a common package (Figure 24)
that leads to considerable reduction
in synthesizer component count. It is
worth mentioning, however, the sampling detector is very sensitive to circuit parameters; making one work
properly is not trivial. The main disadvantages of the mixer-based phase
detectors are relatively high undesired signals (e.g. reference harmonics and DC offset) and initial frequency acquisition problem when the
PLL is out of lock.
A digital phase-frequency detector is a very popular and frequently
used alternative since it provides a
frequency-sensitive signal to aid
acquisition. The detector can be constructed from discrete logic components as shown in Figure 25; it is also
available in IC form (usually with an
integrated charge-pump circuit). The
main disadvantage of digital detectors is a higher residual noise in comparison with analog, mixer-based
parts.
Integrated PLL ICs
Figure 26 · Simplified depiction of integrated PLL functions on an IC.
24
High Frequency Electronics
Some vendors (e.g., Analog
Devices, National Semiconductor and
others) provide fully integrated ICs
containing all necessary components
required to build a whole synthesizer
(Figure 26). A nice example is
ADF4106 PLL IC from Analog
lines in the assembly shown in
Figure 27. The advantages of using
printed components are obviously
their low cost (just the PCB material
itself) and more predictable frequency response due to the absence of
package parasitics effects. The main
disadvantage is that more “real
estate” is required for some compo-
Figure 27
assembly.
·
nents in comparison with packaged
versions. And finally, the simplest but
very important element of any
microwave design is a 50-ohm transmission line used to connect the mentioned above individual parts. The
transmission line impedance depends
on the line width as well as the thickness and dielectric constant of the
Example of a PCB
Devices, which includes a digital
phase detector with an integrated
charge pump, RF and reference
dividers, lock detector, and other circuits. All division coefficients can be
programmed through a built-in 3wire serial interface (clock, data, and
chip select lines). The user can also
program charge pump current (to
adjust PLL bandwidth), change
phase detector polarity (this feature
can be very helpful if a frequency
mixing employed), monitor frequency
lock, or access some internal signals.
The IC allows building a simple single-loop PLL synthesizer or can be
used in more complex schemes.
Other synthesizer-oriented ICs
may include more phase detector/
divider sets to build a dual-loop synthesizer, fractional-N dividers, DDS,
parallel interface for faster control,
on-chip memory, etc.
Other Components
Depending on a particular architecture, frequency synthesizers can
include many other components both
active (e.g., amplifiers, switches,
attenuators, phase shifters, etc.) and
passive (e.g., resistors, capacitors,
inductors, transformers, fixed attenuators, power splitters, couplers, filters, etc.) available in surface-mount
packages.
Many passive components can
also be printed directly on a PCB,
such as the coupler and transmission
Get info at www.HFeLink.com
High Frequency Design
SYNTHESIZER DESIGN
utilized PCB material. FR-4 works well at relatively low
frequencies (a few GHz), while lower loss materials (such
as Rogers 4003C) are preferable at higher frequencies.
Also, it si preferred that a solder mask should be removed
from high-frequency elements since it introduces extra
loss and slightly changes the impedance. It is also worth
mentioning that all packaged parts introduce discontinuity effects, which should be minimized (or compensated)
to avoid any unexpected issues and provide a robust and
reproducible design.
This article will be continued in the next issue, demonstrating the most important aspects of the synthesizer
design process. Part 3 will show all design stages from a
general block diagram to schematic, PCB layout, assembly, troubleshooting, testing, and documentation release. A
simple, single-loop PLL architecture is used to discuss all
aspects of the design process.
References
23. D. Leeson, “A Simple Model of Feedback Oscillator
Noise Spectrum,” IEEE Proc. Letters, vol. 54, Feb. 1966,
pp. 329-330.
24. G. Sauvage, “Phase Noise in Oscillators: A
Mathematical Analysis of Leeson’s Model,” IEEE Trans.
on Instrumentation and Measurement, vol. 26, Dec. 1977,
pp. 408-410.
25. B. Parzen, “Clarification and a Generalized
Restatement of Leeson’s Oscillator Noise Model,” IEEE
Int. Frequency Control Symposium Proc., June 1988, pp.
348-351.
26. F. Dacus, J. Van Niekerk, and S. Bible, “Tracking
Phase Noise in Short-Range Radios,” Microwaves & RF,
March 2002, pp. 57-64.
27. E. Rubiola, “The Leeson Effect: Phase Noise in
Feedback Oscillators,” IEEE Int. Frequency Control
Symposium Tutorial, June 2006.
28. I. Bahl and P. Bhartia, Microwave Solid State
Circuit Design, Wiley, 2003.
29. U. Rohde, A. Podar, and G. Bock, The Design of
Modern Microwave Oscillators for Wireless Applications:
Theory and Optimization, Wiley, 2005.
30. J. Everard, “A Review of Low Noise Oscillator.
Theory and Design,” IEEE Int. Frequency Control
Symposium Proc., May 1997, pp. 909-918.
31. U. Rohde and A. Podar, “Noise Minimization
Techniques for RF and MW Signal Sources,” Microwave
Journal, Sept. 2007, pp. 136-162.
32. C. McNeilage, E. Ivanov, P. Stockwell, and J. Searls,
“Review of Feedback and Feedforward Noise Reduction
Techniques,” IEEE Int. Frequency Control Symposium
Proc., May 1998, pp. 146-155.
33. R. Trew, “Design theory for broad-band YIG-tuned
FET oscillators,” IEEE Trans. on Microwave Theory and
Techniques, vol. MTT-27, Jan. 1979, pp. 8-14.
26
High Frequency Electronics
34. T. Heyboer and F. Emery, “YIG-tuned GaAs FET
oscillators,” IEEE Int. Microwave Symposium Dig., June
1976, pp. 48-50.
35. J. Papp, “An 8-18 GHz YIG-Tuned FET Oscillator,”
IEEE Trans. on Microwave Theory and Techniques, vol.
MTT-28, July 1980, pp. 762-767.
36. C. Schiebold, “An Approach to Realizing MultiOctave Performance in GaAs YIG-Tuned Oscillators,”
IEEE Int. Microwave Symposium Dig., 1985, pp. 261-263.
37. A. Khanna and J. Buenrostro, “2-22 GHz Low
Phase Noise Silicon Bipolar YIG-Tuned Oscillator Using
Composite Feedback,” IEEE Int. Microwave Symposium
Dig., June 1992, pp. 1297-1299.
38. S. Maas, The RF and Microwave Circuit Design
Cookbook, Artech House, 1998.
39. R. Harrison, “Theory of Regenerative Frequency
Dividers Using Double Balanced Mixers,” Int. Microwave
Symposium Dig., June 1989, pp. 459-462.
40. E. Ferre-Pical and F. Walls, “Microwave
Regenerative Frequency Dividers with Low Phase Noise,”
IEEE Trans. on Ultrasonics, Ferroelectrics, and Frequency
Control, vol. 46, Jan. 1999, pp. 216-219.
41. A. Sen Gupta, J. Garcia Nava, and F. Walls,
“Conjugate Regenerative Dividers,” IEEE Trans. on
Ultrasonics, Ferroelectrics, and Frequency Control, vol. 51,
March 2004, pp. 271-276.
Author Information
Dr. Alexander Chenakin is the
Director of the Frequency Synthesis
Group at Phase Matrix, Inc.,
(www.phasematrix.com) where he
oversees the development of advanced
frequency synthesizer products for
test and measurement applications.
He earned his degree from Kiev
Polytechnic Institute and has worked in a variety of technical and managerial positions around the world. He has
led the development of advanced products for Celeritek,
Nextek, Micro Lambda Wireless, General Electronic
Devices, and other companies. Dr. Chenakin was a lecturer for the 2008 IEEE International Frequency Control
Symposium tutorials. He can be reached by phone at 408954-6409 or by e-mail at achenakin@phasematrix.com.
Visit the Archives
Readers are reminded that all technical articles are archived
and available at www.highfrequencyelectronics.com. Each
issue’s articles are placed in the Archives section of our Web
site one month after they appear in the printed and online
editions of High Frequency Electronics. This service makes it
easy for new subscribers to access past articles, or for readers
to send a link to colleagues who may not yet be subscribers.
From July 2008 High Frequency Electronics
Copyright © 2008 Summit Technical Media, LLC
High Frequency Design
SYNTHESIZER DESIGN
Building a Microwave
Frequency Synthesizer—
Part 3: From Sketch to Product
By Alexander Chenakin
Phase Matrix, Inc.
D
evelopment of a
new product usually starts from
an idea or concept, followed by several design
steps. In this article, a
simple single-loop PLL
example is used to demonstrate the most
important aspects of the design process,
beginning with a specification and block diagram, then proceeding to schematic, PCB layout, assembly, troubleshooting, testing, and
documentation release.
This series continues with a
step-by-step review of the
design sequence, from
basic diagram and specifications to production
The synthesizer should come in a connectorized metal box and be programmed to any
desired frequency within the indicated frequency range and 1 MHz step size using a personal computer. The 10 MHz reference is from
the customer’s own equipment.
Obviously, the specification is not complete; however, we have enough information to
start defining the synthesizer architecture
and selecting its main components. Other
parameters can be marked as TBD (to be
determined)—that gives us some flexibility at
this stage, and those parameters can be analyzed and negotiated later in the process.
Specification
A specification is a set of requirements
that have to be met by a product. It can be
generated through market research identifying particular customer needs and market
demands. Alternatively, it can come from a
customer, sometimes in a form of a “wish list.”
The requirements are analyzed and then
gradually nailed down to a formal document
that establishes all parameters describing the
product. As an example, let’s consider a customer who needs a signal between 5 and 5.5
GHz to be used as a stimulus source for some
experiments. Although the requirements have
not been completely defined, some desirable
characteristics are as follows:
Frequency Range: 5.0-5.5 GHz
Resolution: 1 MHz
Tuning Speed: 1 msec
Output Power: +7 dBm
Spurious: –60 dBc
Harmonics: –25 dBc
Phase Noise: –90 dBc/Hz at 100 kHz offset
External Reference Frequency: 10 MHz
18
High Frequency Electronics
Block Diagram
A block diagram is a high-level pictorial
model of a product that helps to understand
the overall design concept. Taking a quick look
at the indicated above parameters, one can
conclude that the spec is straightforward: a
single-loop PLL should probably do the job.
What components should be used? First of
all we need a VCO. Hittite’s HMC430LP4
seems to be an excellent candidate. It provides
the desired frequency coverage and is available in a low-cost, surface-mount form.
Moreover, we can also rely on the VCO freerunning noise at 100 kHz frequency offset,
which is better than –100 dBc/Hz [42]. We also
need PLL components (phased detector,
dividers) to lock the VCO. Analog Devices’
ADF4106 should be a perfect choice. The part
supports the required frequency range and
includes a digital phase-frequency detector,
both RF and reference dividers as well as lock
detector circuitry [43]. All division coefficients
are programmed through a built-in 3-wire
serial interface. The part also allows program-
High Frequency Design
SYNTHESIZER DESIGN
Figure 28 · A simple block diagram sketch is the usual starting point for
synthesizer design.
ming the phase detector charge pump
current to adjust PLL loop filter
bandwidth if required. This is an
especially useful feature for broad
bandwidth synthesizers, since the
VCO tuning sensitivity and the loop
division coefficients may change with
frequency.
Now we can draft a very simplified
block diagram sketch like the one
shown in Figure 28, which helps to
quickly estimate some key design
characteristics, such as phase noise,
loop bandwidth, and tuning speed.
According to the ADF4106 data
sheets, the effective phase detector
noise at 1 MHz comparison frequency
is about –159 dBc/Hz. Assuming that
PLL noise dominates (that means the
external reference noise is sufficiently
low), we can estimate the RF output
phase noise generated by the PLL
itself at –84 dBc/Hz. Since the VCO
free-running noise at 10 kHz frequency offset is worse, the PLL bandwidth
should be set slightly above 10 kHz
(let’s say 20 kHz) for optimal phase
noise performance. The tuning speed
corresponding to this loop bandwidth
is in the order of 200 microseconds for
a 45-degree phase margin. This
should be verified with your choice of
simulation methods.
Now, it is probably a good time to
contact the customer again to discuss
the characteristics we can potentially
achieve (some margin should be
added, of course) and clarify other
parameters such as external reference phase noise. Then, we come back
and proceed with the block diagram.
What else are we missing? The
VCO tuning curve indicates that we
need about 7.5V to steer the VCO to
5.5 GHz. However, the maximum
voltage provided by the phase detector output is only 5.5V. Thus, an operational amplifier (such as AD820 by
Analog Devices) should be added to
scale up the charge pump output.
Moreover, we also need to boost the
VCO RF output in order to get the
Figure 29 · A block diagram with additional operating information.
20
High Frequency Electronics
desired output power. A number of
parts can be used; Hittite’s
HMC476MP86 gain block should
work sufficiently well. Thus, we can
further refine our block diagram by
checking all the system parameters
and adding more parts as necessary.
A good block diagram also includes
extra information (e.g., signal frequencies and power levels, bias conditions, etc.) required to understand
the circuit operation; an example is
shown in Figure 29.
Creating a Schematic
The next step is to create a
schematic, which is a detailed circuit
diagram that shows all individual
components as graphic symbols as
well as connections between the components (Figure 30). The schematic is
accomplished with specialized software (e.g., OrCAD) that allows creating a library of component symbols
for use in schematic entry. In contrast
to the block diagram, the schematic
represents an exact model of the
desired product; thus, all the details
(such as component values) should be
thoroughly checked and optimized.
Although the schematic shown in
Figure 30 will probably work (after
some manipulations), it is too far
from perfect. What can be improved?
Let’s examine the RF signal path
first. The RF output power looks too
low, since some power will be lost in
the output connector. On the other
hand, we can save quite a bit of the
energy we are losing in the resistive
splitter (6 dB loss). Since the
ADF4106 RF divider only needs –15
dBm signal to operate, putting a
directional coupler (see Fig. 31) is a
better alternative. It properly balances the RF power budget and also
provides isolation between the synthesizer output and RF divider path.
This helps to reduce undesired subharmonics products, which are generated by the dividers and reflected
back to the RF output. From this
point of view, the coupler should be
preferably placed after the RF ampli-
High Frequency Design
SYNTHESIZER DESIGN
Figure 30 · Example of a basic schematic diagram.
fier to avoid unnecessary amplification of these products. It is worth
mentioning, that the coupler can be
printed on a PCB, which can lead to
an overall component count reduction. Further subharmonic reduction
is achieved by putting a surfacemount high-pass filter such as
HFCN-4600+ manufactured by MiniCircuits. For very tight spurious
requirements, an additional RF
amplifier can be inserted into the RF
divider path to increase the isolation.
After removing the resistive power
splitter we get more power in front of
the amplifier, which puts it in a saturation regime. This stabilizes its output level and improves the output
power flatness. On the other hand,
keeping the amplifier oversaturated
is not a good idea since it results in
higher current consumption and can
also reduce the device lifetime.
Putting a small fixed attenuator
between the VCO and amplifier
allows us to keep the amplifier slightly compressed (but not oversaturated)
and also provides a better termination for the VCO output. We can also
add an attenuator at the amplifier
output that improves the synthesizer
output match. Another potential problem is the output harmonics generated by the VCO and amplifier. The
indicated spec of –25 dBc can be handled by putting a low-pass filter at the
amplifier output. The filter can be a
purchased surface-mount part (such
as LFCN-7200+ from Mini-Circuits)
or can be printed on the board.
The next part to focus on is the
ADF4106 PLL IC. The reference
input exhibits very high impedance
and should work well with squarewave CMOS signals. However, an
additional resistor together with DC
blocking caps is required to work in a
50-ohm environment. In contrast, the
ADF4106 RF input looks fine, since
its impedance at the indicated fre-
Figure 31 · Schematic diagram, with locations noted for performance optimization.
22
High Frequency Electronics
High Frequency Design
SYNTHESIZER DESIGN
From Schematic to PCB
Figure 32 · Common PCB layer arrangements.
quencies is close enough to 50 ohms.
Nevertheless, additional matching
components may be needed at lower
frequencies or to achieve better highpass filter termination.
The major area of optimization is
the loop filter. The configuration shown
in Figure 30 is probably not the best
since the operational amplifier boosts
both the phase detector output DC
voltage and the noise. Thus, the amplifier gain should be optimized. There
are many different types of loop filters
well described in [10-22]; an operational amplifier integrator can be a
better choice. Although the 45-degree
phase margin provides the best trade-
off between the stability, noise picking
and tuning speed, a better (flatter)
noise performance can be achieved by
increasing the phase margin to higher
numbers. The penalty is a slower tuning speed that, perhaps, is not a problem at all. The final optimization
should be done after clarifying all the
key specifications, such as the required
phase noise and tuning speed, available reference noise, etc. It is worth
mentioning that this optimization
could be done earlier at the block diagram stage. However, for more complex designs it is usually a back-andforward process due to the number of
trade-offs and possible solutions.
Once we have refined the
schematic, it is time to turn it into a
printed circuit board. The PCB layout
is the physical form of the circuit;
thus, all connections are derived from
the schematic. There are many computer-added PCB design packages
tied to a schematic. Most of the job is
performed automatically, although,
the best results for high-frequency
designs are still achieved with a certain amount of manual placement
and routing in order to control various signal interactions effects.
A typical PCB design uses surfacemount components soldered flush to
PCB pads. The components and connecting traces are preferably placed
on the top of the board, while the bottom layer is used as a ground. This
arrangement allows natural 50-ohm
microstrip environment (Figure 32);
the RF trace width is defined by the
board material thickness and its
dielectric constant. A multilayer
board can be used for more complex
designs such as multiloop synthesizers. The board is constructed as a
sandwich where each layer is dedicated for specific signals as shown in
Figure 32. Connections between layers are performed with metalized via
holes. The components can also be
mounted on both sides of a PCB to
utilize the available space more efficiently.
A solder mask is normally put on
a PCB exposing only the areas to be
soldered. It should be, however,
removed from certain high-frequency
areas, too, since it introduces extra
loss and slightly changes the
impedance. The PCB is also
silkscreened with component identification lettering and some other information, which assists people to
assemble and troubleshoot the board.
Housing Design
The PCB assembly is placed into a
metal housing, which is usually made
from an aluminum alloy with a proper coating. The synthesizer connects
to the outside world through RF connectors (such as SMA, K, etc.), while
screw-in EMI feed thrus can be used
to bring the external voltages. A certain effort should be applied to minimize discontinuity effects at the RF
connector transition. For a singlelayer board the design is pretty
straightforward since the RF ground
is in direct contact with the housing
floor as shown in Figure 33. For a
multilayer board, however, the RF
ground is in-between the layers and is
connected to the bottom layer through
multiple via holes. This connection
represents a relatively high inductance in the ground path that can
affect the performance at high frequencies. A better grounding can be
achieved through the top layer (e.g.,
using an edge-mount connector
shown in Fig. 34) due to a shorter distance between the RF ground plane
and connector body. From this point of
view, the upper level material should
be as thin as possible, while other layers can be accommodated using a
Figure 33 · RF connector interface
example.
Figure 34 · Top layer grounding
with metal and via holes.
thicker, lower-frequency material.
Using a coplanar waveguide transition is a good solution as well.
Control Software
To program the output frequency
and other parameters, synthesizers
require a control mechanism, which
can be implemented in many differ-
ent ways depending on a particular
application. Designing software for
complex microwave synthesizers can
be a challenging task, which is usually developed by a separate team. In
our case no internal controller is
required since the software resides in
an outside computer and is connected
through a PC interface. The control
High Frequency Design
SYNTHESIZER DESIGN
Moving to Production
Figure 35 · Amplifier failure
symptom, determined by
using circuit probes.
Figure 36 · RF test points aid in circuit troubleshooting.
algorithm is fairly simple and well
documented in the ADF4106 data
sheets [43].
Troubleshooting and Testing
Very few microwave synthesizer
designs work perfectly from the first
cut. More likely, they exhibit some
undesirable behavior and need troubleshooting. A basic principle in troubleshooting is to reproduce and isolate a particular problem. There is no
troubleshooting harder than fixing a
symptom that has more than one
cause. The process normally starts
from a visual inspection of a PCB
assembly to look for obvious construction flaws, followed by checking DC
bias for all active components. The
next step is to check the RF power
signal at the output, which should be
in expected limits. Otherwise, the RF
signal path is inspected by measuring
and comparing signal levels at the
individual components with an RF
probe. Although, the probe does not
provide accurate power reading, it can
give an idea if a component is functional. For example, measuring no
power difference (or even power drop)
between the amplifier input and output (Fig. 35) indicates that the part is
probably damaged. It is also a good
idea to include designated RF test
points at critical locations, using
miniature coaxial connectors, which
can be connected or disconnected as
required (Figure 36).
The PLL debugging is greatly simplified since the ADF4106 IC provides
26
High Frequency Electronics
a programmable access to some internal points such as RF and reference
divider outputs. Measuring output
frequencies at these points (which
should be equal to the desired step
size) can give an idea on what path is
functioning. You can also check how
the charge pump output responds on
a division coefficient change. No
response indicates a possible phase
detector failure; otherwise, the problem can relate to the operational
amplifier or VCO parts. The VCO can
be checked manually by connecting
its tuning port to an external DC supply; the VCO output frequency should
follow the control voltage.
Some of the most difficult troubleshooting issues relate to symptoms that are intermittent. This often
is the result of components that are
thermally sensitive. Compressed air
can be used to cool down specific
spots on a PCB, while a heat gun
raises the temperatures, if necessary.
The main idea is to reproduce a problem and then find and replace a part
responsible for the failure. Besides
fixing the damaged parts, some component adjustments or tuning may be
required, for example, with printed
filters. A PLL loop filter is another
sensitive area that needs further
optimizing. Finally, all necessary
parameters are measured, and various other specific functional and performance tests are conducted as well.
The process is accomplished with a
detailed failure analysis and possible
design changes.
At a certain point all necessary
design documents (e.g., specifications, block diagram, schematic, PCB
and mechanical drawings, assembly
drawing and bill of materials, test
procedure, etc.) should be properly
documented and released. All further
changes are implemented as an ECO
(engineering change order) in accordance with a specific company’s rules
and standards. A good documentation
system is vital for quality manufacturing of any product. To test the
product manufacturability, a pilot
run of a greater number of units (typically 10 to 25) follows the prototyping stage. It is an opportunity to
evaluate the reproducibility of the
design as well as documentation completeness. Following the pilot run
there will likely be additional small
changes until the design develops
into a stable product.
This series will be continued in the
next issue, showing how to improve
the main synthesizer characteristics.
Synthesizer design trade-offs and
various solutions will be discussed.
Past articles are available online at:
www.highfrequencyelectronics.com
References
42. HMC430LP4 data sheets,
available at www.hittite.com
43. ADF4106 data sheets, available at www.analog.com
Author Information
Dr. Alexander
Chenakin is the
Director of the
F r e q u e n c y
Synthesis Group
at Phase Matrix,
Inc., (www.phasematrix.com). He
earned his degree from Kiev
Polytechnic Institute and has worked
in a variety of technical and managerial positions around the world.
He can be reached by telephone at
408-954-6409 or by e-mail at
achenakin@phasematrix.com.
From August 2008 High Frequency Electronics
Copyright © Summit Technical Media, LLC
High Frequency Design
SYNTHESIZER DESIGN
Building a Microwave
Frequency Synthesizer—
Part 4: Improving Performance
By Alexander Chenakin
Phase Matrix, Inc.
T
his series of articles continues with
an analysis of PLL
synthesizer design tradeoffs. The simple singleloop PLL synthesizer
approach exhibits various
limitations
and
trade-offs. Thus, achieving a good performance
combination (e.g., small step size and low
phase noise) usually requires more sophisticated solutions. The common design trade-offs
as well as various methods to improve synthesizer characteristics are discussed.
In this article, the author
examines design alternatives to achieve different
performance objectives
such as fast switching
speed or fine resolution
PLL Design Trade-offs
The main PLL synthesizer parameters,
such as output frequency range, step size,
switching speed, spurious, and phase noise
heavily depend on each other. First of all, the
synthesizer switching speed is a function of its
loop bandwidth, which is, in turn, defined by
the phase detector comparison frequency or
the step size. Thus, the smaller the step size,
the slower the switching speed. Trying to
increase the loop bandwidth may lead to higher reference spurs due to insufficient loop filter rejection. Clearly, increasing the phase
detector comparison frequency will benefit the
switching speed and spurious performance.
On the other hand, for a simple single-loop
PLL the phase detector frequency equals to
the frequency step size and, therefore, can not
be arbitrarily increased.
A simple solution to overcome this problem
is presented in Figure 37. The idea is to
increase both phase detector input and VCO
output frequencies by K times, and then bring
the synthesizer output frequency and step size
44
High Frequency Electronics
Figure 37 · A simple way to improve singleloop PLL performance.
down to desired numbers with an additional
divider. This scheme allows higher phase
detector comparison frequencies that lead to
improved performance, e.g., faster tuning
speed or better spur rejection. Besides, it can
potentially provide better phase noise characteristics too. Although the phase detector
noise normally exhibits 10logK degradation
with the phase detector comparison frequency
increase, this degradation will be offset by a
factor of 20logK by the output frequency
divider. Assuming that the phase detector
noise dominates (in certain cases) and the loop
division coefficient N remains unchanged, the
scheme will demonstrate 10logK overall noise
improvement.
Let’s step back to the general single-loop
PLL case (Fig. 15). The main impact on the
synthesizer performance is posted by large
division ratios required to provide a high-frequency output with a fine resolution. For
example, in order to get 10 GHz output with 1
MHz step size, the feedback divider ratio has
to be 10000 that corresponds to 80 dB phase
noise degradation. Moreover, programmable
dividers are usually not available at high frequencies, thus an additional fixed divider
(prescaler) is required. In this case the total
High Frequency Design
SYNTHESIZER DESIGN
Figure 38 · The fractional division
concept.
division ratio will increase by the
prescaler division coefficient resulting in further phase noise degradation. Furthermore, the discrete spurs
at multiples of the reference frequency tend to be proportional to the loop
division ratio that leads to spurious
degradation too. As a result, the simple single-loop schemes are only used
in low-performance applications.
Fractional-N Techniques
In the PLL example above we
assumed that the RF signal was
divided by integer numbers only.
Let’s come back to our example where
we need to synthesize some frequencies around 10 GHz with 1 MHz step
size, i.e., 10.000, 10.001, 10.002, etc.
Note, that we could get these numbers using 10 MHz reference if we
could set the loop division coefficient
to fractional numbers, i.e., 1000+0/10,
1000+1/10, 1000+2/10, etc. Thus, we
would be able to reduce the maximum loop division coefficient and use
a higher phase detector comparison
frequency that would benefit virtually all synthesizer parameters.
How fractional division coefficients can be realized? In general it is
possible by alternating two dividers
(Fig. 38) and averaging the output
frequency over a certain period of
Figure 39 · Using DDS as a reference.
46
High Frequency Electronics
time. Another way to look at this process is to calculate the number of
pulses delivered by this circuit for a
given time interval, let’s say 1 sec.
Obviously, the total number of pulses
depends how the processing time is
split between these two dividers.
Thus, the average division coefficient
will be between 2 and 3 depending on
how many pulses are processed by
each divider.
There are a number of fractional
divider implementation techniques,
which are well described in [16-17].
However, for practical purpose, the
fractional dividers are usually purchased parts, which are also integrated with phase detector, reference
divider and other circuitry. A good
example is a family of fractional-N
PLL ICs from Analog Devices, which
are pin-to-pin compatible with integer PLL ICs discussed in the previous part.
The main disadvantage of the
fractional-N technique is excessive
spurious levels due to phase errors
inherent to the fractional division
mechanism. Nevertheless, it is a simple and elegant solution for many
applications where spurious performance is not the main concern.
Using a DDS
The DDS is another very effective
solution to provide a very fine frequency resolution without a common
penalty of the phase detector frequency reduction. The DDS is essentially a fractional divider that can be
inserted into the reference or RF
feedback path as shown in Figure 39
and Figure 40, respectively. In the
first case, the DDS provides a fine-
resolution and relatively high-frequency reference signal that allows
reducing the loop division coefficient
for a given step size. Moreover, since
the DDS output can be programmed
in wide limits, the loop division coefficient can be kept unchanged. Thus,
a programmable divider is not
required. The configuration shown in
Figure 40 employs DDS as a fractional divider, whose division coefficient
is set by DDS tuning command. An
additional divider may be required in
front of the DDS to keep its input
clock frequency within specified limits. In both cases, the overall loop
division coefficient is defined by the
ratio between the VCO output and
phase detector input frequencies.
Special attention should be paid
to the DDS spurious signals, which
are degraded by the loop division
ratio for both configurations. A number of solutions (both hardware and
software based) can be utilized to
reduce the DDS spurs. Hardware
techniques are usually based on
upconversion of the DDS signal followed by a frequency divider as
shown in Figure 41. Since the frequency mixing does not affect DDS
spurs (assuming that undesired
mixer products are properly filtered),
the circuit reduces the DDS spurious
content at 20 dB/decade rate inherent to the frequency division process.
Unfortunately, it also reduces the
output bandwidth, which may be a
limiting factor in certain cases. The
DDS bandwidth can be extended by
applying more LO frequencies and
filters as depicted in Figure 42 that,
however, results in a higher component count similar to the direct ana-
Figure 40 · Using DDS as a fractional divider.
High Frequency Design
SYNTHESIZER DESIGN
Figure 41 · DDS spur reduction.
Frequency Mixing
Figure 42 · DDS bandwidth extension.
log schemes.
On the other hand, software
techniques involve frequency planning to move DDS spurs in the frequency domain. These techniques
are based on the fact that DDS spur
location is a function of its output
and clock frequencies. Therefore, for
a given output frequency one can
Figure 43 · DDS spur filtering.
48
High Frequency Electronics
move and then filter out an undesired spur by adjusting the DDS
input clock frequency and frequency
tuning command as shown in Figure
43. This technique can be easily
combined with PLL architectures,
which provide a variable clock
source as well as very efficient PLLbased filtering.
The synthesizer’s main characteristics can be dramatically improved
by employing a frequency conversion
(mixing) within the synthesizer feedback path [44] as shown in Figure 44.
The VCO output frequency is converted to a much lower frequency
with the aid of an offset frequency
source in order to minimize the maximum frequency division ratio. The
offset signal can be produced using
an additional PLL or a chain of frequency multipliers. An attractive
solution is a harmonic mixer that utilizes multiple harmonics created by a
built-in step recovery diode. This
approach usually leads to a shorter
bill of materials in comparison with
fundamental mixing schemes; however, it is more sensitive to circuit
parameters.
The offset signal can be generated
within the same PLL (Fig. 45) by
adding two programmable dividers at
the mixer terminals as suggested in
[45]. This scheme allows fractional
division coefficients that can lead to
the overall performance improvement.
One of the problems associated
with any frequency-mixing scheme is
a possible false lock due to undesired
mixing products. This type of failure
requires a sufficiently accurate
coarse-tuning mechanism. A digitalto-analog converter (DAC) may be
included to coarse-tune the VCO to
approximately the correct frequency
as shown in Figure 46. This acquisition aid requires linear (and repeat-
High Frequency Design
SYNTHESIZER DESIGN
Figure 44 · Frequency mixing within RF feedback path.
Figure 45 · Self-offset loop.
Figure 46 · Initial frequency acquisition.
Figure 47 · Dual-loop synthesizer example.
able) VCO tuning characteristics
over operating temperature range as
well as precise frequency calibration
to compensate the VCO temperature
drift. Moreover, DACs are usually too
noisy, adversely affecting the synthesizer phase noise performance if they
are not properly removed after the
initial
frequency
acquisition.
Another potential problem is due to
undesired mixer signals (e.g., LO
leakage, intermodulation products),
which can leak to the synthesizer
output. Thus, a certain effort is
required to provide required isolation between the mixer ports and the
synthesizer output.
Multiloop Synthesizers
The main disadvantage of the
simple frequency offset schemes is
limited
frequency
coverage.
Increasing the output frequency
range for a fixed offset signal leads to
a higher IF at the mixer output. This
requires a divider with a larger division coefficient that defeats the idea
of this method. The offset frequency
signal should preferably be as close
50
High Frequency Electronics
as possible to the VCO output frequency in order to keep the division
ratio at minimum. Thus, a variable
frequency offset signal is desired.
The variable offset signal can be
generated with another PLL as
depicted in Figure 47. What do we
gain with this approach? Let’s revise
again our need for a 1 MHz-step synthesizer operating between 9 and 10
GHz. The first PLL provides 9 to 10
GHz frequency coverage with a 100
MHz step size by varying the division
ratio N1 between 90 and 100. The
output of the first PLL is used as an
offset signal for the second loop to
keep the mixer output below 100
MHz. Thus, for the desired 1 MHz
step size, the maximum division ratio
for the second loop does not exceed
100 as well. The phase noise degradation for both loops (set by the maximum division ratio) does not exceed
40 dB versus 80 dB for the single-loop
alternative. Therefore, splitting the
design in two loops can potentially
result in overall 40 dB phase noise
improvement compared to the singleloop approach.
Greater phase noise improvement
(or smaller step sizes) can be
achieved using a larger number of
PLLs as shown in Figure 48. The
number of loops and frequency plan
depend on particular synthesizer
requirements (step size, phase noise,
etc.). Since there are a number of
choices for managing the individual
loop characteristics, the frequency
planning is not trivial; some scenarios are discussed in [10-22]. An original mathematical algorithm based on
Diophantine equations is described
in [47]. It worth mentioning, however,
that in many cases the synthesizer
architecture is also governed by
available components and their cost.
Thus, the designer’s experience and
intuition are probably the most
important factors in the synthesizer
development equation.
This series of articles will conclude
next
month
reviewing
advanced synthesizer solution. It will
discuss how to remove the YIG oscillator still preserving good phase
noise characteristics. Complex multiloop
synthesizers,
modulation
http://www.synergymwave.com.
47. P. Sotiriadis, “Diophantine
Frequency
Synthesis,”
IEEE
Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, vol.
53, Nov. 2006, pp. 1988-1998.
Author Information
Figure 48 · Multiloop synthesizer concept.
options, various platforms and interfaces will be also discussed.
References
44. D. Pedreira, J. Alonso, F. Perez
and C. Briso-Rodriguez, “High
Performance Offset Synthesizer,”
35th European Microwave Conf.
Proc., October 2005.
45. B. Sadowski, “A Self-offset
Phase-locked Loop,” Microwave
Journal, April 2008.
46. “Fractional-N Synthesizer,”
Application Note, available at
Dr. Alexander Chenakin is the
Director of the Frequency Synthesis
Group at Phase Matrix, Inc.,
(www.phasematrix.com) where he
oversees
the
development
of
advanced frequency synthesizer
products for test and measurement
applications. He earned his degree
from Kiev Polytechnic Institute and
has worked in a variety of technical
and managerial positions around the
world. He has led the development of
various products for Celeritek,
Nextek, Micro Lambda Wireless,
General Electronic Devices, and
other companies. His professional
achievements have been widely presented in professional magazines and
international
conferences.
Dr.
Chenakin also was a lecturer for the
2008 IEEE International Frequency
Control Symposium tutorials. He can
be reached by telephone at 408-9546409 or by e-mail at achenakin@
phasematrix.com.
August 2008
51
From September 2008 High Frequency Electronics
Copyright © 2008 Summit Technical Media, LLC
High Frequency Design
SYNTHESIZER DESIGN
Building a Microwave
Frequency Synthesizer—Part 5:
Advanced Techniques
By Alexander Chenakin
Phase Matrix, Inc.
T
his is the final article in a five-part
series on microwave frequency synthesizers. It concludes with a
review of advanced synthesizer solutions. Although synthesizers can
be found in virtually any
microwave system, test and measurement
(T&M) is probably the most challenging application that calls for advanced synthesizer techniques. This final article addresses some specific T&M requirements and possible solutions.
This series concludes with
notes on advanced design
options and features for
greater functionality, with
descriptions of their implementation in test and
measurement products
T&M Synthesizer Considerations
Broadband operation, very fine frequency
resolution, low spurious and low phase noise
are the key specifications for T&M applications. More recently a lot of interest has been
focused on fast frequency switching. This has
been motivated by a need for increased data
throughput of ATE systems, and the frequency agility demands of wide bandwidth
receivers and transmitters [2, 3]. Besides the
spectral purity and switching characteristics,
the T&M applications require extended functionality that include output power leveling
and control, frequency and power sweep, modulation, etc. These options can be realized by
adding additional separate modules or can be
incorporated into the synthesizer core module.
For example, the amplitude and pulse modulators can be either external or internal to the
synthesizer itself (Figure 49), while the phase
and frequency modulation components are
usually included into the synthesizer as a part
of the PLL circuitry.
Test and measurement applications are
50
High Frequency Electronics
Figure 49 · Adding modulation capabilities.
usually associated with big bench-top instruments, which can be found in every engineering lab. Synthetic instrumentation is a costeffective alternative for building complex test
and measurement equipment [48-49]. It
enables the emulation of various traditional
bench-top instruments employed in automatic
test systems using a reconfigurable combination of core hardware components (such as a
signal generator shown in Figure 50).
Figure 50 · VXI signal generator covers 0.01
to 20 GHz.
High Frequency Design
SYNTHESIZER DESIGN
Figure 51 · Microwave synthesizer module for the PXI
platform.
Synthetic instrumentation utilizes various platforms
(VXI, LXI); more recently a lot of effort has been put on
PXI platform, which offers a lower size and cost benefits.
A practical PXI microwave synthesizer example is shown
in Figure 51. It is based on a small (4" × 6" × 1.5") module
that covers 3 to 9 GHz frequency band with 0.1 Hz resolution and less than 500 µs tuning speed. The module construction and design details are presented in [50].
Thus, today’s T&M market requirements demand that
new synthesizers must be faster and smaller; simultaneously their other characteristics (e.g., resolution, phase
noise, spurious) and functionality must be kept unaffected. Since the available space is continuously diminishing,
it requires a certain engineering effort to compact all necessary hardware into available space.
Figure 52 · VCO and YIG oscillator phase noise comparison.
One of the main contributors to the synthesizer speed
and size parameters is the YIG oscillator, which has been
widely used in T&M synthesizers due to its unique lownoise features. Today’s market requirements (specifically,
fast switching speed) encourage the use of VCO-based
technologies, which, however, normally exhibit higher
phase noise.
How can the VCO phase noise be controlled? First,
let’s compare phase noise behavior (Figure 52) of two
hypothetical oscillators (YIG and VCO), which utilize
identical active device arrangement. At very high frequency offsets both oscillators should demonstrate the
same behavior (noise floor) defined by the ratio of the
available RF power and active device thermal noise. The
noise starts degrading at 20 dB/decade rate at lower frequency offsets set by the resonator Q. Clearly, the VCO
demonstrates significantly higher phase noise in comparison with the YIG-oscillator due to the difference in their
resonator Q-factors.
Let’s build a synthesizer using these oscillators or, in
other words, lock them to a low-noise reference source.
What phase noise behavior is expected? A very typical
YIG-based synthesizer phase noise profile is shown in
Figure 53 (blue curve). The reference source noise normally dominates at very low frequency offsets (region 1),
while a relatively flat noise plateau in the region 2 is
mainly due to PLL components (e.g., phase detector,
dividers, etc.) residual noise limitations. Outside the loop
filter bandwidth the noise follows the YIG oscillator freerunning curve (region 3). The loop filter bandwidth is
Figure 53 · Locking VCO and YIG oscillators within the
same PLL bandwidth.
Figure 54 · Locking VCO and YIG oscillators within their
optimal bandwidths.
Removing the YIG
52
High Frequency Electronics
High Frequency Design
SYNTHESIZER DESIGN
Figure 55 · QuickSyn frequency synthesizer.
preferably set at its optimal frequency (which is the cross
point of the PLL multiplied noise and oscillator free-running noise curves) that provides the lowest overall phase
noise response.
Trying to lock the VCO within the same loop bandwidth results in a very ugly noise profile due to excessive
VCO noise at these offsets (Figure 53, red curve). A
smoother phase noise profile can be obtained by locking
the VCO within its own optimal bandwidth as shown in
Figure 54. Nevertheless, it is still much higher in compassion with the YIG-based counterpart. The difference is
indicated as a hatched area in Figure 52 and can be minimized as follows:
Figure 56 · QuickSyn phase noise at 2 GHz output.
provide better phase noise performance (recalculated to
the same output frequency) at offset frequencies up to a
few hundred kHz. A combined reference (OCXO + CRO or
OCXO + DRO) will exceed the YIG-oscillator performance
at any frequency offset. Therefore, the limitations are
mainly set by a PLL residual noise or, in other words, by
a particular synthesizer architecture.
Design Examples
1.
2.
3.
A very low-noise reference source has to be used.
The PLL residual noise floor has to be reduced.
The PLL loop bandwidth has to be extended.
Can a VCO-based design achieve YIG-comparable performance? We have already discussed that today’s OCXOs
54
High Frequency Electronics
A good example demonstrating the indicated above
concept is QuickSyn synthesizer (Figure 55) manufactured by Phase Matrix, Inc. The core model covers 2 to 10
GHz frequency range with about 100 µs tuning speed
using a broadband fundamental VCO. The VCO is locked
to a built-in DDS that provides sub-Hz frequency resolu-
High Frequency Design
SYNTHESIZER DESIGN
tion without the common penalty of slower tuning. Since
DDS-based designs are normally prone to increased spurious content, both hardware and software techniques are
extensively utilized to suppress DDS spurs to negligible
levels (in comparison with more copious PLL reference
spurs). Though PLL spurs dominate, they are easily managed down to about –80 dBc level by optimizing the loop
filter. The VCO phase noise is controlled by utilizing an
ultra low-noise reference OCXO as well as very wide (a
few MHz) loop bandwidth as suggested above. Thus, the
synthesizer phase noise within its PLL filter bandwidth
mainly depends on the multiplied reference noise as well
as residual noise characteristics of the locking mechanism. A novel phase-refining technique (patent pending)
is used to minimize the residual PLL noise floor [51]. The
technique allows inverting the PLL division ratio (i.e.,
applying a multiplier within the PLL feedback path) that
drastically improves both phase noise and spurious characteristics. The typical phase noise measured at the 10
GHz output and 10 kHz offset is –120 dBc/Hz. The phase
noise at the 2 GHz output drops down to –131 dBc/Hz
(Figure 56) that exceeds the performance of traditional
YIG-based synthesizer designs at the same frequency settings. Phase hits (usually inherent to YIGs) are also
56
High Frequency Electronics
Figure 57 · Synthesizer technologies comparison.
reduced due to the use of a low-mass VCO and very wide
loop filter bandwidth.
QuickSyn also offers a great functionality including an
output power calibration and control, various modulation
options (AM, PM, FM, Pulse), external ALC input, independent power and frequency sweep, and list mode. A
built-in power equalizer easily sets a flat or virtually any
desirable output power-to-frequency profile. It is worth
mentioning that these noteworthy
characteristics are compacted into a
relatively small package (5" × 7" × 1")
ideal for a variety of stand alone and
embedded OEM applications.
Future Developments
Microwave synthesizers have
been continuously evolving and will
continue to do so with time. The
advancements will be made through
architecture optimization, as well as
the introduction and improvement of
individual components such as VCOs,
phase detectors, DDS, fractional-N
dividers, etc. What architecture will
gain in popularity? A quick comparison between the most popular architectures is shown in Figure 57. The
direct analog synthesizer is obviously
the most advanced solution providing
unsurpassed tuning speed and phase
noise characteristics. Unfortunately,
today’s direct analog designs are
hardware intensive and, therefore,
are limited to the applications where
fairly high cost can be tolerated.
Although, some cost reduction is
expected with the introduction of
new devices (such as a wideband
DDS), the most practical near-term
developments are likely to be associated with multiloop VCO-based
designs. Much of the progress here
will be brought by reduction of the
PLL residual noise characteristics
and simultaneous extension of the
PLL bandwidth (targeting the VCO
noise floor region). Equipping the
synthesizer with a low-noise reference will provide very fast microseconds tuning speed with a “YIGgrade” noise performance at much
lower cost in comparison with traditional direct analog and YIG-based
techniques. The continuous performance improvement, functionality
extension, reduction in cost and size
are targets for the new synthesizer
designs.
References
48. M. Granieri, “Synthetic
Instrumentation: An Emerging Tech-
nology,” RF Design, February 2004,
pp. 16-25.
49. D. Menzer, “Synthetic
Instruments: A New Horizon,”
Microwave Journal, March 2006, pp.
22-36.
50. A. Chenakin and S. Ojha, “A
Small Form Factor 3-9 GHz
Synthesizer Module for Use in
Synthetic Instrumentation Applications,” Microwave Product Digest,
April 2008, pp. 58-62.
51. A. Chenakin, “Method for Low
Phase Noise Frequency Synthesis,”
patent pending.
Author Information
Dr. Alexander
Chenakin is the
Director of the
F r e q u e n c y
Synthesis Group
at Phase Matrix,
Inc., (www.phasematrix.com)
where he oversees the development of advanced frequency synthesizer products for test
and measurement applications. He
earned his degree from Kiev
Polytechnic Institute and has worked
in a variety of technical and managerial positions around the world. He
has led the development of advanced
products for Celeritek, Nextek, Micro
Lambda Wireless, General Electronic
Devices, and other companies. His
professional achievements have been
widely presented in professional magazines and international conferences.
Dr. Chenakin was also a lecturer for
the 2008 IEEE International
Frequency Control Symposium tutorials. He can be reached by phone at
408-954-6409 or by e-mail at
achenakin@phasematrix.com.
Editor’s Note
The first four parts of this series
on synthesizer design are now available online in the Archives section of
www.highfrequencyelectronics.com.
This final part will be placed in the
archives in mid-October.